octeon_edac-pci.c 2.7 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 Cavium, Inc.
  7. * Copyright (C) 2009 Wind River Systems,
  8. * written by Ralf Baechle <ralf@linux-mips.org>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/slab.h>
  13. #include <linux/io.h>
  14. #include <linux/edac.h>
  15. #include <asm/octeon/cvmx.h>
  16. #include <asm/octeon/cvmx-npi-defs.h>
  17. #include <asm/octeon/cvmx-pci-defs.h>
  18. #include <asm/octeon/octeon.h>
  19. #include "edac_module.h"
  20. static void octeon_pci_poll(struct edac_pci_ctl_info *pci)
  21. {
  22. union cvmx_pci_cfg01 cfg01;
  23. cfg01.u32 = octeon_npi_read32(CVMX_NPI_PCI_CFG01);
  24. if (cfg01.s.dpe) { /* Detected parity error */
  25. edac_pci_handle_pe(pci, pci->ctl_name);
  26. cfg01.s.dpe = 1; /* Reset */
  27. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  28. }
  29. if (cfg01.s.sse) {
  30. edac_pci_handle_npe(pci, "Signaled System Error");
  31. cfg01.s.sse = 1; /* Reset */
  32. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  33. }
  34. if (cfg01.s.rma) {
  35. edac_pci_handle_npe(pci, "Received Master Abort");
  36. cfg01.s.rma = 1; /* Reset */
  37. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  38. }
  39. if (cfg01.s.rta) {
  40. edac_pci_handle_npe(pci, "Received Target Abort");
  41. cfg01.s.rta = 1; /* Reset */
  42. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  43. }
  44. if (cfg01.s.sta) {
  45. edac_pci_handle_npe(pci, "Signaled Target Abort");
  46. cfg01.s.sta = 1; /* Reset */
  47. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  48. }
  49. if (cfg01.s.mdpe) {
  50. edac_pci_handle_npe(pci, "Master Data Parity Error");
  51. cfg01.s.mdpe = 1; /* Reset */
  52. octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
  53. }
  54. }
  55. static int octeon_pci_probe(struct platform_device *pdev)
  56. {
  57. struct edac_pci_ctl_info *pci;
  58. int res = 0;
  59. pci = edac_pci_alloc_ctl_info(0, "octeon_pci_err");
  60. if (!pci)
  61. return -ENOMEM;
  62. pci->dev = &pdev->dev;
  63. platform_set_drvdata(pdev, pci);
  64. pci->dev_name = dev_name(&pdev->dev);
  65. pci->mod_name = "octeon-pci";
  66. pci->ctl_name = "octeon_pci_err";
  67. pci->edac_check = octeon_pci_poll;
  68. if (edac_pci_add_device(pci, 0) > 0) {
  69. pr_err("%s: edac_pci_add_device() failed\n", __func__);
  70. goto err;
  71. }
  72. return 0;
  73. err:
  74. edac_pci_free_ctl_info(pci);
  75. return res;
  76. }
  77. static int octeon_pci_remove(struct platform_device *pdev)
  78. {
  79. struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
  80. edac_pci_del_device(&pdev->dev);
  81. edac_pci_free_ctl_info(pci);
  82. return 0;
  83. }
  84. static struct platform_driver octeon_pci_driver = {
  85. .probe = octeon_pci_probe,
  86. .remove = octeon_pci_remove,
  87. .driver = {
  88. .name = "octeon_pci_edac",
  89. }
  90. };
  91. module_platform_driver(octeon_pci_driver);
  92. MODULE_LICENSE("GPL");
  93. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");