octeon_edac-pc.c 3.5 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 Cavium, Inc.
  7. *
  8. * Copyright (C) 2009 Wind River Systems,
  9. * written by Ralf Baechle <ralf@linux-mips.org>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/slab.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/edac.h>
  17. #include "edac_module.h"
  18. #include <asm/octeon/cvmx.h>
  19. #include <asm/mipsregs.h>
  20. extern int register_co_cache_error_notifier(struct notifier_block *nb);
  21. extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
  22. extern unsigned long long cache_err_dcache[NR_CPUS];
  23. struct co_cache_error {
  24. struct notifier_block notifier;
  25. struct edac_device_ctl_info *ed;
  26. };
  27. /**
  28. * EDAC CPU cache error callback
  29. *
  30. * @event: non-zero if unrecoverable.
  31. */
  32. static int co_cache_error_event(struct notifier_block *this,
  33. unsigned long event, void *ptr)
  34. {
  35. struct co_cache_error *p = container_of(this, struct co_cache_error,
  36. notifier);
  37. unsigned int core = cvmx_get_core_num();
  38. unsigned int cpu = smp_processor_id();
  39. u64 icache_err = read_octeon_c0_icacheerr();
  40. u64 dcache_err;
  41. if (event) {
  42. dcache_err = cache_err_dcache[core];
  43. cache_err_dcache[core] = 0;
  44. } else {
  45. dcache_err = read_octeon_c0_dcacheerr();
  46. }
  47. if (icache_err & 1) {
  48. edac_device_printk(p->ed, KERN_ERR,
  49. "CacheErr (Icache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n",
  50. (unsigned long long)icache_err, core, cpu,
  51. read_c0_errorepc());
  52. write_octeon_c0_icacheerr(0);
  53. edac_device_handle_ce(p->ed, cpu, 1, "icache");
  54. }
  55. if (dcache_err & 1) {
  56. edac_device_printk(p->ed, KERN_ERR,
  57. "CacheErr (Dcache):%llx, core %d/cpu %d, cp0_errorepc == %lx\n",
  58. (unsigned long long)dcache_err, core, cpu,
  59. read_c0_errorepc());
  60. if (event)
  61. edac_device_handle_ue(p->ed, cpu, 0, "dcache");
  62. else
  63. edac_device_handle_ce(p->ed, cpu, 0, "dcache");
  64. /* Clear the error indication */
  65. if (OCTEON_IS_OCTEON2())
  66. write_octeon_c0_dcacheerr(1);
  67. else
  68. write_octeon_c0_dcacheerr(0);
  69. }
  70. return NOTIFY_STOP;
  71. }
  72. static int co_cache_error_probe(struct platform_device *pdev)
  73. {
  74. struct co_cache_error *p = devm_kzalloc(&pdev->dev, sizeof(*p),
  75. GFP_KERNEL);
  76. if (!p)
  77. return -ENOMEM;
  78. p->notifier.notifier_call = co_cache_error_event;
  79. platform_set_drvdata(pdev, p);
  80. p->ed = edac_device_alloc_ctl_info(0, "cpu", num_possible_cpus(),
  81. "cache", 2, 0, NULL, 0,
  82. edac_device_alloc_index());
  83. if (!p->ed)
  84. goto err;
  85. p->ed->dev = &pdev->dev;
  86. p->ed->dev_name = dev_name(&pdev->dev);
  87. p->ed->mod_name = "octeon-cpu";
  88. p->ed->ctl_name = "cache";
  89. if (edac_device_add_device(p->ed)) {
  90. pr_err("%s: edac_device_add_device() failed\n", __func__);
  91. goto err1;
  92. }
  93. register_co_cache_error_notifier(&p->notifier);
  94. return 0;
  95. err1:
  96. edac_device_free_ctl_info(p->ed);
  97. err:
  98. return -ENXIO;
  99. }
  100. static int co_cache_error_remove(struct platform_device *pdev)
  101. {
  102. struct co_cache_error *p = platform_get_drvdata(pdev);
  103. unregister_co_cache_error_notifier(&p->notifier);
  104. edac_device_del_device(&pdev->dev);
  105. edac_device_free_ctl_info(p->ed);
  106. return 0;
  107. }
  108. static struct platform_driver co_cache_error_driver = {
  109. .probe = co_cache_error_probe,
  110. .remove = co_cache_error_remove,
  111. .driver = {
  112. .name = "octeon_pc_edac",
  113. }
  114. };
  115. module_platform_driver(co_cache_error_driver);
  116. MODULE_LICENSE("GPL");
  117. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");