mt2701-cs42448.c 12 KB

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  1. /*
  2. * mt2701-cs42448.c -- MT2701 CS42448 ALSA SoC machine driver
  3. *
  4. * Copyright (c) 2016 MediaTek Inc.
  5. * Author: Ir Lian <ir.lian@mediatek.com>
  6. * Garlic Tseng <garlic.tseng@mediatek.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 and
  11. * only version 2 as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/module.h>
  19. #include <sound/soc.h>
  20. #include <linux/delay.h>
  21. #include <linux/gpio.h>
  22. #include <linux/pinctrl/consumer.h>
  23. #include <linux/of_gpio.h>
  24. #include "mt2701-afe-common.h"
  25. struct mt2701_cs42448_private {
  26. int i2s1_in_mux;
  27. int i2s1_in_mux_gpio_sel_1;
  28. int i2s1_in_mux_gpio_sel_2;
  29. };
  30. static const char * const i2sin_mux_switch_text[] = {
  31. "ADC_SDOUT2",
  32. "ADC_SDOUT3",
  33. "I2S_IN_1",
  34. "I2S_IN_2",
  35. };
  36. static const struct soc_enum i2sin_mux_enum =
  37. SOC_ENUM_SINGLE_EXT(4, i2sin_mux_switch_text);
  38. static int mt2701_cs42448_i2sin1_mux_get(struct snd_kcontrol *kcontrol,
  39. struct snd_ctl_elem_value *ucontrol)
  40. {
  41. struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
  42. struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
  43. ucontrol->value.integer.value[0] = priv->i2s1_in_mux;
  44. return 0;
  45. }
  46. static int mt2701_cs42448_i2sin1_mux_set(struct snd_kcontrol *kcontrol,
  47. struct snd_ctl_elem_value *ucontrol)
  48. {
  49. struct snd_soc_card *card = snd_kcontrol_chip(kcontrol);
  50. struct mt2701_cs42448_private *priv = snd_soc_card_get_drvdata(card);
  51. if (ucontrol->value.integer.value[0] == priv->i2s1_in_mux)
  52. return 0;
  53. switch (ucontrol->value.integer.value[0]) {
  54. case 0:
  55. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
  56. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
  57. break;
  58. case 1:
  59. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
  60. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 0);
  61. break;
  62. case 2:
  63. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 0);
  64. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
  65. break;
  66. case 3:
  67. gpio_set_value(priv->i2s1_in_mux_gpio_sel_1, 1);
  68. gpio_set_value(priv->i2s1_in_mux_gpio_sel_2, 1);
  69. break;
  70. default:
  71. dev_warn(card->dev, "%s invalid setting\n", __func__);
  72. }
  73. priv->i2s1_in_mux = ucontrol->value.integer.value[0];
  74. return 0;
  75. }
  76. static const struct snd_soc_dapm_widget
  77. mt2701_cs42448_asoc_card_dapm_widgets[] = {
  78. SND_SOC_DAPM_LINE("Line Out Jack", NULL),
  79. SND_SOC_DAPM_MIC("AMIC", NULL),
  80. SND_SOC_DAPM_LINE("Tuner In", NULL),
  81. SND_SOC_DAPM_LINE("Satellite Tuner In", NULL),
  82. SND_SOC_DAPM_LINE("AUX In", NULL),
  83. };
  84. static const struct snd_kcontrol_new mt2701_cs42448_controls[] = {
  85. SOC_DAPM_PIN_SWITCH("Line Out Jack"),
  86. SOC_DAPM_PIN_SWITCH("AMIC"),
  87. SOC_DAPM_PIN_SWITCH("Tuner In"),
  88. SOC_DAPM_PIN_SWITCH("Satellite Tuner In"),
  89. SOC_DAPM_PIN_SWITCH("AUX In"),
  90. SOC_ENUM_EXT("I2SIN1_MUX_Switch", i2sin_mux_enum,
  91. mt2701_cs42448_i2sin1_mux_get,
  92. mt2701_cs42448_i2sin1_mux_set),
  93. };
  94. static const unsigned int mt2701_cs42448_sampling_rates[] = {48000};
  95. static struct snd_pcm_hw_constraint_list mt2701_cs42448_constraints_rates = {
  96. .count = ARRAY_SIZE(mt2701_cs42448_sampling_rates),
  97. .list = mt2701_cs42448_sampling_rates,
  98. .mask = 0,
  99. };
  100. static int mt2701_cs42448_fe_ops_startup(struct snd_pcm_substream *substream)
  101. {
  102. int err;
  103. err = snd_pcm_hw_constraint_list(substream->runtime, 0,
  104. SNDRV_PCM_HW_PARAM_RATE,
  105. &mt2701_cs42448_constraints_rates);
  106. if (err < 0) {
  107. dev_err(substream->pcm->card->dev,
  108. "%s snd_pcm_hw_constraint_list failed: 0x%x\n",
  109. __func__, err);
  110. return err;
  111. }
  112. return 0;
  113. }
  114. static struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
  115. .startup = mt2701_cs42448_fe_ops_startup,
  116. };
  117. static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
  118. struct snd_pcm_hw_params *params)
  119. {
  120. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  121. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  122. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  123. unsigned int mclk_rate;
  124. unsigned int rate = params_rate(params);
  125. unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
  126. unsigned int div_bck_over_lrck = 64;
  127. mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
  128. /* mt2701 mclk */
  129. snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, SND_SOC_CLOCK_OUT);
  130. /* codec mclk */
  131. snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, SND_SOC_CLOCK_IN);
  132. return 0;
  133. }
  134. static struct snd_soc_ops mt2701_cs42448_be_ops = {
  135. .hw_params = mt2701_cs42448_be_ops_hw_params
  136. };
  137. enum {
  138. DAI_LINK_FE_MULTI_CH_OUT,
  139. DAI_LINK_FE_PCM0_IN,
  140. DAI_LINK_FE_PCM1_IN,
  141. DAI_LINK_FE_BT_OUT,
  142. DAI_LINK_FE_BT_IN,
  143. DAI_LINK_BE_I2S0,
  144. DAI_LINK_BE_I2S1,
  145. DAI_LINK_BE_I2S2,
  146. DAI_LINK_BE_I2S3,
  147. DAI_LINK_BE_MRG_BT,
  148. };
  149. static struct snd_soc_dai_link mt2701_cs42448_dai_links[] = {
  150. /* FE */
  151. [DAI_LINK_FE_MULTI_CH_OUT] = {
  152. .name = "mt2701-cs42448-multi-ch-out",
  153. .stream_name = "mt2701-cs42448-multi-ch-out",
  154. .cpu_dai_name = "PCM_multi",
  155. .codec_name = "snd-soc-dummy",
  156. .codec_dai_name = "snd-soc-dummy-dai",
  157. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  158. SND_SOC_DPCM_TRIGGER_POST},
  159. .ops = &mt2701_cs42448_48k_fe_ops,
  160. .dynamic = 1,
  161. .dpcm_playback = 1,
  162. },
  163. [DAI_LINK_FE_PCM0_IN] = {
  164. .name = "mt2701-cs42448-pcm0",
  165. .stream_name = "mt2701-cs42448-pcm0-data-UL",
  166. .cpu_dai_name = "PCM0",
  167. .codec_name = "snd-soc-dummy",
  168. .codec_dai_name = "snd-soc-dummy-dai",
  169. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  170. SND_SOC_DPCM_TRIGGER_POST},
  171. .ops = &mt2701_cs42448_48k_fe_ops,
  172. .dynamic = 1,
  173. .dpcm_capture = 1,
  174. },
  175. [DAI_LINK_FE_PCM1_IN] = {
  176. .name = "mt2701-cs42448-pcm1-data-UL",
  177. .stream_name = "mt2701-cs42448-pcm1-data-UL",
  178. .cpu_dai_name = "PCM1",
  179. .codec_name = "snd-soc-dummy",
  180. .codec_dai_name = "snd-soc-dummy-dai",
  181. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  182. SND_SOC_DPCM_TRIGGER_POST},
  183. .ops = &mt2701_cs42448_48k_fe_ops,
  184. .dynamic = 1,
  185. .dpcm_capture = 1,
  186. },
  187. [DAI_LINK_FE_BT_OUT] = {
  188. .name = "mt2701-cs42448-pcm-BT-out",
  189. .stream_name = "mt2701-cs42448-pcm-BT",
  190. .cpu_dai_name = "PCM_BT_DL",
  191. .codec_name = "snd-soc-dummy",
  192. .codec_dai_name = "snd-soc-dummy-dai",
  193. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  194. SND_SOC_DPCM_TRIGGER_POST},
  195. .dynamic = 1,
  196. .dpcm_playback = 1,
  197. },
  198. [DAI_LINK_FE_BT_IN] = {
  199. .name = "mt2701-cs42448-pcm-BT-in",
  200. .stream_name = "mt2701-cs42448-pcm-BT",
  201. .cpu_dai_name = "PCM_BT_UL",
  202. .codec_name = "snd-soc-dummy",
  203. .codec_dai_name = "snd-soc-dummy-dai",
  204. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  205. SND_SOC_DPCM_TRIGGER_POST},
  206. .dynamic = 1,
  207. .dpcm_capture = 1,
  208. },
  209. /* BE */
  210. [DAI_LINK_BE_I2S0] = {
  211. .name = "mt2701-cs42448-I2S0",
  212. .cpu_dai_name = "I2S0",
  213. .no_pcm = 1,
  214. .codec_dai_name = "cs42448",
  215. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  216. | SND_SOC_DAIFMT_GATED,
  217. .ops = &mt2701_cs42448_be_ops,
  218. .dpcm_playback = 1,
  219. .dpcm_capture = 1,
  220. },
  221. [DAI_LINK_BE_I2S1] = {
  222. .name = "mt2701-cs42448-I2S1",
  223. .cpu_dai_name = "I2S1",
  224. .no_pcm = 1,
  225. .codec_dai_name = "cs42448",
  226. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  227. | SND_SOC_DAIFMT_GATED,
  228. .ops = &mt2701_cs42448_be_ops,
  229. .dpcm_playback = 1,
  230. .dpcm_capture = 1,
  231. },
  232. [DAI_LINK_BE_I2S2] = {
  233. .name = "mt2701-cs42448-I2S2",
  234. .cpu_dai_name = "I2S2",
  235. .no_pcm = 1,
  236. .codec_dai_name = "cs42448",
  237. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  238. | SND_SOC_DAIFMT_GATED,
  239. .ops = &mt2701_cs42448_be_ops,
  240. .dpcm_playback = 1,
  241. .dpcm_capture = 1,
  242. },
  243. [DAI_LINK_BE_I2S3] = {
  244. .name = "mt2701-cs42448-I2S3",
  245. .cpu_dai_name = "I2S3",
  246. .no_pcm = 1,
  247. .codec_dai_name = "cs42448",
  248. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS
  249. | SND_SOC_DAIFMT_GATED,
  250. .ops = &mt2701_cs42448_be_ops,
  251. .dpcm_playback = 1,
  252. .dpcm_capture = 1,
  253. },
  254. [DAI_LINK_BE_MRG_BT] = {
  255. .name = "mt2701-cs42448-MRG-BT",
  256. .cpu_dai_name = "MRG BT",
  257. .no_pcm = 1,
  258. .codec_dai_name = "bt-sco-pcm-wb",
  259. .dpcm_playback = 1,
  260. .dpcm_capture = 1,
  261. },
  262. };
  263. static struct snd_soc_card mt2701_cs42448_soc_card = {
  264. .name = "mt2701-cs42448",
  265. .owner = THIS_MODULE,
  266. .dai_link = mt2701_cs42448_dai_links,
  267. .num_links = ARRAY_SIZE(mt2701_cs42448_dai_links),
  268. .controls = mt2701_cs42448_controls,
  269. .num_controls = ARRAY_SIZE(mt2701_cs42448_controls),
  270. .dapm_widgets = mt2701_cs42448_asoc_card_dapm_widgets,
  271. .num_dapm_widgets = ARRAY_SIZE(mt2701_cs42448_asoc_card_dapm_widgets),
  272. };
  273. static int mt2701_cs42448_machine_probe(struct platform_device *pdev)
  274. {
  275. struct snd_soc_card *card = &mt2701_cs42448_soc_card;
  276. int ret;
  277. int i;
  278. struct device_node *platform_node, *codec_node, *codec_node_bt_mrg;
  279. struct mt2701_cs42448_private *priv =
  280. devm_kzalloc(&pdev->dev, sizeof(struct mt2701_cs42448_private),
  281. GFP_KERNEL);
  282. struct device *dev = &pdev->dev;
  283. if (!priv)
  284. return -ENOMEM;
  285. platform_node = of_parse_phandle(pdev->dev.of_node,
  286. "mediatek,platform", 0);
  287. if (!platform_node) {
  288. dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
  289. return -EINVAL;
  290. }
  291. for (i = 0; i < card->num_links; i++) {
  292. if (mt2701_cs42448_dai_links[i].platform_name)
  293. continue;
  294. mt2701_cs42448_dai_links[i].platform_of_node = platform_node;
  295. }
  296. card->dev = dev;
  297. codec_node = of_parse_phandle(pdev->dev.of_node,
  298. "mediatek,audio-codec", 0);
  299. if (!codec_node) {
  300. dev_err(&pdev->dev,
  301. "Property 'audio-codec' missing or invalid\n");
  302. return -EINVAL;
  303. }
  304. for (i = 0; i < card->num_links; i++) {
  305. if (mt2701_cs42448_dai_links[i].codec_name)
  306. continue;
  307. mt2701_cs42448_dai_links[i].codec_of_node = codec_node;
  308. }
  309. codec_node_bt_mrg = of_parse_phandle(pdev->dev.of_node,
  310. "mediatek,audio-codec-bt-mrg", 0);
  311. if (!codec_node_bt_mrg) {
  312. dev_err(&pdev->dev,
  313. "Property 'audio-codec-bt-mrg' missing or invalid\n");
  314. return -EINVAL;
  315. }
  316. mt2701_cs42448_dai_links[DAI_LINK_BE_MRG_BT].codec_of_node
  317. = codec_node_bt_mrg;
  318. ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
  319. if (ret) {
  320. dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
  321. return ret;
  322. }
  323. priv->i2s1_in_mux_gpio_sel_1 =
  324. of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio1", 0);
  325. if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_1)) {
  326. ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_1,
  327. "i2s1_in_mux_gpio_sel_1");
  328. if (ret)
  329. dev_warn(&pdev->dev, "%s devm_gpio_request fail %d\n",
  330. __func__, ret);
  331. gpio_direction_output(priv->i2s1_in_mux_gpio_sel_1, 0);
  332. }
  333. priv->i2s1_in_mux_gpio_sel_2 =
  334. of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio2", 0);
  335. if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_2)) {
  336. ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_2,
  337. "i2s1_in_mux_gpio_sel_2");
  338. if (ret)
  339. dev_warn(&pdev->dev, "%s devm_gpio_request fail2 %d\n",
  340. __func__, ret);
  341. gpio_direction_output(priv->i2s1_in_mux_gpio_sel_2, 0);
  342. }
  343. snd_soc_card_set_drvdata(card, priv);
  344. ret = devm_snd_soc_register_card(&pdev->dev, card);
  345. if (ret)
  346. dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
  347. __func__, ret);
  348. return ret;
  349. }
  350. #ifdef CONFIG_OF
  351. static const struct of_device_id mt2701_cs42448_machine_dt_match[] = {
  352. {.compatible = "mediatek,mt2701-cs42448-machine",},
  353. {}
  354. };
  355. #endif
  356. static struct platform_driver mt2701_cs42448_machine = {
  357. .driver = {
  358. .name = "mt2701-cs42448",
  359. #ifdef CONFIG_OF
  360. .of_match_table = mt2701_cs42448_machine_dt_match,
  361. #endif
  362. },
  363. .probe = mt2701_cs42448_machine_probe,
  364. };
  365. module_platform_driver(mt2701_cs42448_machine);
  366. /* Module information */
  367. MODULE_DESCRIPTION("MT2701 CS42448 ALSA SoC machine driver");
  368. MODULE_AUTHOR("Ir Lian <ir.lian@mediatek.com>");
  369. MODULE_LICENSE("GPL v2");
  370. MODULE_ALIAS("mt2701 cs42448 soc card");