rt5651.c 55 KB

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  1. /*
  2. * rt5651.c -- RT5651 ALSA SoC audio codec driver
  3. *
  4. * Copyright 2014 Realtek Semiconductor Corp.
  5. * Author: Bard Liao <bardliao@realtek.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/regmap.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/acpi.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include "rl6231.h"
  29. #include "rt5651.h"
  30. #define RT5651_DEVICE_ID_VALUE 0x6281
  31. #define RT5651_PR_RANGE_BASE (0xff + 1)
  32. #define RT5651_PR_SPACING 0x100
  33. #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
  34. static const struct regmap_range_cfg rt5651_ranges[] = {
  35. { .name = "PR", .range_min = RT5651_PR_BASE,
  36. .range_max = RT5651_PR_BASE + 0xb4,
  37. .selector_reg = RT5651_PRIV_INDEX,
  38. .selector_mask = 0xff,
  39. .selector_shift = 0x0,
  40. .window_start = RT5651_PRIV_DATA,
  41. .window_len = 0x1, },
  42. };
  43. static const struct reg_sequence init_list[] = {
  44. {RT5651_PR_BASE + 0x3d, 0x3e00},
  45. };
  46. static const struct reg_default rt5651_reg[] = {
  47. { 0x00, 0x0000 },
  48. { 0x02, 0xc8c8 },
  49. { 0x03, 0xc8c8 },
  50. { 0x05, 0x0000 },
  51. { 0x0d, 0x0000 },
  52. { 0x0e, 0x0000 },
  53. { 0x0f, 0x0808 },
  54. { 0x10, 0x0808 },
  55. { 0x19, 0xafaf },
  56. { 0x1a, 0xafaf },
  57. { 0x1b, 0x0c00 },
  58. { 0x1c, 0x2f2f },
  59. { 0x1d, 0x2f2f },
  60. { 0x1e, 0x0000 },
  61. { 0x27, 0x7860 },
  62. { 0x28, 0x7070 },
  63. { 0x29, 0x8080 },
  64. { 0x2a, 0x5252 },
  65. { 0x2b, 0x5454 },
  66. { 0x2f, 0x0000 },
  67. { 0x30, 0x5000 },
  68. { 0x3b, 0x0000 },
  69. { 0x3c, 0x006f },
  70. { 0x3d, 0x0000 },
  71. { 0x3e, 0x006f },
  72. { 0x45, 0x6000 },
  73. { 0x4d, 0x0000 },
  74. { 0x4e, 0x0000 },
  75. { 0x4f, 0x0279 },
  76. { 0x50, 0x0000 },
  77. { 0x51, 0x0000 },
  78. { 0x52, 0x0279 },
  79. { 0x53, 0xf000 },
  80. { 0x61, 0x0000 },
  81. { 0x62, 0x0000 },
  82. { 0x63, 0x00c0 },
  83. { 0x64, 0x0000 },
  84. { 0x65, 0x0000 },
  85. { 0x66, 0x0000 },
  86. { 0x70, 0x8000 },
  87. { 0x71, 0x8000 },
  88. { 0x73, 0x1104 },
  89. { 0x74, 0x0c00 },
  90. { 0x75, 0x1400 },
  91. { 0x77, 0x0c00 },
  92. { 0x78, 0x4000 },
  93. { 0x79, 0x0123 },
  94. { 0x80, 0x0000 },
  95. { 0x81, 0x0000 },
  96. { 0x82, 0x0000 },
  97. { 0x83, 0x0800 },
  98. { 0x84, 0x0000 },
  99. { 0x85, 0x0008 },
  100. { 0x89, 0x0000 },
  101. { 0x8e, 0x0004 },
  102. { 0x8f, 0x1100 },
  103. { 0x90, 0x0000 },
  104. { 0x93, 0x2000 },
  105. { 0x94, 0x0200 },
  106. { 0xb0, 0x2080 },
  107. { 0xb1, 0x0000 },
  108. { 0xb4, 0x2206 },
  109. { 0xb5, 0x1f00 },
  110. { 0xb6, 0x0000 },
  111. { 0xbb, 0x0000 },
  112. { 0xbc, 0x0000 },
  113. { 0xbd, 0x0000 },
  114. { 0xbe, 0x0000 },
  115. { 0xbf, 0x0000 },
  116. { 0xc0, 0x0400 },
  117. { 0xc1, 0x0000 },
  118. { 0xc2, 0x0000 },
  119. { 0xcf, 0x0013 },
  120. { 0xd0, 0x0680 },
  121. { 0xd1, 0x1c17 },
  122. { 0xd3, 0xb320 },
  123. { 0xd9, 0x0809 },
  124. { 0xfa, 0x0010 },
  125. { 0xfe, 0x10ec },
  126. { 0xff, 0x6281 },
  127. };
  128. static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
  129. {
  130. int i;
  131. for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
  132. if ((reg >= rt5651_ranges[i].window_start &&
  133. reg <= rt5651_ranges[i].window_start +
  134. rt5651_ranges[i].window_len) ||
  135. (reg >= rt5651_ranges[i].range_min &&
  136. reg <= rt5651_ranges[i].range_max)) {
  137. return true;
  138. }
  139. }
  140. switch (reg) {
  141. case RT5651_RESET:
  142. case RT5651_PRIV_DATA:
  143. case RT5651_EQ_CTRL1:
  144. case RT5651_ALC_1:
  145. case RT5651_IRQ_CTRL2:
  146. case RT5651_INT_IRQ_ST:
  147. case RT5651_PGM_REG_ARR1:
  148. case RT5651_PGM_REG_ARR3:
  149. case RT5651_VENDOR_ID:
  150. case RT5651_DEVICE_ID:
  151. return true;
  152. default:
  153. return false;
  154. }
  155. }
  156. static bool rt5651_readable_register(struct device *dev, unsigned int reg)
  157. {
  158. int i;
  159. for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
  160. if ((reg >= rt5651_ranges[i].window_start &&
  161. reg <= rt5651_ranges[i].window_start +
  162. rt5651_ranges[i].window_len) ||
  163. (reg >= rt5651_ranges[i].range_min &&
  164. reg <= rt5651_ranges[i].range_max)) {
  165. return true;
  166. }
  167. }
  168. switch (reg) {
  169. case RT5651_RESET:
  170. case RT5651_VERSION_ID:
  171. case RT5651_VENDOR_ID:
  172. case RT5651_DEVICE_ID:
  173. case RT5651_HP_VOL:
  174. case RT5651_LOUT_CTRL1:
  175. case RT5651_LOUT_CTRL2:
  176. case RT5651_IN1_IN2:
  177. case RT5651_IN3:
  178. case RT5651_INL1_INR1_VOL:
  179. case RT5651_INL2_INR2_VOL:
  180. case RT5651_DAC1_DIG_VOL:
  181. case RT5651_DAC2_DIG_VOL:
  182. case RT5651_DAC2_CTRL:
  183. case RT5651_ADC_DIG_VOL:
  184. case RT5651_ADC_DATA:
  185. case RT5651_ADC_BST_VOL:
  186. case RT5651_STO1_ADC_MIXER:
  187. case RT5651_STO2_ADC_MIXER:
  188. case RT5651_AD_DA_MIXER:
  189. case RT5651_STO_DAC_MIXER:
  190. case RT5651_DD_MIXER:
  191. case RT5651_DIG_INF_DATA:
  192. case RT5651_PDM_CTL:
  193. case RT5651_REC_L1_MIXER:
  194. case RT5651_REC_L2_MIXER:
  195. case RT5651_REC_R1_MIXER:
  196. case RT5651_REC_R2_MIXER:
  197. case RT5651_HPO_MIXER:
  198. case RT5651_OUT_L1_MIXER:
  199. case RT5651_OUT_L2_MIXER:
  200. case RT5651_OUT_L3_MIXER:
  201. case RT5651_OUT_R1_MIXER:
  202. case RT5651_OUT_R2_MIXER:
  203. case RT5651_OUT_R3_MIXER:
  204. case RT5651_LOUT_MIXER:
  205. case RT5651_PWR_DIG1:
  206. case RT5651_PWR_DIG2:
  207. case RT5651_PWR_ANLG1:
  208. case RT5651_PWR_ANLG2:
  209. case RT5651_PWR_MIXER:
  210. case RT5651_PWR_VOL:
  211. case RT5651_PRIV_INDEX:
  212. case RT5651_PRIV_DATA:
  213. case RT5651_I2S1_SDP:
  214. case RT5651_I2S2_SDP:
  215. case RT5651_ADDA_CLK1:
  216. case RT5651_ADDA_CLK2:
  217. case RT5651_DMIC:
  218. case RT5651_TDM_CTL_1:
  219. case RT5651_TDM_CTL_2:
  220. case RT5651_TDM_CTL_3:
  221. case RT5651_GLB_CLK:
  222. case RT5651_PLL_CTRL1:
  223. case RT5651_PLL_CTRL2:
  224. case RT5651_PLL_MODE_1:
  225. case RT5651_PLL_MODE_2:
  226. case RT5651_PLL_MODE_3:
  227. case RT5651_PLL_MODE_4:
  228. case RT5651_PLL_MODE_5:
  229. case RT5651_PLL_MODE_6:
  230. case RT5651_PLL_MODE_7:
  231. case RT5651_DEPOP_M1:
  232. case RT5651_DEPOP_M2:
  233. case RT5651_DEPOP_M3:
  234. case RT5651_CHARGE_PUMP:
  235. case RT5651_MICBIAS:
  236. case RT5651_A_JD_CTL1:
  237. case RT5651_EQ_CTRL1:
  238. case RT5651_EQ_CTRL2:
  239. case RT5651_ALC_1:
  240. case RT5651_ALC_2:
  241. case RT5651_ALC_3:
  242. case RT5651_JD_CTRL1:
  243. case RT5651_JD_CTRL2:
  244. case RT5651_IRQ_CTRL1:
  245. case RT5651_IRQ_CTRL2:
  246. case RT5651_INT_IRQ_ST:
  247. case RT5651_GPIO_CTRL1:
  248. case RT5651_GPIO_CTRL2:
  249. case RT5651_GPIO_CTRL3:
  250. case RT5651_PGM_REG_ARR1:
  251. case RT5651_PGM_REG_ARR2:
  252. case RT5651_PGM_REG_ARR3:
  253. case RT5651_PGM_REG_ARR4:
  254. case RT5651_PGM_REG_ARR5:
  255. case RT5651_SCB_FUNC:
  256. case RT5651_SCB_CTRL:
  257. case RT5651_BASE_BACK:
  258. case RT5651_MP3_PLUS1:
  259. case RT5651_MP3_PLUS2:
  260. case RT5651_ADJ_HPF_CTRL1:
  261. case RT5651_ADJ_HPF_CTRL2:
  262. case RT5651_HP_CALIB_AMP_DET:
  263. case RT5651_HP_CALIB2:
  264. case RT5651_SV_ZCD1:
  265. case RT5651_SV_ZCD2:
  266. case RT5651_D_MISC:
  267. case RT5651_DUMMY2:
  268. case RT5651_DUMMY3:
  269. return true;
  270. default:
  271. return false;
  272. }
  273. }
  274. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
  275. static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
  276. static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
  277. static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
  278. static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
  279. /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
  280. static const DECLARE_TLV_DB_RANGE(bst_tlv,
  281. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  282. 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
  283. 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
  284. 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
  285. 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
  286. 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
  287. 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
  288. );
  289. /* Interface data select */
  290. static const char * const rt5651_data_select[] = {
  291. "Normal", "Swap", "left copy to right", "right copy to left"};
  292. static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
  293. RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
  294. static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
  295. RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
  296. static const struct snd_kcontrol_new rt5651_snd_controls[] = {
  297. /* Headphone Output Volume */
  298. SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
  299. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
  300. /* OUTPUT Control */
  301. SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
  302. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
  303. /* DAC Digital Volume */
  304. SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
  305. RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
  306. SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
  307. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  308. 175, 0, dac_vol_tlv),
  309. SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
  310. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  311. 175, 0, dac_vol_tlv),
  312. /* IN1/IN2 Control */
  313. SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
  314. RT5651_BST_SFT1, 8, 0, bst_tlv),
  315. SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
  316. RT5651_BST_SFT2, 8, 0, bst_tlv),
  317. /* INL/INR Volume Control */
  318. SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
  319. RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
  320. 31, 1, in_vol_tlv),
  321. /* ADC Digital Volume Control */
  322. SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
  323. RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
  324. SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
  325. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  326. 127, 0, adc_vol_tlv),
  327. SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
  328. RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
  329. 127, 0, adc_vol_tlv),
  330. /* ADC Boost Volume Control */
  331. SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
  332. RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
  333. 3, 0, adc_bst_tlv),
  334. /* ASRC */
  335. SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
  336. RT5651_STO1_T_SFT, 1, 0),
  337. SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
  338. RT5651_STO2_T_SFT, 1, 0),
  339. SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
  340. RT5651_DMIC_1_M_SFT, 1, 0),
  341. SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
  342. SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
  343. };
  344. /**
  345. * set_dmic_clk - Set parameter of dmic.
  346. *
  347. * @w: DAPM widget.
  348. * @kcontrol: The kcontrol of this widget.
  349. * @event: Event id.
  350. *
  351. */
  352. static int set_dmic_clk(struct snd_soc_dapm_widget *w,
  353. struct snd_kcontrol *kcontrol, int event)
  354. {
  355. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  356. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  357. int idx, rate;
  358. rate = rt5651->sysclk / rl6231_get_pre_div(rt5651->regmap,
  359. RT5651_ADDA_CLK1, RT5651_I2S_PD1_SFT);
  360. idx = rl6231_calc_dmic_clk(rate);
  361. if (idx < 0)
  362. dev_err(codec->dev, "Failed to set DMIC clock\n");
  363. else
  364. snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
  365. idx << RT5651_DMIC_CLK_SFT);
  366. return idx;
  367. }
  368. static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
  369. struct snd_soc_dapm_widget *sink)
  370. {
  371. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
  372. unsigned int val;
  373. val = snd_soc_read(codec, RT5651_GLB_CLK);
  374. val &= RT5651_SCLK_SRC_MASK;
  375. if (val == RT5651_SCLK_SRC_PLL1)
  376. return 1;
  377. else
  378. return 0;
  379. }
  380. /* Digital Mixer */
  381. static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
  382. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
  383. RT5651_M_STO1_ADC_L1_SFT, 1, 1),
  384. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
  385. RT5651_M_STO1_ADC_L2_SFT, 1, 1),
  386. };
  387. static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
  388. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
  389. RT5651_M_STO1_ADC_R1_SFT, 1, 1),
  390. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
  391. RT5651_M_STO1_ADC_R2_SFT, 1, 1),
  392. };
  393. static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
  394. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
  395. RT5651_M_STO2_ADC_L1_SFT, 1, 1),
  396. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
  397. RT5651_M_STO2_ADC_L2_SFT, 1, 1),
  398. };
  399. static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
  400. SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
  401. RT5651_M_STO2_ADC_R1_SFT, 1, 1),
  402. SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
  403. RT5651_M_STO2_ADC_R2_SFT, 1, 1),
  404. };
  405. static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
  406. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
  407. RT5651_M_ADCMIX_L_SFT, 1, 1),
  408. SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
  409. RT5651_M_IF1_DAC_L_SFT, 1, 1),
  410. };
  411. static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
  412. SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
  413. RT5651_M_ADCMIX_R_SFT, 1, 1),
  414. SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
  415. RT5651_M_IF1_DAC_R_SFT, 1, 1),
  416. };
  417. static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
  418. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
  419. RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
  420. SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
  421. RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
  422. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
  423. RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
  424. };
  425. static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
  426. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
  427. RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
  428. SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
  429. RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
  430. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
  431. RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
  432. };
  433. static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
  434. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
  435. RT5651_M_STO_DD_L1_SFT, 1, 1),
  436. SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
  437. RT5651_M_STO_DD_L2_SFT, 1, 1),
  438. SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
  439. RT5651_M_STO_DD_R2_L_SFT, 1, 1),
  440. };
  441. static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
  442. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
  443. RT5651_M_STO_DD_R1_SFT, 1, 1),
  444. SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
  445. RT5651_M_STO_DD_R2_SFT, 1, 1),
  446. SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
  447. RT5651_M_STO_DD_L2_R_SFT, 1, 1),
  448. };
  449. /* Analog Input Mixer */
  450. static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
  451. SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
  452. RT5651_M_IN1_L_RM_L_SFT, 1, 1),
  453. SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
  454. RT5651_M_BST3_RM_L_SFT, 1, 1),
  455. SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
  456. RT5651_M_BST2_RM_L_SFT, 1, 1),
  457. SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
  458. RT5651_M_BST1_RM_L_SFT, 1, 1),
  459. };
  460. static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
  461. SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
  462. RT5651_M_IN1_R_RM_R_SFT, 1, 1),
  463. SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
  464. RT5651_M_BST3_RM_R_SFT, 1, 1),
  465. SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
  466. RT5651_M_BST2_RM_R_SFT, 1, 1),
  467. SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
  468. RT5651_M_BST1_RM_R_SFT, 1, 1),
  469. };
  470. /* Analog Output Mixer */
  471. static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
  472. SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
  473. RT5651_M_BST1_OM_L_SFT, 1, 1),
  474. SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
  475. RT5651_M_BST2_OM_L_SFT, 1, 1),
  476. SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
  477. RT5651_M_IN1_L_OM_L_SFT, 1, 1),
  478. SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
  479. RT5651_M_RM_L_OM_L_SFT, 1, 1),
  480. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
  481. RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
  482. };
  483. static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
  484. SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
  485. RT5651_M_BST2_OM_R_SFT, 1, 1),
  486. SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
  487. RT5651_M_BST1_OM_R_SFT, 1, 1),
  488. SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
  489. RT5651_M_IN1_R_OM_R_SFT, 1, 1),
  490. SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
  491. RT5651_M_RM_R_OM_R_SFT, 1, 1),
  492. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
  493. RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
  494. };
  495. static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
  496. SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
  497. RT5651_M_DAC1_HM_SFT, 1, 1),
  498. SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
  499. RT5651_M_HPVOL_HM_SFT, 1, 1),
  500. };
  501. static const struct snd_kcontrol_new rt5651_lout_mix[] = {
  502. SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
  503. RT5651_M_DAC_L1_LM_SFT, 1, 1),
  504. SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
  505. RT5651_M_DAC_R1_LM_SFT, 1, 1),
  506. SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
  507. RT5651_M_OV_L_LM_SFT, 1, 1),
  508. SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
  509. RT5651_M_OV_R_LM_SFT, 1, 1),
  510. };
  511. static const struct snd_kcontrol_new outvol_l_control =
  512. SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
  513. RT5651_VOL_L_SFT, 1, 1);
  514. static const struct snd_kcontrol_new outvol_r_control =
  515. SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
  516. RT5651_VOL_R_SFT, 1, 1);
  517. static const struct snd_kcontrol_new lout_l_mute_control =
  518. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
  519. RT5651_L_MUTE_SFT, 1, 1);
  520. static const struct snd_kcontrol_new lout_r_mute_control =
  521. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
  522. RT5651_R_MUTE_SFT, 1, 1);
  523. static const struct snd_kcontrol_new hpovol_l_control =
  524. SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
  525. RT5651_VOL_L_SFT, 1, 1);
  526. static const struct snd_kcontrol_new hpovol_r_control =
  527. SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
  528. RT5651_VOL_R_SFT, 1, 1);
  529. static const struct snd_kcontrol_new hpo_l_mute_control =
  530. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
  531. RT5651_L_MUTE_SFT, 1, 1);
  532. static const struct snd_kcontrol_new hpo_r_mute_control =
  533. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
  534. RT5651_R_MUTE_SFT, 1, 1);
  535. /* INL/R source */
  536. static const char * const rt5651_inl_src[] = {"IN2P", "HPOVOLLP"};
  537. static SOC_ENUM_SINGLE_DECL(
  538. rt5651_inl_enum, RT5651_INL1_INR1_VOL,
  539. RT5651_INL_SEL_SFT, rt5651_inl_src);
  540. static const struct snd_kcontrol_new rt5651_inl1_mux =
  541. SOC_DAPM_ENUM("INL1 source", rt5651_inl_enum);
  542. static const char * const rt5651_inr1_src[] = {"IN2N", "HPOVOLRP"};
  543. static SOC_ENUM_SINGLE_DECL(
  544. rt5651_inr1_enum, RT5651_INL1_INR1_VOL,
  545. RT5651_INR_SEL_SFT, rt5651_inr1_src);
  546. static const struct snd_kcontrol_new rt5651_inr1_mux =
  547. SOC_DAPM_ENUM("INR1 source", rt5651_inr1_enum);
  548. static const char * const rt5651_inl2_src[] = {"IN3P", "OUTVOLLP"};
  549. static SOC_ENUM_SINGLE_DECL(
  550. rt5651_inl2_enum, RT5651_INL2_INR2_VOL,
  551. RT5651_INL_SEL_SFT, rt5651_inl2_src);
  552. static const struct snd_kcontrol_new rt5651_inl2_mux =
  553. SOC_DAPM_ENUM("INL2 source", rt5651_inl2_enum);
  554. static const char * const rt5651_inr2_src[] = {"IN3N", "OUTVOLRP"};
  555. static SOC_ENUM_SINGLE_DECL(
  556. rt5651_inr2_enum, RT5651_INL2_INR2_VOL,
  557. RT5651_INR_SEL_SFT, rt5651_inr2_src);
  558. static const struct snd_kcontrol_new rt5651_inr2_mux =
  559. SOC_DAPM_ENUM("INR2 source", rt5651_inr2_enum);
  560. /* Stereo ADC source */
  561. static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
  562. static SOC_ENUM_SINGLE_DECL(
  563. rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
  564. RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
  565. static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
  566. SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
  567. static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
  568. SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
  569. static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
  570. static SOC_ENUM_SINGLE_DECL(
  571. rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
  572. RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
  573. static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
  574. SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
  575. static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
  576. SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
  577. /* Mono ADC source */
  578. static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
  579. static SOC_ENUM_SINGLE_DECL(
  580. rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
  581. RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
  582. static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
  583. SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
  584. static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
  585. static SOC_ENUM_SINGLE_DECL(
  586. rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
  587. RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
  588. static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
  589. SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
  590. static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
  591. static SOC_ENUM_SINGLE_DECL(
  592. rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
  593. RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
  594. static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
  595. SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
  596. static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
  597. static SOC_ENUM_SINGLE_DECL(
  598. rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
  599. RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
  600. static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
  601. SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
  602. /* DAC2 channel source */
  603. static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
  604. static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
  605. RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
  606. static const struct snd_kcontrol_new rt5651_dac_l2_mux =
  607. SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
  608. static SOC_ENUM_SINGLE_DECL(
  609. rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
  610. RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
  611. static const struct snd_kcontrol_new rt5651_dac_r2_mux =
  612. SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
  613. /* IF2_ADC channel source */
  614. static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
  615. static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
  616. RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
  617. static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
  618. SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
  619. /* PDM select */
  620. static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
  621. static SOC_ENUM_SINGLE_DECL(
  622. rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
  623. RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
  624. static SOC_ENUM_SINGLE_DECL(
  625. rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
  626. RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
  627. static const struct snd_kcontrol_new rt5651_pdm_l_mux =
  628. SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
  629. static const struct snd_kcontrol_new rt5651_pdm_r_mux =
  630. SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
  631. static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
  632. struct snd_kcontrol *kcontrol, int event)
  633. {
  634. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  635. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  636. switch (event) {
  637. case SND_SOC_DAPM_POST_PMU:
  638. /* depop parameters */
  639. regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
  640. RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
  641. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
  642. RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
  643. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
  644. RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
  645. RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
  646. RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
  647. regmap_write(rt5651->regmap, RT5651_PR_BASE +
  648. RT5651_HP_DCC_INT1, 0x9f00);
  649. /* headphone amp power on */
  650. regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
  651. RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
  652. regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
  653. RT5651_PWR_HA,
  654. RT5651_PWR_HA);
  655. usleep_range(10000, 15000);
  656. regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
  657. RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
  658. RT5651_PWR_FV1 | RT5651_PWR_FV2);
  659. break;
  660. default:
  661. return 0;
  662. }
  663. return 0;
  664. }
  665. static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
  666. struct snd_kcontrol *kcontrol, int event)
  667. {
  668. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  669. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  670. switch (event) {
  671. case SND_SOC_DAPM_POST_PMU:
  672. /* headphone unmute sequence */
  673. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
  674. RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
  675. RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
  676. regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
  677. RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
  678. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
  679. RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
  680. RT5651_CP_FQ3_MASK,
  681. (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
  682. (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
  683. (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
  684. regmap_write(rt5651->regmap, RT5651_PR_BASE +
  685. RT5651_MAMP_INT_REG2, 0x1c00);
  686. regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
  687. RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
  688. RT5651_HP_CP_PD | RT5651_HP_SG_EN);
  689. regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
  690. RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
  691. rt5651->hp_mute = 0;
  692. break;
  693. case SND_SOC_DAPM_PRE_PMD:
  694. rt5651->hp_mute = 1;
  695. usleep_range(70000, 75000);
  696. break;
  697. default:
  698. return 0;
  699. }
  700. return 0;
  701. }
  702. static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
  703. struct snd_kcontrol *kcontrol, int event)
  704. {
  705. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  706. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  707. switch (event) {
  708. case SND_SOC_DAPM_POST_PMU:
  709. if (!rt5651->hp_mute)
  710. usleep_range(80000, 85000);
  711. break;
  712. default:
  713. return 0;
  714. }
  715. return 0;
  716. }
  717. static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
  718. struct snd_kcontrol *kcontrol, int event)
  719. {
  720. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  721. switch (event) {
  722. case SND_SOC_DAPM_POST_PMU:
  723. snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
  724. RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
  725. break;
  726. case SND_SOC_DAPM_PRE_PMD:
  727. snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
  728. RT5651_PWR_BST1_OP2, 0);
  729. break;
  730. default:
  731. return 0;
  732. }
  733. return 0;
  734. }
  735. static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
  736. struct snd_kcontrol *kcontrol, int event)
  737. {
  738. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  739. switch (event) {
  740. case SND_SOC_DAPM_POST_PMU:
  741. snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
  742. RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
  743. break;
  744. case SND_SOC_DAPM_PRE_PMD:
  745. snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
  746. RT5651_PWR_BST2_OP2, 0);
  747. break;
  748. default:
  749. return 0;
  750. }
  751. return 0;
  752. }
  753. static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
  754. struct snd_kcontrol *kcontrol, int event)
  755. {
  756. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  757. switch (event) {
  758. case SND_SOC_DAPM_POST_PMU:
  759. snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
  760. RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
  761. break;
  762. case SND_SOC_DAPM_PRE_PMD:
  763. snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
  764. RT5651_PWR_BST3_OP2, 0);
  765. break;
  766. default:
  767. return 0;
  768. }
  769. return 0;
  770. }
  771. static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
  772. /* ASRC */
  773. SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
  774. 15, 0, NULL, 0),
  775. SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
  776. 14, 0, NULL, 0),
  777. SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
  778. 13, 0, NULL, 0),
  779. SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
  780. 12, 0, NULL, 0),
  781. SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
  782. 11, 0, NULL, 0),
  783. SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
  784. RT5651_PWR_PLL_BIT, 0, NULL, 0),
  785. /* Input Side */
  786. /* micbias */
  787. SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
  788. RT5651_PWR_LDO_BIT, 0, NULL, 0),
  789. SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2,
  790. RT5651_PWR_MB1_BIT, 0),
  791. /* Input Lines */
  792. SND_SOC_DAPM_INPUT("MIC1"),
  793. SND_SOC_DAPM_INPUT("MIC2"),
  794. SND_SOC_DAPM_INPUT("MIC3"),
  795. SND_SOC_DAPM_INPUT("IN1P"),
  796. SND_SOC_DAPM_INPUT("IN2P"),
  797. SND_SOC_DAPM_INPUT("IN2N"),
  798. SND_SOC_DAPM_INPUT("IN3P"),
  799. SND_SOC_DAPM_INPUT("DMIC L1"),
  800. SND_SOC_DAPM_INPUT("DMIC R1"),
  801. SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
  802. 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
  803. /* Boost */
  804. SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
  805. RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
  806. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  807. SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
  808. RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
  809. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  810. SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
  811. RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
  812. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  813. /* Input Volume */
  814. SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
  815. RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
  816. SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
  817. RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
  818. SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
  819. RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
  820. SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
  821. RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
  822. /* IN Mux */
  823. SND_SOC_DAPM_MUX("INL1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl1_mux),
  824. SND_SOC_DAPM_MUX("INR1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr1_mux),
  825. SND_SOC_DAPM_MUX("INL2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl2_mux),
  826. SND_SOC_DAPM_MUX("INR2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr2_mux),
  827. /* REC Mixer */
  828. SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
  829. rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
  830. SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
  831. rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
  832. /* ADCs */
  833. SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
  834. SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
  835. SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
  836. RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
  837. SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
  838. RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
  839. /* ADC Mux */
  840. SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  841. &rt5651_sto1_adc_l2_mux),
  842. SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  843. &rt5651_sto1_adc_r2_mux),
  844. SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  845. &rt5651_sto1_adc_l1_mux),
  846. SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  847. &rt5651_sto1_adc_r1_mux),
  848. SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
  849. &rt5651_sto2_adc_l2_mux),
  850. SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
  851. &rt5651_sto2_adc_l1_mux),
  852. SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
  853. &rt5651_sto2_adc_r1_mux),
  854. SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
  855. &rt5651_sto2_adc_r2_mux),
  856. /* ADC Mixer */
  857. SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
  858. RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
  859. SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
  860. RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
  861. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
  862. rt5651_sto1_adc_l_mix,
  863. ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
  864. SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
  865. rt5651_sto1_adc_r_mix,
  866. ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
  867. SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
  868. rt5651_sto2_adc_l_mix,
  869. ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
  870. SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
  871. rt5651_sto2_adc_r_mix,
  872. ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
  873. /* Digital Interface */
  874. SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
  875. RT5651_PWR_I2S1_BIT, 0, NULL, 0),
  876. SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  877. SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  878. SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  879. SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
  880. SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
  881. SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
  882. SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
  883. SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
  884. RT5651_PWR_I2S2_BIT, 0, NULL, 0),
  885. SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
  886. SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
  887. SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
  888. SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
  889. &rt5651_if2_adc_src_mux),
  890. /* Digital Interface Select */
  891. SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
  892. RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
  893. SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
  894. RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
  895. /* Audio Interface */
  896. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  897. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  898. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  899. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  900. /* Audio DSP */
  901. SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
  902. /* Output Side */
  903. /* DAC mixer before sound effect */
  904. SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
  905. rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
  906. SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
  907. rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
  908. /* DAC2 channel Mux */
  909. SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
  910. SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
  911. SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
  912. SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
  913. SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
  914. RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
  915. SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
  916. RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
  917. /* DAC Mixer */
  918. SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
  919. rt5651_sto_dac_l_mix,
  920. ARRAY_SIZE(rt5651_sto_dac_l_mix)),
  921. SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
  922. rt5651_sto_dac_r_mix,
  923. ARRAY_SIZE(rt5651_sto_dac_r_mix)),
  924. SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
  925. rt5651_dd_dac_l_mix,
  926. ARRAY_SIZE(rt5651_dd_dac_l_mix)),
  927. SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
  928. rt5651_dd_dac_r_mix,
  929. ARRAY_SIZE(rt5651_dd_dac_r_mix)),
  930. /* DACs */
  931. SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
  932. SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
  933. SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
  934. RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
  935. SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
  936. RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
  937. /* OUT Mixer */
  938. SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
  939. 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
  940. SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
  941. 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
  942. /* Ouput Volume */
  943. SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
  944. RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
  945. SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
  946. RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
  947. SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
  948. RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
  949. SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
  950. RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
  951. SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
  952. RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
  953. SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
  954. RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
  955. SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
  956. RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
  957. SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
  958. RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
  959. /* HPO/LOUT/Mono Mixer */
  960. SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
  961. rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
  962. SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
  963. rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
  964. SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
  965. RT5651_PWR_HP_L_BIT, 0, NULL, 0),
  966. SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
  967. RT5651_PWR_HP_R_BIT, 0, NULL, 0),
  968. SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
  969. rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
  970. SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
  971. RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
  972. SND_SOC_DAPM_POST_PMU),
  973. SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
  974. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  975. SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
  976. &hpo_l_mute_control),
  977. SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
  978. &hpo_r_mute_control),
  979. SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
  980. &lout_l_mute_control),
  981. SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
  982. &lout_r_mute_control),
  983. SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
  984. /* Output Lines */
  985. SND_SOC_DAPM_OUTPUT("HPOL"),
  986. SND_SOC_DAPM_OUTPUT("HPOR"),
  987. SND_SOC_DAPM_OUTPUT("LOUTL"),
  988. SND_SOC_DAPM_OUTPUT("LOUTR"),
  989. SND_SOC_DAPM_OUTPUT("PDML"),
  990. SND_SOC_DAPM_OUTPUT("PDMR"),
  991. };
  992. static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
  993. {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
  994. {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
  995. {"I2S1", NULL, "I2S1 ASRC"},
  996. {"I2S2", NULL, "I2S2 ASRC"},
  997. {"IN1P", NULL, "LDO"},
  998. {"IN2P", NULL, "LDO"},
  999. {"IN3P", NULL, "LDO"},
  1000. {"IN1P", NULL, "MIC1"},
  1001. {"IN2P", NULL, "MIC2"},
  1002. {"IN2N", NULL, "MIC2"},
  1003. {"IN3P", NULL, "MIC3"},
  1004. {"BST1", NULL, "IN1P"},
  1005. {"BST2", NULL, "IN2P"},
  1006. {"BST2", NULL, "IN2N"},
  1007. {"BST3", NULL, "IN3P"},
  1008. {"INL1 VOL", NULL, "IN2P"},
  1009. {"INR1 VOL", NULL, "IN2N"},
  1010. {"RECMIXL", "INL1 Switch", "INL1 VOL"},
  1011. {"RECMIXL", "BST3 Switch", "BST3"},
  1012. {"RECMIXL", "BST2 Switch", "BST2"},
  1013. {"RECMIXL", "BST1 Switch", "BST1"},
  1014. {"RECMIXR", "INR1 Switch", "INR1 VOL"},
  1015. {"RECMIXR", "BST3 Switch", "BST3"},
  1016. {"RECMIXR", "BST2 Switch", "BST2"},
  1017. {"RECMIXR", "BST1 Switch", "BST1"},
  1018. {"ADC L", NULL, "RECMIXL"},
  1019. {"ADC L", NULL, "ADC L Power"},
  1020. {"ADC R", NULL, "RECMIXR"},
  1021. {"ADC R", NULL, "ADC R Power"},
  1022. {"DMIC L1", NULL, "DMIC CLK"},
  1023. {"DMIC R1", NULL, "DMIC CLK"},
  1024. {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
  1025. {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
  1026. {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
  1027. {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
  1028. {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
  1029. {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
  1030. {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
  1031. {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
  1032. {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
  1033. {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
  1034. {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
  1035. {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
  1036. {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
  1037. {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
  1038. {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
  1039. {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
  1040. {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
  1041. {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
  1042. {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
  1043. {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
  1044. {"Stereo1 Filter", NULL, "ADC ASRC"},
  1045. {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
  1046. {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
  1047. {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
  1048. {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
  1049. {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
  1050. {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
  1051. {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
  1052. {"Stereo2 Filter", NULL, "ADC ASRC"},
  1053. {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
  1054. {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
  1055. {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
  1056. {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
  1057. {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
  1058. {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
  1059. {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
  1060. {"IF1 ADC1", NULL, "I2S1"},
  1061. {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
  1062. {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
  1063. {"IF2 ADC", NULL, "I2S2"},
  1064. {"AIF1TX", NULL, "IF1 ADC1"},
  1065. {"AIF1TX", NULL, "IF1 ADC2"},
  1066. {"AIF2TX", NULL, "IF2 ADC"},
  1067. {"IF1 DAC", NULL, "AIF1RX"},
  1068. {"IF1 DAC", NULL, "I2S1"},
  1069. {"IF2 DAC", NULL, "AIF2RX"},
  1070. {"IF2 DAC", NULL, "I2S2"},
  1071. {"IF1 DAC1 L", NULL, "IF1 DAC"},
  1072. {"IF1 DAC1 R", NULL, "IF1 DAC"},
  1073. {"IF1 DAC2 L", NULL, "IF1 DAC"},
  1074. {"IF1 DAC2 R", NULL, "IF1 DAC"},
  1075. {"IF2 DAC L", NULL, "IF2 DAC"},
  1076. {"IF2 DAC R", NULL, "IF2 DAC"},
  1077. {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
  1078. {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
  1079. {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
  1080. {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
  1081. {"Audio DSP", NULL, "DAC MIXL"},
  1082. {"Audio DSP", NULL, "DAC MIXR"},
  1083. {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
  1084. {"DAC L2 Mux", "IF2", "IF2 DAC L"},
  1085. {"DAC L2 Volume", NULL, "DAC L2 Mux"},
  1086. {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
  1087. {"DAC R2 Mux", "IF2", "IF2 DAC R"},
  1088. {"DAC R2 Volume", NULL, "DAC R2 Mux"},
  1089. {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
  1090. {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
  1091. {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
  1092. {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
  1093. {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
  1094. {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
  1095. {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
  1096. {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
  1097. {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
  1098. {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
  1099. {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
  1100. {"PDM L Mux", "DD MIX", "DAC MIXL"},
  1101. {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
  1102. {"PDM R Mux", "DD MIX", "DAC MIXR"},
  1103. {"DAC L1", NULL, "Stereo DAC MIXL"},
  1104. {"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
  1105. {"DAC L1", NULL, "DAC L1 Power"},
  1106. {"DAC R1", NULL, "Stereo DAC MIXR"},
  1107. {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
  1108. {"DAC R1", NULL, "DAC R1 Power"},
  1109. {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
  1110. {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
  1111. {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
  1112. {"DD MIXL", NULL, "Stero2 DAC Power"},
  1113. {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
  1114. {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
  1115. {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
  1116. {"DD MIXR", NULL, "Stero2 DAC Power"},
  1117. {"OUT MIXL", "BST1 Switch", "BST1"},
  1118. {"OUT MIXL", "BST2 Switch", "BST2"},
  1119. {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
  1120. {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
  1121. {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
  1122. {"OUT MIXR", "BST2 Switch", "BST2"},
  1123. {"OUT MIXR", "BST1 Switch", "BST1"},
  1124. {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
  1125. {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
  1126. {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
  1127. {"HPOVOL L", "Switch", "OUT MIXL"},
  1128. {"HPOVOL R", "Switch", "OUT MIXR"},
  1129. {"OUTVOL L", "Switch", "OUT MIXL"},
  1130. {"OUTVOL R", "Switch", "OUT MIXR"},
  1131. {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
  1132. {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
  1133. {"HPOL MIX", NULL, "HP L Amp"},
  1134. {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
  1135. {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
  1136. {"HPOR MIX", NULL, "HP R Amp"},
  1137. {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
  1138. {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
  1139. {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
  1140. {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
  1141. {"HP Amp", NULL, "HPOL MIX"},
  1142. {"HP Amp", NULL, "HPOR MIX"},
  1143. {"HP Amp", NULL, "Amp Power"},
  1144. {"HPO L Playback", "Switch", "HP Amp"},
  1145. {"HPO R Playback", "Switch", "HP Amp"},
  1146. {"HPOL", NULL, "HPO L Playback"},
  1147. {"HPOR", NULL, "HPO R Playback"},
  1148. {"LOUT L Playback", "Switch", "LOUT MIX"},
  1149. {"LOUT R Playback", "Switch", "LOUT MIX"},
  1150. {"LOUTL", NULL, "LOUT L Playback"},
  1151. {"LOUTL", NULL, "Amp Power"},
  1152. {"LOUTR", NULL, "LOUT R Playback"},
  1153. {"LOUTR", NULL, "Amp Power"},
  1154. {"PDML", NULL, "PDM L Mux"},
  1155. {"PDMR", NULL, "PDM R Mux"},
  1156. };
  1157. static int rt5651_hw_params(struct snd_pcm_substream *substream,
  1158. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1159. {
  1160. struct snd_soc_codec *codec = dai->codec;
  1161. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1162. unsigned int val_len = 0, val_clk, mask_clk;
  1163. int pre_div, bclk_ms, frame_size;
  1164. rt5651->lrck[dai->id] = params_rate(params);
  1165. pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
  1166. if (pre_div < 0) {
  1167. dev_err(codec->dev, "Unsupported clock setting\n");
  1168. return -EINVAL;
  1169. }
  1170. frame_size = snd_soc_params_to_frame_size(params);
  1171. if (frame_size < 0) {
  1172. dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
  1173. return -EINVAL;
  1174. }
  1175. bclk_ms = frame_size > 32 ? 1 : 0;
  1176. rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
  1177. dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
  1178. rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
  1179. dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
  1180. bclk_ms, pre_div, dai->id);
  1181. switch (params_width(params)) {
  1182. case 16:
  1183. break;
  1184. case 20:
  1185. val_len |= RT5651_I2S_DL_20;
  1186. break;
  1187. case 24:
  1188. val_len |= RT5651_I2S_DL_24;
  1189. break;
  1190. case 8:
  1191. val_len |= RT5651_I2S_DL_8;
  1192. break;
  1193. default:
  1194. return -EINVAL;
  1195. }
  1196. switch (dai->id) {
  1197. case RT5651_AIF1:
  1198. mask_clk = RT5651_I2S_PD1_MASK;
  1199. val_clk = pre_div << RT5651_I2S_PD1_SFT;
  1200. snd_soc_update_bits(codec, RT5651_I2S1_SDP,
  1201. RT5651_I2S_DL_MASK, val_len);
  1202. snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
  1203. break;
  1204. case RT5651_AIF2:
  1205. mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
  1206. val_clk = pre_div << RT5651_I2S_PD2_SFT;
  1207. snd_soc_update_bits(codec, RT5651_I2S2_SDP,
  1208. RT5651_I2S_DL_MASK, val_len);
  1209. snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
  1210. break;
  1211. default:
  1212. dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
  1213. return -EINVAL;
  1214. }
  1215. return 0;
  1216. }
  1217. static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1218. {
  1219. struct snd_soc_codec *codec = dai->codec;
  1220. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1221. unsigned int reg_val = 0;
  1222. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1223. case SND_SOC_DAIFMT_CBM_CFM:
  1224. rt5651->master[dai->id] = 1;
  1225. break;
  1226. case SND_SOC_DAIFMT_CBS_CFS:
  1227. reg_val |= RT5651_I2S_MS_S;
  1228. rt5651->master[dai->id] = 0;
  1229. break;
  1230. default:
  1231. return -EINVAL;
  1232. }
  1233. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1234. case SND_SOC_DAIFMT_NB_NF:
  1235. break;
  1236. case SND_SOC_DAIFMT_IB_NF:
  1237. reg_val |= RT5651_I2S_BP_INV;
  1238. break;
  1239. default:
  1240. return -EINVAL;
  1241. }
  1242. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1243. case SND_SOC_DAIFMT_I2S:
  1244. break;
  1245. case SND_SOC_DAIFMT_LEFT_J:
  1246. reg_val |= RT5651_I2S_DF_LEFT;
  1247. break;
  1248. case SND_SOC_DAIFMT_DSP_A:
  1249. reg_val |= RT5651_I2S_DF_PCM_A;
  1250. break;
  1251. case SND_SOC_DAIFMT_DSP_B:
  1252. reg_val |= RT5651_I2S_DF_PCM_B;
  1253. break;
  1254. default:
  1255. return -EINVAL;
  1256. }
  1257. switch (dai->id) {
  1258. case RT5651_AIF1:
  1259. snd_soc_update_bits(codec, RT5651_I2S1_SDP,
  1260. RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
  1261. RT5651_I2S_DF_MASK, reg_val);
  1262. break;
  1263. case RT5651_AIF2:
  1264. snd_soc_update_bits(codec, RT5651_I2S2_SDP,
  1265. RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
  1266. RT5651_I2S_DF_MASK, reg_val);
  1267. break;
  1268. default:
  1269. dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
  1270. return -EINVAL;
  1271. }
  1272. return 0;
  1273. }
  1274. static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
  1275. int clk_id, unsigned int freq, int dir)
  1276. {
  1277. struct snd_soc_codec *codec = dai->codec;
  1278. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1279. unsigned int reg_val = 0;
  1280. if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
  1281. return 0;
  1282. switch (clk_id) {
  1283. case RT5651_SCLK_S_MCLK:
  1284. reg_val |= RT5651_SCLK_SRC_MCLK;
  1285. break;
  1286. case RT5651_SCLK_S_PLL1:
  1287. reg_val |= RT5651_SCLK_SRC_PLL1;
  1288. break;
  1289. case RT5651_SCLK_S_RCCLK:
  1290. reg_val |= RT5651_SCLK_SRC_RCCLK;
  1291. break;
  1292. default:
  1293. dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
  1294. return -EINVAL;
  1295. }
  1296. snd_soc_update_bits(codec, RT5651_GLB_CLK,
  1297. RT5651_SCLK_SRC_MASK, reg_val);
  1298. rt5651->sysclk = freq;
  1299. rt5651->sysclk_src = clk_id;
  1300. dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
  1301. return 0;
  1302. }
  1303. static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
  1304. unsigned int freq_in, unsigned int freq_out)
  1305. {
  1306. struct snd_soc_codec *codec = dai->codec;
  1307. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1308. struct rl6231_pll_code pll_code;
  1309. int ret;
  1310. if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
  1311. freq_out == rt5651->pll_out)
  1312. return 0;
  1313. if (!freq_in || !freq_out) {
  1314. dev_dbg(codec->dev, "PLL disabled\n");
  1315. rt5651->pll_in = 0;
  1316. rt5651->pll_out = 0;
  1317. snd_soc_update_bits(codec, RT5651_GLB_CLK,
  1318. RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
  1319. return 0;
  1320. }
  1321. switch (source) {
  1322. case RT5651_PLL1_S_MCLK:
  1323. snd_soc_update_bits(codec, RT5651_GLB_CLK,
  1324. RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
  1325. break;
  1326. case RT5651_PLL1_S_BCLK1:
  1327. snd_soc_update_bits(codec, RT5651_GLB_CLK,
  1328. RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
  1329. break;
  1330. case RT5651_PLL1_S_BCLK2:
  1331. snd_soc_update_bits(codec, RT5651_GLB_CLK,
  1332. RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
  1333. break;
  1334. default:
  1335. dev_err(codec->dev, "Unknown PLL source %d\n", source);
  1336. return -EINVAL;
  1337. }
  1338. ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
  1339. if (ret < 0) {
  1340. dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
  1341. return ret;
  1342. }
  1343. dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
  1344. pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
  1345. pll_code.n_code, pll_code.k_code);
  1346. snd_soc_write(codec, RT5651_PLL_CTRL1,
  1347. pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
  1348. snd_soc_write(codec, RT5651_PLL_CTRL2,
  1349. (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
  1350. pll_code.m_bp << RT5651_PLL_M_BP_SFT);
  1351. rt5651->pll_in = freq_in;
  1352. rt5651->pll_out = freq_out;
  1353. rt5651->pll_src = source;
  1354. return 0;
  1355. }
  1356. static int rt5651_set_bias_level(struct snd_soc_codec *codec,
  1357. enum snd_soc_bias_level level)
  1358. {
  1359. switch (level) {
  1360. case SND_SOC_BIAS_PREPARE:
  1361. if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
  1362. snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
  1363. RT5651_PWR_VREF1 | RT5651_PWR_MB |
  1364. RT5651_PWR_BG | RT5651_PWR_VREF2,
  1365. RT5651_PWR_VREF1 | RT5651_PWR_MB |
  1366. RT5651_PWR_BG | RT5651_PWR_VREF2);
  1367. usleep_range(10000, 15000);
  1368. snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
  1369. RT5651_PWR_FV1 | RT5651_PWR_FV2,
  1370. RT5651_PWR_FV1 | RT5651_PWR_FV2);
  1371. snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
  1372. RT5651_PWR_LDO_DVO_MASK,
  1373. RT5651_PWR_LDO_DVO_1_2V);
  1374. snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1);
  1375. if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200)
  1376. snd_soc_update_bits(codec, RT5651_D_MISC,
  1377. 0xc00, 0xc00);
  1378. }
  1379. break;
  1380. case SND_SOC_BIAS_STANDBY:
  1381. snd_soc_write(codec, RT5651_D_MISC, 0x0010);
  1382. snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000);
  1383. snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000);
  1384. snd_soc_write(codec, RT5651_PWR_VOL, 0x0000);
  1385. snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000);
  1386. snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000);
  1387. snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000);
  1388. break;
  1389. default:
  1390. break;
  1391. }
  1392. return 0;
  1393. }
  1394. static int rt5651_probe(struct snd_soc_codec *codec)
  1395. {
  1396. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1397. rt5651->codec = codec;
  1398. snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
  1399. RT5651_PWR_VREF1 | RT5651_PWR_MB |
  1400. RT5651_PWR_BG | RT5651_PWR_VREF2,
  1401. RT5651_PWR_VREF1 | RT5651_PWR_MB |
  1402. RT5651_PWR_BG | RT5651_PWR_VREF2);
  1403. usleep_range(10000, 15000);
  1404. snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
  1405. RT5651_PWR_FV1 | RT5651_PWR_FV2,
  1406. RT5651_PWR_FV1 | RT5651_PWR_FV2);
  1407. snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
  1408. return 0;
  1409. }
  1410. #ifdef CONFIG_PM
  1411. static int rt5651_suspend(struct snd_soc_codec *codec)
  1412. {
  1413. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1414. regcache_cache_only(rt5651->regmap, true);
  1415. regcache_mark_dirty(rt5651->regmap);
  1416. return 0;
  1417. }
  1418. static int rt5651_resume(struct snd_soc_codec *codec)
  1419. {
  1420. struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
  1421. regcache_cache_only(rt5651->regmap, false);
  1422. snd_soc_cache_sync(codec);
  1423. return 0;
  1424. }
  1425. #else
  1426. #define rt5651_suspend NULL
  1427. #define rt5651_resume NULL
  1428. #endif
  1429. #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
  1430. #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1431. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  1432. static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
  1433. .hw_params = rt5651_hw_params,
  1434. .set_fmt = rt5651_set_dai_fmt,
  1435. .set_sysclk = rt5651_set_dai_sysclk,
  1436. .set_pll = rt5651_set_dai_pll,
  1437. };
  1438. static struct snd_soc_dai_driver rt5651_dai[] = {
  1439. {
  1440. .name = "rt5651-aif1",
  1441. .id = RT5651_AIF1,
  1442. .playback = {
  1443. .stream_name = "AIF1 Playback",
  1444. .channels_min = 1,
  1445. .channels_max = 2,
  1446. .rates = RT5651_STEREO_RATES,
  1447. .formats = RT5651_FORMATS,
  1448. },
  1449. .capture = {
  1450. .stream_name = "AIF1 Capture",
  1451. .channels_min = 1,
  1452. .channels_max = 2,
  1453. .rates = RT5651_STEREO_RATES,
  1454. .formats = RT5651_FORMATS,
  1455. },
  1456. .ops = &rt5651_aif_dai_ops,
  1457. },
  1458. {
  1459. .name = "rt5651-aif2",
  1460. .id = RT5651_AIF2,
  1461. .playback = {
  1462. .stream_name = "AIF2 Playback",
  1463. .channels_min = 1,
  1464. .channels_max = 2,
  1465. .rates = RT5651_STEREO_RATES,
  1466. .formats = RT5651_FORMATS,
  1467. },
  1468. .capture = {
  1469. .stream_name = "AIF2 Capture",
  1470. .channels_min = 1,
  1471. .channels_max = 2,
  1472. .rates = RT5651_STEREO_RATES,
  1473. .formats = RT5651_FORMATS,
  1474. },
  1475. .ops = &rt5651_aif_dai_ops,
  1476. },
  1477. };
  1478. static struct snd_soc_codec_driver soc_codec_dev_rt5651 = {
  1479. .probe = rt5651_probe,
  1480. .suspend = rt5651_suspend,
  1481. .resume = rt5651_resume,
  1482. .set_bias_level = rt5651_set_bias_level,
  1483. .idle_bias_off = true,
  1484. .component_driver = {
  1485. .controls = rt5651_snd_controls,
  1486. .num_controls = ARRAY_SIZE(rt5651_snd_controls),
  1487. .dapm_widgets = rt5651_dapm_widgets,
  1488. .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
  1489. .dapm_routes = rt5651_dapm_routes,
  1490. .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
  1491. },
  1492. };
  1493. static const struct regmap_config rt5651_regmap = {
  1494. .reg_bits = 8,
  1495. .val_bits = 16,
  1496. .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
  1497. RT5651_PR_SPACING),
  1498. .volatile_reg = rt5651_volatile_register,
  1499. .readable_reg = rt5651_readable_register,
  1500. .cache_type = REGCACHE_RBTREE,
  1501. .reg_defaults = rt5651_reg,
  1502. .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
  1503. .ranges = rt5651_ranges,
  1504. .num_ranges = ARRAY_SIZE(rt5651_ranges),
  1505. .use_single_rw = true,
  1506. };
  1507. #if defined(CONFIG_OF)
  1508. static const struct of_device_id rt5651_of_match[] = {
  1509. { .compatible = "realtek,rt5651", },
  1510. {},
  1511. };
  1512. MODULE_DEVICE_TABLE(of, rt5651_of_match);
  1513. #endif
  1514. #ifdef CONFIG_ACPI
  1515. static const struct acpi_device_id rt5651_acpi_match[] = {
  1516. { "10EC5651", 0 },
  1517. { },
  1518. };
  1519. MODULE_DEVICE_TABLE(acpi, rt5651_acpi_match);
  1520. #endif
  1521. static const struct i2c_device_id rt5651_i2c_id[] = {
  1522. { "rt5651", 0 },
  1523. { }
  1524. };
  1525. MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
  1526. static int rt5651_parse_dt(struct rt5651_priv *rt5651, struct device_node *np)
  1527. {
  1528. rt5651->pdata.in2_diff = of_property_read_bool(np,
  1529. "realtek,in2-differential");
  1530. rt5651->pdata.dmic_en = of_property_read_bool(np,
  1531. "realtek,dmic-en");
  1532. return 0;
  1533. }
  1534. static int rt5651_i2c_probe(struct i2c_client *i2c,
  1535. const struct i2c_device_id *id)
  1536. {
  1537. struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev);
  1538. struct rt5651_priv *rt5651;
  1539. int ret;
  1540. rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
  1541. GFP_KERNEL);
  1542. if (NULL == rt5651)
  1543. return -ENOMEM;
  1544. i2c_set_clientdata(i2c, rt5651);
  1545. if (pdata)
  1546. rt5651->pdata = *pdata;
  1547. else if (i2c->dev.of_node)
  1548. rt5651_parse_dt(rt5651, i2c->dev.of_node);
  1549. rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
  1550. if (IS_ERR(rt5651->regmap)) {
  1551. ret = PTR_ERR(rt5651->regmap);
  1552. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1553. ret);
  1554. return ret;
  1555. }
  1556. regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
  1557. if (ret != RT5651_DEVICE_ID_VALUE) {
  1558. dev_err(&i2c->dev,
  1559. "Device with ID register %#x is not rt5651\n", ret);
  1560. return -ENODEV;
  1561. }
  1562. regmap_write(rt5651->regmap, RT5651_RESET, 0);
  1563. ret = regmap_register_patch(rt5651->regmap, init_list,
  1564. ARRAY_SIZE(init_list));
  1565. if (ret != 0)
  1566. dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
  1567. if (rt5651->pdata.in2_diff)
  1568. regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2,
  1569. RT5651_IN_DF2, RT5651_IN_DF2);
  1570. if (rt5651->pdata.dmic_en)
  1571. regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1,
  1572. RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
  1573. rt5651->hp_mute = 1;
  1574. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651,
  1575. rt5651_dai, ARRAY_SIZE(rt5651_dai));
  1576. return ret;
  1577. }
  1578. static int rt5651_i2c_remove(struct i2c_client *i2c)
  1579. {
  1580. snd_soc_unregister_codec(&i2c->dev);
  1581. return 0;
  1582. }
  1583. static struct i2c_driver rt5651_i2c_driver = {
  1584. .driver = {
  1585. .name = "rt5651",
  1586. .acpi_match_table = ACPI_PTR(rt5651_acpi_match),
  1587. .of_match_table = of_match_ptr(rt5651_of_match),
  1588. },
  1589. .probe = rt5651_i2c_probe,
  1590. .remove = rt5651_i2c_remove,
  1591. .id_table = rt5651_i2c_id,
  1592. };
  1593. module_i2c_driver(rt5651_i2c_driver);
  1594. MODULE_DESCRIPTION("ASoC RT5651 driver");
  1595. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  1596. MODULE_LICENSE("GPL v2");