s3c2410.h 1.4 KB

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  1. /*
  2. * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
  9. */
  10. #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
  11. #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
  12. /*
  13. * Let each exported clock get a unique index, which is used on DT-enabled
  14. * platforms to lookup the clock from a clock specifier. These indices are
  15. * therefore considered an ABI and so must not be changed. This implies
  16. * that new clocks should be added either in free spaces between clock groups
  17. * or at the end.
  18. */
  19. /* Core clocks. */
  20. /* id 1 is reserved */
  21. #define MPLL 2
  22. #define UPLL 3
  23. #define FCLK 4
  24. #define HCLK 5
  25. #define PCLK 6
  26. #define UCLK 7
  27. #define ARMCLK 8
  28. /* pclk-gates */
  29. #define PCLK_UART0 16
  30. #define PCLK_UART1 17
  31. #define PCLK_UART2 18
  32. #define PCLK_I2C 19
  33. #define PCLK_SDI 20
  34. #define PCLK_SPI 21
  35. #define PCLK_ADC 22
  36. #define PCLK_AC97 23
  37. #define PCLK_I2S 24
  38. #define PCLK_PWM 25
  39. #define PCLK_RTC 26
  40. #define PCLK_GPIO 27
  41. /* hclk-gates */
  42. #define HCLK_LCD 32
  43. #define HCLK_USBH 33
  44. #define HCLK_USBD 34
  45. #define HCLK_NAND 35
  46. #define HCLK_CAM 36
  47. #define CAMIF 40
  48. /* Total number of clocks. */
  49. #define NR_CLKS (CAMIF + 1)
  50. #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */