core_intr.c 16 KB

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  1. /*
  2. * core_intr.c - DesignWare HS OTG Controller common interrupt handling
  3. *
  4. * Copyright (C) 2004-2013 Synopsys, Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions, and the following disclaimer,
  11. * without modification.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. The names of the above-listed copyright holders may not be used
  16. * to endorse or promote products derived from this software without
  17. * specific prior written permission.
  18. *
  19. * ALTERNATIVELY, this software may be distributed under the terms of the
  20. * GNU General Public License ("GPL") as published by the Free Software
  21. * Foundation; either version 2 of the License, or (at your option) any
  22. * later version.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. /*
  37. * This file contains the common interrupt handlers
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/moduleparam.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/io.h>
  46. #include <linux/slab.h>
  47. #include <linux/usb.h>
  48. #include <linux/usb/hcd.h>
  49. #include <linux/usb/ch11.h>
  50. #include "core.h"
  51. #include "hcd.h"
  52. static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  53. {
  54. switch (hsotg->op_state) {
  55. case OTG_STATE_A_HOST:
  56. return "a_host";
  57. case OTG_STATE_A_SUSPEND:
  58. return "a_suspend";
  59. case OTG_STATE_A_PERIPHERAL:
  60. return "a_peripheral";
  61. case OTG_STATE_B_PERIPHERAL:
  62. return "b_peripheral";
  63. case OTG_STATE_B_HOST:
  64. return "b_host";
  65. default:
  66. return "unknown";
  67. }
  68. }
  69. /**
  70. * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  71. * When the PRTINT interrupt fires, there are certain status bits in the Host
  72. * Port that needs to get cleared.
  73. *
  74. * @hsotg: Programming view of DWC_otg controller
  75. */
  76. static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  77. {
  78. u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
  79. if (hprt0 & HPRT0_ENACHG) {
  80. hprt0 &= ~HPRT0_ENA;
  81. dwc2_writel(hprt0, hsotg->regs + HPRT0);
  82. }
  83. }
  84. /**
  85. * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  86. *
  87. * @hsotg: Programming view of DWC_otg controller
  88. */
  89. static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  90. {
  91. /* Clear interrupt */
  92. dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
  93. dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
  94. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  95. }
  96. /**
  97. * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
  98. * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
  99. *
  100. * @hsotg: Programming view of DWC_otg controller
  101. */
  102. static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
  103. {
  104. u32 gotgint;
  105. u32 gotgctl;
  106. u32 gintmsk;
  107. gotgint = dwc2_readl(hsotg->regs + GOTGINT);
  108. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  109. dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
  110. dwc2_op_state_str(hsotg));
  111. if (gotgint & GOTGINT_SES_END_DET) {
  112. dev_dbg(hsotg->dev,
  113. " ++OTG Interrupt: Session End Detected++ (%s)\n",
  114. dwc2_op_state_str(hsotg));
  115. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  116. if (dwc2_is_device_mode(hsotg))
  117. dwc2_hsotg_disconnect(hsotg);
  118. if (hsotg->op_state == OTG_STATE_B_HOST) {
  119. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  120. } else {
  121. /*
  122. * If not B_HOST and Device HNP still set, HNP did
  123. * not succeed!
  124. */
  125. if (gotgctl & GOTGCTL_DEVHNPEN) {
  126. dev_dbg(hsotg->dev, "Session End Detected\n");
  127. dev_err(hsotg->dev,
  128. "Device Not Connected/Responding!\n");
  129. }
  130. /*
  131. * If Session End Detected the B-Cable has been
  132. * disconnected
  133. */
  134. /* Reset to a clean state */
  135. hsotg->lx_state = DWC2_L0;
  136. }
  137. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  138. gotgctl &= ~GOTGCTL_DEVHNPEN;
  139. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  140. }
  141. if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
  142. dev_dbg(hsotg->dev,
  143. " ++OTG Interrupt: Session Request Success Status Change++\n");
  144. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  145. if (gotgctl & GOTGCTL_SESREQSCS) {
  146. if (hsotg->core_params->phy_type ==
  147. DWC2_PHY_TYPE_PARAM_FS
  148. && hsotg->core_params->i2c_enable > 0) {
  149. hsotg->srp_success = 1;
  150. } else {
  151. /* Clear Session Request */
  152. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  153. gotgctl &= ~GOTGCTL_SESREQ;
  154. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  155. }
  156. }
  157. }
  158. if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
  159. /*
  160. * Print statements during the HNP interrupt handling
  161. * can cause it to fail
  162. */
  163. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  164. /*
  165. * WA for 3.00a- HW is not setting cur_mode, even sometimes
  166. * this does not help
  167. */
  168. if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
  169. udelay(100);
  170. if (gotgctl & GOTGCTL_HSTNEGSCS) {
  171. if (dwc2_is_host_mode(hsotg)) {
  172. hsotg->op_state = OTG_STATE_B_HOST;
  173. /*
  174. * Need to disable SOF interrupt immediately.
  175. * When switching from device to host, the PCD
  176. * interrupt handler won't handle the interrupt
  177. * if host mode is already set. The HCD
  178. * interrupt handler won't get called if the
  179. * HCD state is HALT. This means that the
  180. * interrupt does not get handled and Linux
  181. * complains loudly.
  182. */
  183. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  184. gintmsk &= ~GINTSTS_SOF;
  185. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  186. /*
  187. * Call callback function with spin lock
  188. * released
  189. */
  190. spin_unlock(&hsotg->lock);
  191. /* Initialize the Core for Host mode */
  192. dwc2_hcd_start(hsotg);
  193. spin_lock(&hsotg->lock);
  194. hsotg->op_state = OTG_STATE_B_HOST;
  195. }
  196. } else {
  197. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  198. gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
  199. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  200. dev_dbg(hsotg->dev, "HNP Failed\n");
  201. dev_err(hsotg->dev,
  202. "Device Not Connected/Responding\n");
  203. }
  204. }
  205. if (gotgint & GOTGINT_HST_NEG_DET) {
  206. /*
  207. * The disconnect interrupt is set at the same time as
  208. * Host Negotiation Detected. During the mode switch all
  209. * interrupts are cleared so the disconnect interrupt
  210. * handler will not get executed.
  211. */
  212. dev_dbg(hsotg->dev,
  213. " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
  214. (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
  215. if (dwc2_is_device_mode(hsotg)) {
  216. dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
  217. hsotg->op_state);
  218. spin_unlock(&hsotg->lock);
  219. dwc2_hcd_disconnect(hsotg, false);
  220. spin_lock(&hsotg->lock);
  221. hsotg->op_state = OTG_STATE_A_PERIPHERAL;
  222. } else {
  223. /* Need to disable SOF interrupt immediately */
  224. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  225. gintmsk &= ~GINTSTS_SOF;
  226. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  227. spin_unlock(&hsotg->lock);
  228. dwc2_hcd_start(hsotg);
  229. spin_lock(&hsotg->lock);
  230. hsotg->op_state = OTG_STATE_A_HOST;
  231. }
  232. }
  233. if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
  234. dev_dbg(hsotg->dev,
  235. " ++OTG Interrupt: A-Device Timeout Change++\n");
  236. if (gotgint & GOTGINT_DBNCE_DONE)
  237. dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
  238. /* Clear GOTGINT */
  239. dwc2_writel(gotgint, hsotg->regs + GOTGINT);
  240. }
  241. /**
  242. * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
  243. * Change Interrupt
  244. *
  245. * @hsotg: Programming view of DWC_otg controller
  246. *
  247. * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
  248. * Device to Host Mode transition or a Host to Device Mode transition. This only
  249. * occurs when the cable is connected/removed from the PHY connector.
  250. */
  251. static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
  252. {
  253. u32 gintmsk;
  254. /* Clear interrupt */
  255. dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
  256. /* Need to disable SOF interrupt immediately */
  257. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  258. gintmsk &= ~GINTSTS_SOF;
  259. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  260. dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
  261. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  262. /*
  263. * Need to schedule a work, as there are possible DELAY function calls.
  264. * Release lock before scheduling workq as it holds spinlock during
  265. * scheduling.
  266. */
  267. if (hsotg->wq_otg) {
  268. spin_unlock(&hsotg->lock);
  269. queue_work(hsotg->wq_otg, &hsotg->wf_otg);
  270. spin_lock(&hsotg->lock);
  271. }
  272. }
  273. /**
  274. * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
  275. * initiating the Session Request Protocol to request the host to turn on bus
  276. * power so a new session can begin
  277. *
  278. * @hsotg: Programming view of DWC_otg controller
  279. *
  280. * This handler responds by turning on bus power. If the DWC_otg controller is
  281. * in low power mode, this handler brings the controller out of low power mode
  282. * before turning on bus power.
  283. */
  284. static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
  285. {
  286. int ret;
  287. /* Clear interrupt */
  288. dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
  289. dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
  290. hsotg->lx_state);
  291. if (dwc2_is_device_mode(hsotg)) {
  292. if (hsotg->lx_state == DWC2_L2) {
  293. ret = dwc2_exit_hibernation(hsotg, true);
  294. if (ret && (ret != -ENOTSUPP))
  295. dev_err(hsotg->dev,
  296. "exit hibernation failed\n");
  297. }
  298. /*
  299. * Report disconnect if there is any previous session
  300. * established
  301. */
  302. dwc2_hsotg_disconnect(hsotg);
  303. }
  304. }
  305. /*
  306. * This interrupt indicates that the DWC_otg controller has detected a
  307. * resume or remote wakeup sequence. If the DWC_otg controller is in
  308. * low power mode, the handler must brings the controller out of low
  309. * power mode. The controller automatically begins resume signaling.
  310. * The handler schedules a time to stop resume signaling.
  311. */
  312. static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
  313. {
  314. int ret;
  315. /* Clear interrupt */
  316. dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
  317. dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
  318. dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
  319. if (dwc2_is_device_mode(hsotg)) {
  320. dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
  321. dwc2_readl(hsotg->regs + DSTS));
  322. if (hsotg->lx_state == DWC2_L2) {
  323. u32 dctl = dwc2_readl(hsotg->regs + DCTL);
  324. /* Clear Remote Wakeup Signaling */
  325. dctl &= ~DCTL_RMTWKUPSIG;
  326. dwc2_writel(dctl, hsotg->regs + DCTL);
  327. ret = dwc2_exit_hibernation(hsotg, true);
  328. if (ret && (ret != -ENOTSUPP))
  329. dev_err(hsotg->dev, "exit hibernation failed\n");
  330. call_gadget(hsotg, resume);
  331. }
  332. /* Change to L0 state */
  333. hsotg->lx_state = DWC2_L0;
  334. } else {
  335. if (hsotg->core_params->hibernation)
  336. return;
  337. if (hsotg->lx_state != DWC2_L1) {
  338. u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
  339. /* Restart the Phy Clock */
  340. pcgcctl &= ~PCGCTL_STOPPCLK;
  341. dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
  342. mod_timer(&hsotg->wkp_timer,
  343. jiffies + msecs_to_jiffies(71));
  344. } else {
  345. /* Change to L0 state */
  346. hsotg->lx_state = DWC2_L0;
  347. }
  348. }
  349. }
  350. /*
  351. * This interrupt indicates that a device has been disconnected from the
  352. * root port
  353. */
  354. static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
  355. {
  356. dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
  357. dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
  358. dwc2_is_host_mode(hsotg) ? "Host" : "Device",
  359. dwc2_op_state_str(hsotg));
  360. if (hsotg->op_state == OTG_STATE_A_HOST)
  361. dwc2_hcd_disconnect(hsotg, false);
  362. }
  363. /*
  364. * This interrupt indicates that SUSPEND state has been detected on the USB.
  365. *
  366. * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
  367. * to "a_host".
  368. *
  369. * When power management is enabled the core will be put in low power mode.
  370. */
  371. static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
  372. {
  373. u32 dsts;
  374. int ret;
  375. /* Clear interrupt */
  376. dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
  377. dev_dbg(hsotg->dev, "USB SUSPEND\n");
  378. if (dwc2_is_device_mode(hsotg)) {
  379. /*
  380. * Check the Device status register to determine if the Suspend
  381. * state is active
  382. */
  383. dsts = dwc2_readl(hsotg->regs + DSTS);
  384. dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
  385. dev_dbg(hsotg->dev,
  386. "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
  387. !!(dsts & DSTS_SUSPSTS),
  388. hsotg->hw_params.power_optimized);
  389. if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) {
  390. /* Ignore suspend request before enumeration */
  391. if (!dwc2_is_device_connected(hsotg)) {
  392. dev_dbg(hsotg->dev,
  393. "ignore suspend request before enumeration\n");
  394. return;
  395. }
  396. ret = dwc2_enter_hibernation(hsotg);
  397. if (ret) {
  398. if (ret != -ENOTSUPP)
  399. dev_err(hsotg->dev,
  400. "enter hibernation failed\n");
  401. goto skip_power_saving;
  402. }
  403. udelay(100);
  404. /* Ask phy to be suspended */
  405. if (!IS_ERR_OR_NULL(hsotg->uphy))
  406. usb_phy_set_suspend(hsotg->uphy, true);
  407. skip_power_saving:
  408. /*
  409. * Change to L2 (suspend) state before releasing
  410. * spinlock
  411. */
  412. hsotg->lx_state = DWC2_L2;
  413. /* Call gadget suspend callback */
  414. call_gadget(hsotg, suspend);
  415. }
  416. } else {
  417. if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
  418. dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
  419. /* Change to L2 (suspend) state */
  420. hsotg->lx_state = DWC2_L2;
  421. /* Clear the a_peripheral flag, back to a_host */
  422. spin_unlock(&hsotg->lock);
  423. dwc2_hcd_start(hsotg);
  424. spin_lock(&hsotg->lock);
  425. hsotg->op_state = OTG_STATE_A_HOST;
  426. }
  427. }
  428. }
  429. #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
  430. GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
  431. GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
  432. GINTSTS_USBSUSP | GINTSTS_PRTINT)
  433. /*
  434. * This function returns the Core Interrupt register
  435. */
  436. static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
  437. {
  438. u32 gintsts;
  439. u32 gintmsk;
  440. u32 gahbcfg;
  441. u32 gintmsk_common = GINTMSK_COMMON;
  442. gintsts = dwc2_readl(hsotg->regs + GINTSTS);
  443. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  444. gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  445. /* If any common interrupts set */
  446. if (gintsts & gintmsk_common)
  447. dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
  448. gintsts, gintmsk);
  449. if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
  450. return gintsts & gintmsk & gintmsk_common;
  451. else
  452. return 0;
  453. }
  454. /*
  455. * Common interrupt handler
  456. *
  457. * The common interrupts are those that occur in both Host and Device mode.
  458. * This handler handles the following interrupts:
  459. * - Mode Mismatch Interrupt
  460. * - OTG Interrupt
  461. * - Connector ID Status Change Interrupt
  462. * - Disconnect Interrupt
  463. * - Session Request Interrupt
  464. * - Resume / Remote Wakeup Detected Interrupt
  465. * - Suspend Interrupt
  466. */
  467. irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
  468. {
  469. struct dwc2_hsotg *hsotg = dev;
  470. u32 gintsts;
  471. irqreturn_t retval = IRQ_NONE;
  472. spin_lock(&hsotg->lock);
  473. if (!dwc2_is_controller_alive(hsotg)) {
  474. dev_warn(hsotg->dev, "Controller is dead\n");
  475. goto out;
  476. }
  477. gintsts = dwc2_read_common_intr(hsotg);
  478. if (gintsts & ~GINTSTS_PRTINT)
  479. retval = IRQ_HANDLED;
  480. if (gintsts & GINTSTS_MODEMIS)
  481. dwc2_handle_mode_mismatch_intr(hsotg);
  482. if (gintsts & GINTSTS_OTGINT)
  483. dwc2_handle_otg_intr(hsotg);
  484. if (gintsts & GINTSTS_CONIDSTSCHNG)
  485. dwc2_handle_conn_id_status_change_intr(hsotg);
  486. if (gintsts & GINTSTS_DISCONNINT)
  487. dwc2_handle_disconnect_intr(hsotg);
  488. if (gintsts & GINTSTS_SESSREQINT)
  489. dwc2_handle_session_req_intr(hsotg);
  490. if (gintsts & GINTSTS_WKUPINT)
  491. dwc2_handle_wakeup_detected_intr(hsotg);
  492. if (gintsts & GINTSTS_USBSUSP)
  493. dwc2_handle_usb_suspend_intr(hsotg);
  494. if (gintsts & GINTSTS_PRTINT) {
  495. /*
  496. * The port interrupt occurs while in device mode with HPRT0
  497. * Port Enable/Disable
  498. */
  499. if (dwc2_is_device_mode(hsotg)) {
  500. dev_dbg(hsotg->dev,
  501. " --Port interrupt received in Device mode--\n");
  502. dwc2_handle_usb_port_intr(hsotg);
  503. retval = IRQ_HANDLED;
  504. }
  505. }
  506. out:
  507. spin_unlock(&hsotg->lock);
  508. return retval;
  509. }