mv_sas.c 54 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; version 2 of the
  13. * License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include "mv_sas.h"
  26. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  27. {
  28. if (task->lldd_task) {
  29. struct mvs_slot_info *slot;
  30. slot = task->lldd_task;
  31. *tag = slot->slot_tag;
  32. return 1;
  33. }
  34. return 0;
  35. }
  36. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  37. {
  38. void *bitmap = mvi->tags;
  39. clear_bit(tag, bitmap);
  40. }
  41. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  42. {
  43. mvs_tag_clear(mvi, tag);
  44. }
  45. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  46. {
  47. void *bitmap = mvi->tags;
  48. set_bit(tag, bitmap);
  49. }
  50. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  51. {
  52. unsigned int index, tag;
  53. void *bitmap = mvi->tags;
  54. index = find_first_zero_bit(bitmap, mvi->tags_num);
  55. tag = index;
  56. if (tag >= mvi->tags_num)
  57. return -SAS_QUEUE_FULL;
  58. mvs_tag_set(mvi, tag);
  59. *tag_out = tag;
  60. return 0;
  61. }
  62. void mvs_tag_init(struct mvs_info *mvi)
  63. {
  64. int i;
  65. for (i = 0; i < mvi->tags_num; ++i)
  66. mvs_tag_clear(mvi, i);
  67. }
  68. static struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  69. {
  70. unsigned long i = 0, j = 0, hi = 0;
  71. struct sas_ha_struct *sha = dev->port->ha;
  72. struct mvs_info *mvi = NULL;
  73. struct asd_sas_phy *phy;
  74. while (sha->sas_port[i]) {
  75. if (sha->sas_port[i] == dev->port) {
  76. phy = container_of(sha->sas_port[i]->phy_list.next,
  77. struct asd_sas_phy, port_phy_el);
  78. j = 0;
  79. while (sha->sas_phy[j]) {
  80. if (sha->sas_phy[j] == phy)
  81. break;
  82. j++;
  83. }
  84. break;
  85. }
  86. i++;
  87. }
  88. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  89. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  90. return mvi;
  91. }
  92. static int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  93. {
  94. unsigned long i = 0, j = 0, n = 0, num = 0;
  95. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  96. struct mvs_info *mvi = mvi_dev->mvi_info;
  97. struct sas_ha_struct *sha = dev->port->ha;
  98. while (sha->sas_port[i]) {
  99. if (sha->sas_port[i] == dev->port) {
  100. struct asd_sas_phy *phy;
  101. list_for_each_entry(phy,
  102. &sha->sas_port[i]->phy_list, port_phy_el) {
  103. j = 0;
  104. while (sha->sas_phy[j]) {
  105. if (sha->sas_phy[j] == phy)
  106. break;
  107. j++;
  108. }
  109. phyno[n] = (j >= mvi->chip->n_phy) ?
  110. (j - mvi->chip->n_phy) : j;
  111. num++;
  112. n++;
  113. }
  114. break;
  115. }
  116. i++;
  117. }
  118. return num;
  119. }
  120. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  121. u8 reg_set)
  122. {
  123. u32 dev_no;
  124. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  125. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  126. continue;
  127. if (mvi->devices[dev_no].taskfileset == reg_set)
  128. return &mvi->devices[dev_no];
  129. }
  130. return NULL;
  131. }
  132. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  133. struct mvs_device *dev)
  134. {
  135. if (!dev) {
  136. mv_printk("device has been free.\n");
  137. return;
  138. }
  139. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  140. return;
  141. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  142. }
  143. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  144. struct mvs_device *dev)
  145. {
  146. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  147. return 0;
  148. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  149. }
  150. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  151. {
  152. u32 no;
  153. for_each_phy(phy_mask, phy_mask, no) {
  154. if (!(phy_mask & 1))
  155. continue;
  156. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  157. }
  158. }
  159. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  160. void *funcdata)
  161. {
  162. int rc = 0, phy_id = sas_phy->id;
  163. u32 tmp, i = 0, hi;
  164. struct sas_ha_struct *sha = sas_phy->ha;
  165. struct mvs_info *mvi = NULL;
  166. while (sha->sas_phy[i]) {
  167. if (sha->sas_phy[i] == sas_phy)
  168. break;
  169. i++;
  170. }
  171. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  172. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  173. switch (func) {
  174. case PHY_FUNC_SET_LINK_RATE:
  175. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  176. break;
  177. case PHY_FUNC_HARD_RESET:
  178. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  179. if (tmp & PHY_RST_HARD)
  180. break;
  181. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
  182. break;
  183. case PHY_FUNC_LINK_RESET:
  184. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  185. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
  186. break;
  187. case PHY_FUNC_DISABLE:
  188. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  189. break;
  190. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  191. default:
  192. rc = -ENOSYS;
  193. }
  194. msleep(200);
  195. return rc;
  196. }
  197. void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
  198. u32 off_hi, u64 sas_addr)
  199. {
  200. u32 lo = (u32)sas_addr;
  201. u32 hi = (u32)(sas_addr>>32);
  202. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  203. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  204. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  205. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  206. }
  207. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  208. {
  209. struct mvs_phy *phy = &mvi->phy[i];
  210. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  211. struct sas_ha_struct *sas_ha;
  212. if (!phy->phy_attached)
  213. return;
  214. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  215. && phy->phy_type & PORT_TYPE_SAS) {
  216. return;
  217. }
  218. sas_ha = mvi->sas;
  219. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  220. if (sas_phy->phy) {
  221. struct sas_phy *sphy = sas_phy->phy;
  222. sphy->negotiated_linkrate = sas_phy->linkrate;
  223. sphy->minimum_linkrate = phy->minimum_linkrate;
  224. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  225. sphy->maximum_linkrate = phy->maximum_linkrate;
  226. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  227. }
  228. if (phy->phy_type & PORT_TYPE_SAS) {
  229. struct sas_identify_frame *id;
  230. id = (struct sas_identify_frame *)phy->frame_rcvd;
  231. id->dev_type = phy->identify.device_type;
  232. id->initiator_bits = SAS_PROTOCOL_ALL;
  233. id->target_bits = phy->identify.target_port_protocols;
  234. /* direct attached SAS device */
  235. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  236. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  237. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
  238. }
  239. } else if (phy->phy_type & PORT_TYPE_SATA) {
  240. /*Nothing*/
  241. }
  242. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  243. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  244. mvi->sas->notify_port_event(sas_phy,
  245. PORTE_BYTES_DMAED);
  246. }
  247. void mvs_scan_start(struct Scsi_Host *shost)
  248. {
  249. int i, j;
  250. unsigned short core_nr;
  251. struct mvs_info *mvi;
  252. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  253. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  254. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  255. for (j = 0; j < core_nr; j++) {
  256. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  257. for (i = 0; i < mvi->chip->n_phy; ++i)
  258. mvs_bytes_dmaed(mvi, i);
  259. }
  260. mvs_prv->scan_finished = 1;
  261. }
  262. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  263. {
  264. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  265. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  266. if (mvs_prv->scan_finished == 0)
  267. return 0;
  268. sas_drain_work(sha);
  269. return 1;
  270. }
  271. static int mvs_task_prep_smp(struct mvs_info *mvi,
  272. struct mvs_task_exec_info *tei)
  273. {
  274. int elem, rc, i;
  275. struct sas_ha_struct *sha = mvi->sas;
  276. struct sas_task *task = tei->task;
  277. struct mvs_cmd_hdr *hdr = tei->hdr;
  278. struct domain_device *dev = task->dev;
  279. struct asd_sas_port *sas_port = dev->port;
  280. struct sas_phy *sphy = dev->phy;
  281. struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
  282. struct scatterlist *sg_req, *sg_resp;
  283. u32 req_len, resp_len, tag = tei->tag;
  284. void *buf_tmp;
  285. u8 *buf_oaf;
  286. dma_addr_t buf_tmp_dma;
  287. void *buf_prd;
  288. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  289. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  290. /*
  291. * DMA-map SMP request, response buffers
  292. */
  293. sg_req = &task->smp_task.smp_req;
  294. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  295. if (!elem)
  296. return -ENOMEM;
  297. req_len = sg_dma_len(sg_req);
  298. sg_resp = &task->smp_task.smp_resp;
  299. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  300. if (!elem) {
  301. rc = -ENOMEM;
  302. goto err_out;
  303. }
  304. resp_len = SB_RFB_MAX;
  305. /* must be in dwords */
  306. if ((req_len & 0x3) || (resp_len & 0x3)) {
  307. rc = -EINVAL;
  308. goto err_out_2;
  309. }
  310. /*
  311. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  312. */
  313. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  314. buf_tmp = slot->buf;
  315. buf_tmp_dma = slot->buf_dma;
  316. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  317. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  318. buf_oaf = buf_tmp;
  319. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  320. buf_tmp += MVS_OAF_SZ;
  321. buf_tmp_dma += MVS_OAF_SZ;
  322. /* region 3: PRD table *********************************** */
  323. buf_prd = buf_tmp;
  324. if (tei->n_elem)
  325. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  326. else
  327. hdr->prd_tbl = 0;
  328. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  329. buf_tmp += i;
  330. buf_tmp_dma += i;
  331. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  332. slot->response = buf_tmp;
  333. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  334. if (mvi->flags & MVF_FLAG_SOC)
  335. hdr->reserved[0] = 0;
  336. /*
  337. * Fill in TX ring and command slot header
  338. */
  339. slot->tx = mvi->tx_prod;
  340. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  341. TXQ_MODE_I | tag |
  342. (MVS_PHY_ID << TXQ_PHY_SHIFT));
  343. hdr->flags |= flags;
  344. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  345. hdr->tags = cpu_to_le32(tag);
  346. hdr->data_len = 0;
  347. /* generate open address frame hdr (first 12 bytes) */
  348. /* initiator, SMP, ftype 1h */
  349. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  350. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  351. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  352. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  353. /* fill in PRD (scatter/gather) table, if any */
  354. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  355. return 0;
  356. err_out_2:
  357. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  358. PCI_DMA_FROMDEVICE);
  359. err_out:
  360. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  361. PCI_DMA_TODEVICE);
  362. return rc;
  363. }
  364. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  365. {
  366. struct ata_queued_cmd *qc = task->uldd_task;
  367. if (qc) {
  368. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  369. qc->tf.command == ATA_CMD_FPDMA_READ ||
  370. qc->tf.command == ATA_CMD_FPDMA_RECV ||
  371. qc->tf.command == ATA_CMD_FPDMA_SEND ||
  372. qc->tf.command == ATA_CMD_NCQ_NON_DATA) {
  373. *tag = qc->tag;
  374. return 1;
  375. }
  376. }
  377. return 0;
  378. }
  379. static int mvs_task_prep_ata(struct mvs_info *mvi,
  380. struct mvs_task_exec_info *tei)
  381. {
  382. struct sas_task *task = tei->task;
  383. struct domain_device *dev = task->dev;
  384. struct mvs_device *mvi_dev = dev->lldd_dev;
  385. struct mvs_cmd_hdr *hdr = tei->hdr;
  386. struct asd_sas_port *sas_port = dev->port;
  387. struct mvs_slot_info *slot;
  388. void *buf_prd;
  389. u32 tag = tei->tag, hdr_tag;
  390. u32 flags, del_q;
  391. void *buf_tmp;
  392. u8 *buf_cmd, *buf_oaf;
  393. dma_addr_t buf_tmp_dma;
  394. u32 i, req_len, resp_len;
  395. const u32 max_resp_len = SB_RFB_MAX;
  396. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  397. mv_dprintk("Have not enough regiset for dev %d.\n",
  398. mvi_dev->device_id);
  399. return -EBUSY;
  400. }
  401. slot = &mvi->slot_info[tag];
  402. slot->tx = mvi->tx_prod;
  403. del_q = TXQ_MODE_I | tag |
  404. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  405. ((sas_port->phy_mask & TXQ_PHY_MASK) << TXQ_PHY_SHIFT) |
  406. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  407. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  408. if (task->data_dir == DMA_FROM_DEVICE)
  409. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  410. else
  411. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  412. if (task->ata_task.use_ncq)
  413. flags |= MCH_FPDMA;
  414. if (dev->sata_dev.class == ATA_DEV_ATAPI) {
  415. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  416. flags |= MCH_ATAPI;
  417. }
  418. hdr->flags = cpu_to_le32(flags);
  419. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  420. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  421. else
  422. hdr_tag = tag;
  423. hdr->tags = cpu_to_le32(hdr_tag);
  424. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  425. /*
  426. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  427. */
  428. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  429. buf_cmd = buf_tmp = slot->buf;
  430. buf_tmp_dma = slot->buf_dma;
  431. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  432. buf_tmp += MVS_ATA_CMD_SZ;
  433. buf_tmp_dma += MVS_ATA_CMD_SZ;
  434. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  435. /* used for STP. unused for SATA? */
  436. buf_oaf = buf_tmp;
  437. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  438. buf_tmp += MVS_OAF_SZ;
  439. buf_tmp_dma += MVS_OAF_SZ;
  440. /* region 3: PRD table ********************************************* */
  441. buf_prd = buf_tmp;
  442. if (tei->n_elem)
  443. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  444. else
  445. hdr->prd_tbl = 0;
  446. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  447. buf_tmp += i;
  448. buf_tmp_dma += i;
  449. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  450. slot->response = buf_tmp;
  451. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  452. if (mvi->flags & MVF_FLAG_SOC)
  453. hdr->reserved[0] = 0;
  454. req_len = sizeof(struct host_to_dev_fis);
  455. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  456. sizeof(struct mvs_err_info) - i;
  457. /* request, response lengths */
  458. resp_len = min(resp_len, max_resp_len);
  459. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  460. if (likely(!task->ata_task.device_control_reg_update))
  461. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  462. /* fill in command FIS and ATAPI CDB */
  463. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  464. if (dev->sata_dev.class == ATA_DEV_ATAPI)
  465. memcpy(buf_cmd + STP_ATAPI_CMD,
  466. task->ata_task.atapi_packet, 16);
  467. /* generate open address frame hdr (first 12 bytes) */
  468. /* initiator, STP, ftype 1h */
  469. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  470. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  471. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  472. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  473. /* fill in PRD (scatter/gather) table, if any */
  474. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  475. if (task->data_dir == DMA_FROM_DEVICE)
  476. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  477. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  478. return 0;
  479. }
  480. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  481. struct mvs_task_exec_info *tei, int is_tmf,
  482. struct mvs_tmf_task *tmf)
  483. {
  484. struct sas_task *task = tei->task;
  485. struct mvs_cmd_hdr *hdr = tei->hdr;
  486. struct mvs_port *port = tei->port;
  487. struct domain_device *dev = task->dev;
  488. struct mvs_device *mvi_dev = dev->lldd_dev;
  489. struct asd_sas_port *sas_port = dev->port;
  490. struct mvs_slot_info *slot;
  491. void *buf_prd;
  492. struct ssp_frame_hdr *ssp_hdr;
  493. void *buf_tmp;
  494. u8 *buf_cmd, *buf_oaf, fburst = 0;
  495. dma_addr_t buf_tmp_dma;
  496. u32 flags;
  497. u32 resp_len, req_len, i, tag = tei->tag;
  498. const u32 max_resp_len = SB_RFB_MAX;
  499. u32 phy_mask;
  500. slot = &mvi->slot_info[tag];
  501. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  502. sas_port->phy_mask) & TXQ_PHY_MASK;
  503. slot->tx = mvi->tx_prod;
  504. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  505. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  506. (phy_mask << TXQ_PHY_SHIFT));
  507. flags = MCH_RETRY;
  508. if (task->ssp_task.enable_first_burst) {
  509. flags |= MCH_FBURST;
  510. fburst = (1 << 7);
  511. }
  512. if (is_tmf)
  513. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  514. else
  515. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  516. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  517. hdr->tags = cpu_to_le32(tag);
  518. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  519. /*
  520. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  521. */
  522. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  523. buf_cmd = buf_tmp = slot->buf;
  524. buf_tmp_dma = slot->buf_dma;
  525. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  526. buf_tmp += MVS_SSP_CMD_SZ;
  527. buf_tmp_dma += MVS_SSP_CMD_SZ;
  528. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  529. buf_oaf = buf_tmp;
  530. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  531. buf_tmp += MVS_OAF_SZ;
  532. buf_tmp_dma += MVS_OAF_SZ;
  533. /* region 3: PRD table ********************************************* */
  534. buf_prd = buf_tmp;
  535. if (tei->n_elem)
  536. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  537. else
  538. hdr->prd_tbl = 0;
  539. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  540. buf_tmp += i;
  541. buf_tmp_dma += i;
  542. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  543. slot->response = buf_tmp;
  544. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  545. if (mvi->flags & MVF_FLAG_SOC)
  546. hdr->reserved[0] = 0;
  547. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  548. sizeof(struct mvs_err_info) - i;
  549. resp_len = min(resp_len, max_resp_len);
  550. req_len = sizeof(struct ssp_frame_hdr) + 28;
  551. /* request, response lengths */
  552. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  553. /* generate open address frame hdr (first 12 bytes) */
  554. /* initiator, SSP, ftype 1h */
  555. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  556. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  557. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  558. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  559. /* fill in SSP frame header (Command Table.SSP frame header) */
  560. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  561. if (is_tmf)
  562. ssp_hdr->frame_type = SSP_TASK;
  563. else
  564. ssp_hdr->frame_type = SSP_COMMAND;
  565. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  566. HASHED_SAS_ADDR_SIZE);
  567. memcpy(ssp_hdr->hashed_src_addr,
  568. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  569. ssp_hdr->tag = cpu_to_be16(tag);
  570. /* fill in IU for TASK and Command Frame */
  571. buf_cmd += sizeof(*ssp_hdr);
  572. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  573. if (ssp_hdr->frame_type != SSP_TASK) {
  574. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  575. (task->ssp_task.task_prio << 3);
  576. memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
  577. task->ssp_task.cmd->cmd_len);
  578. } else{
  579. buf_cmd[10] = tmf->tmf;
  580. switch (tmf->tmf) {
  581. case TMF_ABORT_TASK:
  582. case TMF_QUERY_TASK:
  583. buf_cmd[12] =
  584. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  585. buf_cmd[13] =
  586. tmf->tag_of_task_to_be_managed & 0xff;
  587. break;
  588. default:
  589. break;
  590. }
  591. }
  592. /* fill in PRD (scatter/gather) table, if any */
  593. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  594. return 0;
  595. }
  596. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == SAS_PHY_UNUSED)))
  597. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  598. struct mvs_tmf_task *tmf, int *pass)
  599. {
  600. struct domain_device *dev = task->dev;
  601. struct mvs_device *mvi_dev = dev->lldd_dev;
  602. struct mvs_task_exec_info tei;
  603. struct mvs_slot_info *slot;
  604. u32 tag = 0xdeadbeef, n_elem = 0;
  605. int rc = 0;
  606. if (!dev->port) {
  607. struct task_status_struct *tsm = &task->task_status;
  608. tsm->resp = SAS_TASK_UNDELIVERED;
  609. tsm->stat = SAS_PHY_DOWN;
  610. /*
  611. * libsas will use dev->port, should
  612. * not call task_done for sata
  613. */
  614. if (dev->dev_type != SAS_SATA_DEV)
  615. task->task_done(task);
  616. return rc;
  617. }
  618. if (DEV_IS_GONE(mvi_dev)) {
  619. if (mvi_dev)
  620. mv_dprintk("device %d not ready.\n",
  621. mvi_dev->device_id);
  622. else
  623. mv_dprintk("device %016llx not ready.\n",
  624. SAS_ADDR(dev->sas_addr));
  625. rc = SAS_PHY_DOWN;
  626. return rc;
  627. }
  628. tei.port = dev->port->lldd_port;
  629. if (tei.port && !tei.port->port_attached && !tmf) {
  630. if (sas_protocol_ata(task->task_proto)) {
  631. struct task_status_struct *ts = &task->task_status;
  632. mv_dprintk("SATA/STP port %d does not attach"
  633. "device.\n", dev->port->id);
  634. ts->resp = SAS_TASK_COMPLETE;
  635. ts->stat = SAS_PHY_DOWN;
  636. task->task_done(task);
  637. } else {
  638. struct task_status_struct *ts = &task->task_status;
  639. mv_dprintk("SAS port %d does not attach"
  640. "device.\n", dev->port->id);
  641. ts->resp = SAS_TASK_UNDELIVERED;
  642. ts->stat = SAS_PHY_DOWN;
  643. task->task_done(task);
  644. }
  645. return rc;
  646. }
  647. if (!sas_protocol_ata(task->task_proto)) {
  648. if (task->num_scatter) {
  649. n_elem = dma_map_sg(mvi->dev,
  650. task->scatter,
  651. task->num_scatter,
  652. task->data_dir);
  653. if (!n_elem) {
  654. rc = -ENOMEM;
  655. goto prep_out;
  656. }
  657. }
  658. } else {
  659. n_elem = task->num_scatter;
  660. }
  661. rc = mvs_tag_alloc(mvi, &tag);
  662. if (rc)
  663. goto err_out;
  664. slot = &mvi->slot_info[tag];
  665. task->lldd_task = NULL;
  666. slot->n_elem = n_elem;
  667. slot->slot_tag = tag;
  668. slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  669. if (!slot->buf) {
  670. rc = -ENOMEM;
  671. goto err_out_tag;
  672. }
  673. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  674. tei.task = task;
  675. tei.hdr = &mvi->slot[tag];
  676. tei.tag = tag;
  677. tei.n_elem = n_elem;
  678. switch (task->task_proto) {
  679. case SAS_PROTOCOL_SMP:
  680. rc = mvs_task_prep_smp(mvi, &tei);
  681. break;
  682. case SAS_PROTOCOL_SSP:
  683. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  684. break;
  685. case SAS_PROTOCOL_SATA:
  686. case SAS_PROTOCOL_STP:
  687. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  688. rc = mvs_task_prep_ata(mvi, &tei);
  689. break;
  690. default:
  691. dev_printk(KERN_ERR, mvi->dev,
  692. "unknown sas_task proto: 0x%x\n",
  693. task->task_proto);
  694. rc = -EINVAL;
  695. break;
  696. }
  697. if (rc) {
  698. mv_dprintk("rc is %x\n", rc);
  699. goto err_out_slot_buf;
  700. }
  701. slot->task = task;
  702. slot->port = tei.port;
  703. task->lldd_task = slot;
  704. list_add_tail(&slot->entry, &tei.port->list);
  705. spin_lock(&task->task_state_lock);
  706. task->task_state_flags |= SAS_TASK_AT_INITIATOR;
  707. spin_unlock(&task->task_state_lock);
  708. mvi_dev->running_req++;
  709. ++(*pass);
  710. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  711. return rc;
  712. err_out_slot_buf:
  713. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  714. err_out_tag:
  715. mvs_tag_free(mvi, tag);
  716. err_out:
  717. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  718. if (!sas_protocol_ata(task->task_proto))
  719. if (n_elem)
  720. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  721. task->data_dir);
  722. prep_out:
  723. return rc;
  724. }
  725. static int mvs_task_exec(struct sas_task *task, gfp_t gfp_flags,
  726. struct completion *completion, int is_tmf,
  727. struct mvs_tmf_task *tmf)
  728. {
  729. struct mvs_info *mvi = NULL;
  730. u32 rc = 0;
  731. u32 pass = 0;
  732. unsigned long flags = 0;
  733. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  734. spin_lock_irqsave(&mvi->lock, flags);
  735. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  736. if (rc)
  737. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  738. if (likely(pass))
  739. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  740. (MVS_CHIP_SLOT_SZ - 1));
  741. spin_unlock_irqrestore(&mvi->lock, flags);
  742. return rc;
  743. }
  744. int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags)
  745. {
  746. return mvs_task_exec(task, gfp_flags, NULL, 0, NULL);
  747. }
  748. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  749. {
  750. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  751. mvs_tag_clear(mvi, slot_idx);
  752. }
  753. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  754. struct mvs_slot_info *slot, u32 slot_idx)
  755. {
  756. if (!slot)
  757. return;
  758. if (!slot->task)
  759. return;
  760. if (!sas_protocol_ata(task->task_proto))
  761. if (slot->n_elem)
  762. dma_unmap_sg(mvi->dev, task->scatter,
  763. slot->n_elem, task->data_dir);
  764. switch (task->task_proto) {
  765. case SAS_PROTOCOL_SMP:
  766. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  767. PCI_DMA_FROMDEVICE);
  768. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  769. PCI_DMA_TODEVICE);
  770. break;
  771. case SAS_PROTOCOL_SATA:
  772. case SAS_PROTOCOL_STP:
  773. case SAS_PROTOCOL_SSP:
  774. default:
  775. /* do nothing */
  776. break;
  777. }
  778. if (slot->buf) {
  779. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  780. slot->buf = NULL;
  781. }
  782. list_del_init(&slot->entry);
  783. task->lldd_task = NULL;
  784. slot->task = NULL;
  785. slot->port = NULL;
  786. slot->slot_tag = 0xFFFFFFFF;
  787. mvs_slot_free(mvi, slot_idx);
  788. }
  789. static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
  790. {
  791. struct mvs_phy *phy = &mvi->phy[phy_no];
  792. struct mvs_port *port = phy->port;
  793. int j, no;
  794. for_each_phy(port->wide_port_phymap, j, no) {
  795. if (j & 1) {
  796. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  797. PHYR_WIDE_PORT);
  798. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  799. port->wide_port_phymap);
  800. } else {
  801. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  802. PHYR_WIDE_PORT);
  803. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  804. 0);
  805. }
  806. }
  807. }
  808. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  809. {
  810. u32 tmp;
  811. struct mvs_phy *phy = &mvi->phy[i];
  812. struct mvs_port *port = phy->port;
  813. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  814. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  815. if (!port)
  816. phy->phy_attached = 1;
  817. return tmp;
  818. }
  819. if (port) {
  820. if (phy->phy_type & PORT_TYPE_SAS) {
  821. port->wide_port_phymap &= ~(1U << i);
  822. if (!port->wide_port_phymap)
  823. port->port_attached = 0;
  824. mvs_update_wideport(mvi, i);
  825. } else if (phy->phy_type & PORT_TYPE_SATA)
  826. port->port_attached = 0;
  827. phy->port = NULL;
  828. phy->phy_attached = 0;
  829. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  830. }
  831. return 0;
  832. }
  833. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  834. {
  835. u32 *s = (u32 *) buf;
  836. if (!s)
  837. return NULL;
  838. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  839. s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  840. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  841. s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  842. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  843. s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  844. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  845. s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  846. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  847. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  848. return s;
  849. }
  850. static u32 mvs_is_sig_fis_received(u32 irq_status)
  851. {
  852. return irq_status & PHYEV_SIG_FIS;
  853. }
  854. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  855. {
  856. if (phy->timer.function)
  857. del_timer(&phy->timer);
  858. phy->timer.function = NULL;
  859. }
  860. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  861. {
  862. struct mvs_phy *phy = &mvi->phy[i];
  863. struct sas_identify_frame *id;
  864. id = (struct sas_identify_frame *)phy->frame_rcvd;
  865. if (get_st) {
  866. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  867. phy->phy_status = mvs_is_phy_ready(mvi, i);
  868. }
  869. if (phy->phy_status) {
  870. int oob_done = 0;
  871. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  872. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  873. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  874. if (phy->phy_type & PORT_TYPE_SATA) {
  875. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  876. if (mvs_is_sig_fis_received(phy->irq_status)) {
  877. mvs_sig_remove_timer(phy);
  878. phy->phy_attached = 1;
  879. phy->att_dev_sas_addr =
  880. i + mvi->id * mvi->chip->n_phy;
  881. if (oob_done)
  882. sas_phy->oob_mode = SATA_OOB_MODE;
  883. phy->frame_rcvd_size =
  884. sizeof(struct dev_to_host_fis);
  885. mvs_get_d2h_reg(mvi, i, id);
  886. } else {
  887. u32 tmp;
  888. dev_printk(KERN_DEBUG, mvi->dev,
  889. "Phy%d : No sig fis\n", i);
  890. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  891. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  892. tmp | PHYEV_SIG_FIS);
  893. phy->phy_attached = 0;
  894. phy->phy_type &= ~PORT_TYPE_SATA;
  895. goto out_done;
  896. }
  897. } else if (phy->phy_type & PORT_TYPE_SAS
  898. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  899. phy->phy_attached = 1;
  900. phy->identify.device_type =
  901. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  902. if (phy->identify.device_type == SAS_END_DEVICE)
  903. phy->identify.target_port_protocols =
  904. SAS_PROTOCOL_SSP;
  905. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  906. phy->identify.target_port_protocols =
  907. SAS_PROTOCOL_SMP;
  908. if (oob_done)
  909. sas_phy->oob_mode = SAS_OOB_MODE;
  910. phy->frame_rcvd_size =
  911. sizeof(struct sas_identify_frame);
  912. }
  913. memcpy(sas_phy->attached_sas_addr,
  914. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  915. if (MVS_CHIP_DISP->phy_work_around)
  916. MVS_CHIP_DISP->phy_work_around(mvi, i);
  917. }
  918. mv_dprintk("phy %d attach dev info is %x\n",
  919. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  920. mv_dprintk("phy %d attach sas addr is %llx\n",
  921. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  922. out_done:
  923. if (get_st)
  924. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  925. }
  926. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  927. {
  928. struct sas_ha_struct *sas_ha = sas_phy->ha;
  929. struct mvs_info *mvi = NULL; int i = 0, hi;
  930. struct mvs_phy *phy = sas_phy->lldd_phy;
  931. struct asd_sas_port *sas_port = sas_phy->port;
  932. struct mvs_port *port;
  933. unsigned long flags = 0;
  934. if (!sas_port)
  935. return;
  936. while (sas_ha->sas_phy[i]) {
  937. if (sas_ha->sas_phy[i] == sas_phy)
  938. break;
  939. i++;
  940. }
  941. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  942. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  943. if (i >= mvi->chip->n_phy)
  944. port = &mvi->port[i - mvi->chip->n_phy];
  945. else
  946. port = &mvi->port[i];
  947. if (lock)
  948. spin_lock_irqsave(&mvi->lock, flags);
  949. port->port_attached = 1;
  950. phy->port = port;
  951. sas_port->lldd_port = port;
  952. if (phy->phy_type & PORT_TYPE_SAS) {
  953. port->wide_port_phymap = sas_port->phy_mask;
  954. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  955. mvs_update_wideport(mvi, sas_phy->id);
  956. /* direct attached SAS device */
  957. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  958. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  959. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
  960. }
  961. }
  962. if (lock)
  963. spin_unlock_irqrestore(&mvi->lock, flags);
  964. }
  965. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  966. {
  967. struct domain_device *dev;
  968. struct mvs_phy *phy = sas_phy->lldd_phy;
  969. struct mvs_info *mvi = phy->mvi;
  970. struct asd_sas_port *port = sas_phy->port;
  971. int phy_no = 0;
  972. while (phy != &mvi->phy[phy_no]) {
  973. phy_no++;
  974. if (phy_no >= MVS_MAX_PHYS)
  975. return;
  976. }
  977. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  978. mvs_do_release_task(phy->mvi, phy_no, dev);
  979. }
  980. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  981. {
  982. mvs_port_notify_formed(sas_phy, 1);
  983. }
  984. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  985. {
  986. mvs_port_notify_deformed(sas_phy, 1);
  987. }
  988. static struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  989. {
  990. u32 dev;
  991. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  992. if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
  993. mvi->devices[dev].device_id = dev;
  994. return &mvi->devices[dev];
  995. }
  996. }
  997. if (dev == MVS_MAX_DEVICES)
  998. mv_printk("max support %d devices, ignore ..\n",
  999. MVS_MAX_DEVICES);
  1000. return NULL;
  1001. }
  1002. static void mvs_free_dev(struct mvs_device *mvi_dev)
  1003. {
  1004. u32 id = mvi_dev->device_id;
  1005. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1006. mvi_dev->device_id = id;
  1007. mvi_dev->dev_type = SAS_PHY_UNUSED;
  1008. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1009. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1010. }
  1011. static int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1012. {
  1013. unsigned long flags = 0;
  1014. int res = 0;
  1015. struct mvs_info *mvi = NULL;
  1016. struct domain_device *parent_dev = dev->parent;
  1017. struct mvs_device *mvi_device;
  1018. mvi = mvs_find_dev_mvi(dev);
  1019. if (lock)
  1020. spin_lock_irqsave(&mvi->lock, flags);
  1021. mvi_device = mvs_alloc_dev(mvi);
  1022. if (!mvi_device) {
  1023. res = -1;
  1024. goto found_out;
  1025. }
  1026. dev->lldd_dev = mvi_device;
  1027. mvi_device->dev_status = MVS_DEV_NORMAL;
  1028. mvi_device->dev_type = dev->dev_type;
  1029. mvi_device->mvi_info = mvi;
  1030. mvi_device->sas_device = dev;
  1031. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1032. int phy_id;
  1033. u8 phy_num = parent_dev->ex_dev.num_phys;
  1034. struct ex_phy *phy;
  1035. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1036. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1037. if (SAS_ADDR(phy->attached_sas_addr) ==
  1038. SAS_ADDR(dev->sas_addr)) {
  1039. mvi_device->attached_phy = phy_id;
  1040. break;
  1041. }
  1042. }
  1043. if (phy_id == phy_num) {
  1044. mv_printk("Error: no attached dev:%016llx"
  1045. "at ex:%016llx.\n",
  1046. SAS_ADDR(dev->sas_addr),
  1047. SAS_ADDR(parent_dev->sas_addr));
  1048. res = -1;
  1049. }
  1050. }
  1051. found_out:
  1052. if (lock)
  1053. spin_unlock_irqrestore(&mvi->lock, flags);
  1054. return res;
  1055. }
  1056. int mvs_dev_found(struct domain_device *dev)
  1057. {
  1058. return mvs_dev_found_notify(dev, 1);
  1059. }
  1060. static void mvs_dev_gone_notify(struct domain_device *dev)
  1061. {
  1062. unsigned long flags = 0;
  1063. struct mvs_device *mvi_dev = dev->lldd_dev;
  1064. struct mvs_info *mvi;
  1065. if (!mvi_dev) {
  1066. mv_dprintk("found dev has gone.\n");
  1067. return;
  1068. }
  1069. mvi = mvi_dev->mvi_info;
  1070. spin_lock_irqsave(&mvi->lock, flags);
  1071. mv_dprintk("found dev[%d:%x] is gone.\n",
  1072. mvi_dev->device_id, mvi_dev->dev_type);
  1073. mvs_release_task(mvi, dev);
  1074. mvs_free_reg_set(mvi, mvi_dev);
  1075. mvs_free_dev(mvi_dev);
  1076. dev->lldd_dev = NULL;
  1077. mvi_dev->sas_device = NULL;
  1078. spin_unlock_irqrestore(&mvi->lock, flags);
  1079. }
  1080. void mvs_dev_gone(struct domain_device *dev)
  1081. {
  1082. mvs_dev_gone_notify(dev);
  1083. }
  1084. static void mvs_task_done(struct sas_task *task)
  1085. {
  1086. if (!del_timer(&task->slow_task->timer))
  1087. return;
  1088. complete(&task->slow_task->completion);
  1089. }
  1090. static void mvs_tmf_timedout(unsigned long data)
  1091. {
  1092. struct sas_task *task = (struct sas_task *)data;
  1093. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1094. complete(&task->slow_task->completion);
  1095. }
  1096. #define MVS_TASK_TIMEOUT 20
  1097. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1098. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1099. {
  1100. int res, retry;
  1101. struct sas_task *task = NULL;
  1102. for (retry = 0; retry < 3; retry++) {
  1103. task = sas_alloc_slow_task(GFP_KERNEL);
  1104. if (!task)
  1105. return -ENOMEM;
  1106. task->dev = dev;
  1107. task->task_proto = dev->tproto;
  1108. memcpy(&task->ssp_task, parameter, para_len);
  1109. task->task_done = mvs_task_done;
  1110. task->slow_task->timer.data = (unsigned long) task;
  1111. task->slow_task->timer.function = mvs_tmf_timedout;
  1112. task->slow_task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1113. add_timer(&task->slow_task->timer);
  1114. res = mvs_task_exec(task, GFP_KERNEL, NULL, 1, tmf);
  1115. if (res) {
  1116. del_timer(&task->slow_task->timer);
  1117. mv_printk("executing internal task failed:%d\n", res);
  1118. goto ex_err;
  1119. }
  1120. wait_for_completion(&task->slow_task->completion);
  1121. res = TMF_RESP_FUNC_FAILED;
  1122. /* Even TMF timed out, return direct. */
  1123. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1124. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1125. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1126. goto ex_err;
  1127. }
  1128. }
  1129. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1130. task->task_status.stat == SAM_STAT_GOOD) {
  1131. res = TMF_RESP_FUNC_COMPLETE;
  1132. break;
  1133. }
  1134. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1135. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1136. /* no error, but return the number of bytes of
  1137. * underrun */
  1138. res = task->task_status.residual;
  1139. break;
  1140. }
  1141. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1142. task->task_status.stat == SAS_DATA_OVERRUN) {
  1143. mv_dprintk("blocked task error.\n");
  1144. res = -EMSGSIZE;
  1145. break;
  1146. } else {
  1147. mv_dprintk(" task to dev %016llx response: 0x%x "
  1148. "status 0x%x\n",
  1149. SAS_ADDR(dev->sas_addr),
  1150. task->task_status.resp,
  1151. task->task_status.stat);
  1152. sas_free_task(task);
  1153. task = NULL;
  1154. }
  1155. }
  1156. ex_err:
  1157. BUG_ON(retry == 3 && task != NULL);
  1158. sas_free_task(task);
  1159. return res;
  1160. }
  1161. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1162. u8 *lun, struct mvs_tmf_task *tmf)
  1163. {
  1164. struct sas_ssp_task ssp_task;
  1165. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1166. return TMF_RESP_FUNC_ESUPP;
  1167. memcpy(ssp_task.LUN, lun, 8);
  1168. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1169. sizeof(ssp_task), tmf);
  1170. }
  1171. /* Standard mandates link reset for ATA (type 0)
  1172. and hard reset for SSP (type 1) , only for RECOVERY */
  1173. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1174. {
  1175. int rc;
  1176. struct sas_phy *phy = sas_get_local_phy(dev);
  1177. int reset_type = (dev->dev_type == SAS_SATA_DEV ||
  1178. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1179. rc = sas_phy_reset(phy, reset_type);
  1180. sas_put_local_phy(phy);
  1181. msleep(2000);
  1182. return rc;
  1183. }
  1184. /* mandatory SAM-3 */
  1185. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1186. {
  1187. unsigned long flags;
  1188. int rc = TMF_RESP_FUNC_FAILED;
  1189. struct mvs_tmf_task tmf_task;
  1190. struct mvs_device * mvi_dev = dev->lldd_dev;
  1191. struct mvs_info *mvi = mvi_dev->mvi_info;
  1192. tmf_task.tmf = TMF_LU_RESET;
  1193. mvi_dev->dev_status = MVS_DEV_EH;
  1194. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1195. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1196. spin_lock_irqsave(&mvi->lock, flags);
  1197. mvs_release_task(mvi, dev);
  1198. spin_unlock_irqrestore(&mvi->lock, flags);
  1199. }
  1200. /* If failed, fall-through I_T_Nexus reset */
  1201. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1202. mvi_dev->device_id, rc);
  1203. return rc;
  1204. }
  1205. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1206. {
  1207. unsigned long flags;
  1208. int rc = TMF_RESP_FUNC_FAILED;
  1209. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1210. struct mvs_info *mvi = mvi_dev->mvi_info;
  1211. if (mvi_dev->dev_status != MVS_DEV_EH)
  1212. return TMF_RESP_FUNC_COMPLETE;
  1213. else
  1214. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1215. rc = mvs_debug_I_T_nexus_reset(dev);
  1216. mv_printk("%s for device[%x]:rc= %d\n",
  1217. __func__, mvi_dev->device_id, rc);
  1218. spin_lock_irqsave(&mvi->lock, flags);
  1219. mvs_release_task(mvi, dev);
  1220. spin_unlock_irqrestore(&mvi->lock, flags);
  1221. return rc;
  1222. }
  1223. /* optional SAM-3 */
  1224. int mvs_query_task(struct sas_task *task)
  1225. {
  1226. u32 tag;
  1227. struct scsi_lun lun;
  1228. struct mvs_tmf_task tmf_task;
  1229. int rc = TMF_RESP_FUNC_FAILED;
  1230. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1231. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1232. struct domain_device *dev = task->dev;
  1233. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1234. struct mvs_info *mvi = mvi_dev->mvi_info;
  1235. int_to_scsilun(cmnd->device->lun, &lun);
  1236. rc = mvs_find_tag(mvi, task, &tag);
  1237. if (rc == 0) {
  1238. rc = TMF_RESP_FUNC_FAILED;
  1239. return rc;
  1240. }
  1241. tmf_task.tmf = TMF_QUERY_TASK;
  1242. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1243. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1244. switch (rc) {
  1245. /* The task is still in Lun, release it then */
  1246. case TMF_RESP_FUNC_SUCC:
  1247. /* The task is not in Lun or failed, reset the phy */
  1248. case TMF_RESP_FUNC_FAILED:
  1249. case TMF_RESP_FUNC_COMPLETE:
  1250. break;
  1251. }
  1252. }
  1253. mv_printk("%s:rc= %d\n", __func__, rc);
  1254. return rc;
  1255. }
  1256. /* mandatory SAM-3, still need free task/slot info */
  1257. int mvs_abort_task(struct sas_task *task)
  1258. {
  1259. struct scsi_lun lun;
  1260. struct mvs_tmf_task tmf_task;
  1261. struct domain_device *dev = task->dev;
  1262. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1263. struct mvs_info *mvi;
  1264. int rc = TMF_RESP_FUNC_FAILED;
  1265. unsigned long flags;
  1266. u32 tag;
  1267. if (!mvi_dev) {
  1268. mv_printk("Device has removed\n");
  1269. return TMF_RESP_FUNC_FAILED;
  1270. }
  1271. mvi = mvi_dev->mvi_info;
  1272. spin_lock_irqsave(&task->task_state_lock, flags);
  1273. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1274. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1275. rc = TMF_RESP_FUNC_COMPLETE;
  1276. goto out;
  1277. }
  1278. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1279. mvi_dev->dev_status = MVS_DEV_EH;
  1280. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1281. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1282. int_to_scsilun(cmnd->device->lun, &lun);
  1283. rc = mvs_find_tag(mvi, task, &tag);
  1284. if (rc == 0) {
  1285. mv_printk("No such tag in %s\n", __func__);
  1286. rc = TMF_RESP_FUNC_FAILED;
  1287. return rc;
  1288. }
  1289. tmf_task.tmf = TMF_ABORT_TASK;
  1290. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1291. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1292. /* if successful, clear the task and callback forwards.*/
  1293. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1294. u32 slot_no;
  1295. struct mvs_slot_info *slot;
  1296. if (task->lldd_task) {
  1297. slot = task->lldd_task;
  1298. slot_no = (u32) (slot - mvi->slot_info);
  1299. spin_lock_irqsave(&mvi->lock, flags);
  1300. mvs_slot_complete(mvi, slot_no, 1);
  1301. spin_unlock_irqrestore(&mvi->lock, flags);
  1302. }
  1303. }
  1304. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1305. task->task_proto & SAS_PROTOCOL_STP) {
  1306. if (SAS_SATA_DEV == dev->dev_type) {
  1307. struct mvs_slot_info *slot = task->lldd_task;
  1308. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1309. mv_dprintk("mvs_abort_task() mvi=%p task=%p "
  1310. "slot=%p slot_idx=x%x\n",
  1311. mvi, task, slot, slot_idx);
  1312. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1313. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1314. rc = TMF_RESP_FUNC_COMPLETE;
  1315. goto out;
  1316. }
  1317. }
  1318. out:
  1319. if (rc != TMF_RESP_FUNC_COMPLETE)
  1320. mv_printk("%s:rc= %d\n", __func__, rc);
  1321. return rc;
  1322. }
  1323. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1324. {
  1325. int rc = TMF_RESP_FUNC_FAILED;
  1326. struct mvs_tmf_task tmf_task;
  1327. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1328. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1329. return rc;
  1330. }
  1331. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1332. {
  1333. int rc = TMF_RESP_FUNC_FAILED;
  1334. struct mvs_tmf_task tmf_task;
  1335. tmf_task.tmf = TMF_CLEAR_ACA;
  1336. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1337. return rc;
  1338. }
  1339. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1340. {
  1341. int rc = TMF_RESP_FUNC_FAILED;
  1342. struct mvs_tmf_task tmf_task;
  1343. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1344. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1345. return rc;
  1346. }
  1347. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1348. u32 slot_idx, int err)
  1349. {
  1350. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1351. struct task_status_struct *tstat = &task->task_status;
  1352. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1353. int stat = SAM_STAT_GOOD;
  1354. resp->frame_len = sizeof(struct dev_to_host_fis);
  1355. memcpy(&resp->ending_fis[0],
  1356. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1357. sizeof(struct dev_to_host_fis));
  1358. tstat->buf_valid_size = sizeof(*resp);
  1359. if (unlikely(err)) {
  1360. if (unlikely(err & CMD_ISS_STPD))
  1361. stat = SAS_OPEN_REJECT;
  1362. else
  1363. stat = SAS_PROTO_RESPONSE;
  1364. }
  1365. return stat;
  1366. }
  1367. static void mvs_set_sense(u8 *buffer, int len, int d_sense,
  1368. int key, int asc, int ascq)
  1369. {
  1370. memset(buffer, 0, len);
  1371. if (d_sense) {
  1372. /* Descriptor format */
  1373. if (len < 4) {
  1374. mv_printk("Length %d of sense buffer too small to "
  1375. "fit sense %x:%x:%x", len, key, asc, ascq);
  1376. }
  1377. buffer[0] = 0x72; /* Response Code */
  1378. if (len > 1)
  1379. buffer[1] = key; /* Sense Key */
  1380. if (len > 2)
  1381. buffer[2] = asc; /* ASC */
  1382. if (len > 3)
  1383. buffer[3] = ascq; /* ASCQ */
  1384. } else {
  1385. if (len < 14) {
  1386. mv_printk("Length %d of sense buffer too small to "
  1387. "fit sense %x:%x:%x", len, key, asc, ascq);
  1388. }
  1389. buffer[0] = 0x70; /* Response Code */
  1390. if (len > 2)
  1391. buffer[2] = key; /* Sense Key */
  1392. if (len > 7)
  1393. buffer[7] = 0x0a; /* Additional Sense Length */
  1394. if (len > 12)
  1395. buffer[12] = asc; /* ASC */
  1396. if (len > 13)
  1397. buffer[13] = ascq; /* ASCQ */
  1398. }
  1399. return;
  1400. }
  1401. static void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
  1402. u8 key, u8 asc, u8 asc_q)
  1403. {
  1404. iu->datapres = 2;
  1405. iu->response_data_len = 0;
  1406. iu->sense_data_len = 17;
  1407. iu->status = 02;
  1408. mvs_set_sense(iu->sense_data, 17, 0,
  1409. key, asc, asc_q);
  1410. }
  1411. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1412. u32 slot_idx)
  1413. {
  1414. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1415. int stat;
  1416. u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
  1417. u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
  1418. u32 tfs = 0;
  1419. enum mvs_port_type type = PORT_TYPE_SAS;
  1420. if (err_dw0 & CMD_ISS_STPD)
  1421. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1422. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1423. stat = SAM_STAT_CHECK_CONDITION;
  1424. switch (task->task_proto) {
  1425. case SAS_PROTOCOL_SSP:
  1426. {
  1427. stat = SAS_ABORTED_TASK;
  1428. if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
  1429. struct ssp_response_iu *iu = slot->response +
  1430. sizeof(struct mvs_err_info);
  1431. mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
  1432. sas_ssp_task_response(mvi->dev, task, iu);
  1433. stat = SAM_STAT_CHECK_CONDITION;
  1434. }
  1435. if (err_dw1 & bit(31))
  1436. mv_printk("reuse same slot, retry command.\n");
  1437. break;
  1438. }
  1439. case SAS_PROTOCOL_SMP:
  1440. stat = SAM_STAT_CHECK_CONDITION;
  1441. break;
  1442. case SAS_PROTOCOL_SATA:
  1443. case SAS_PROTOCOL_STP:
  1444. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1445. {
  1446. task->ata_task.use_ncq = 0;
  1447. stat = SAS_PROTO_RESPONSE;
  1448. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1449. }
  1450. break;
  1451. default:
  1452. break;
  1453. }
  1454. return stat;
  1455. }
  1456. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1457. {
  1458. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1459. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1460. struct sas_task *task = slot->task;
  1461. struct mvs_device *mvi_dev = NULL;
  1462. struct task_status_struct *tstat;
  1463. struct domain_device *dev;
  1464. u32 aborted;
  1465. void *to;
  1466. enum exec_status sts;
  1467. if (unlikely(!task || !task->lldd_task || !task->dev))
  1468. return -1;
  1469. tstat = &task->task_status;
  1470. dev = task->dev;
  1471. mvi_dev = dev->lldd_dev;
  1472. spin_lock(&task->task_state_lock);
  1473. task->task_state_flags &=
  1474. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1475. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1476. /* race condition*/
  1477. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1478. spin_unlock(&task->task_state_lock);
  1479. memset(tstat, 0, sizeof(*tstat));
  1480. tstat->resp = SAS_TASK_COMPLETE;
  1481. if (unlikely(aborted)) {
  1482. tstat->stat = SAS_ABORTED_TASK;
  1483. if (mvi_dev && mvi_dev->running_req)
  1484. mvi_dev->running_req--;
  1485. if (sas_protocol_ata(task->task_proto))
  1486. mvs_free_reg_set(mvi, mvi_dev);
  1487. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1488. return -1;
  1489. }
  1490. /* when no device attaching, go ahead and complete by error handling*/
  1491. if (unlikely(!mvi_dev || flags)) {
  1492. if (!mvi_dev)
  1493. mv_dprintk("port has not device.\n");
  1494. tstat->stat = SAS_PHY_DOWN;
  1495. goto out;
  1496. }
  1497. /*
  1498. * error info record present; slot->response is 32 bit aligned but may
  1499. * not be 64 bit aligned, so check for zero in two 32 bit reads
  1500. */
  1501. if (unlikely((rx_desc & RXQ_ERR)
  1502. && (*((u32 *)slot->response)
  1503. || *(((u32 *)slot->response) + 1)))) {
  1504. mv_dprintk("port %d slot %d rx_desc %X has error info"
  1505. "%016llX.\n", slot->port->sas_port.id, slot_idx,
  1506. rx_desc, get_unaligned_le64(slot->response));
  1507. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1508. tstat->resp = SAS_TASK_COMPLETE;
  1509. goto out;
  1510. }
  1511. switch (task->task_proto) {
  1512. case SAS_PROTOCOL_SSP:
  1513. /* hw says status == 0, datapres == 0 */
  1514. if (rx_desc & RXQ_GOOD) {
  1515. tstat->stat = SAM_STAT_GOOD;
  1516. tstat->resp = SAS_TASK_COMPLETE;
  1517. }
  1518. /* response frame present */
  1519. else if (rx_desc & RXQ_RSP) {
  1520. struct ssp_response_iu *iu = slot->response +
  1521. sizeof(struct mvs_err_info);
  1522. sas_ssp_task_response(mvi->dev, task, iu);
  1523. } else
  1524. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1525. break;
  1526. case SAS_PROTOCOL_SMP: {
  1527. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1528. tstat->stat = SAM_STAT_GOOD;
  1529. to = kmap_atomic(sg_page(sg_resp));
  1530. memcpy(to + sg_resp->offset,
  1531. slot->response + sizeof(struct mvs_err_info),
  1532. sg_dma_len(sg_resp));
  1533. kunmap_atomic(to);
  1534. break;
  1535. }
  1536. case SAS_PROTOCOL_SATA:
  1537. case SAS_PROTOCOL_STP:
  1538. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1539. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1540. break;
  1541. }
  1542. default:
  1543. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1544. break;
  1545. }
  1546. if (!slot->port->port_attached) {
  1547. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1548. tstat->stat = SAS_PHY_DOWN;
  1549. }
  1550. out:
  1551. if (mvi_dev && mvi_dev->running_req) {
  1552. mvi_dev->running_req--;
  1553. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1554. mvs_free_reg_set(mvi, mvi_dev);
  1555. }
  1556. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1557. sts = tstat->stat;
  1558. spin_unlock(&mvi->lock);
  1559. if (task->task_done)
  1560. task->task_done(task);
  1561. spin_lock(&mvi->lock);
  1562. return sts;
  1563. }
  1564. void mvs_do_release_task(struct mvs_info *mvi,
  1565. int phy_no, struct domain_device *dev)
  1566. {
  1567. u32 slot_idx;
  1568. struct mvs_phy *phy;
  1569. struct mvs_port *port;
  1570. struct mvs_slot_info *slot, *slot2;
  1571. phy = &mvi->phy[phy_no];
  1572. port = phy->port;
  1573. if (!port)
  1574. return;
  1575. /* clean cmpl queue in case request is already finished */
  1576. mvs_int_rx(mvi, false);
  1577. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1578. struct sas_task *task;
  1579. slot_idx = (u32) (slot - mvi->slot_info);
  1580. task = slot->task;
  1581. if (dev && task->dev != dev)
  1582. continue;
  1583. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1584. slot_idx, slot->slot_tag, task);
  1585. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1586. mvs_slot_complete(mvi, slot_idx, 1);
  1587. }
  1588. }
  1589. void mvs_release_task(struct mvs_info *mvi,
  1590. struct domain_device *dev)
  1591. {
  1592. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1593. num = mvs_find_dev_phyno(dev, phyno);
  1594. for (i = 0; i < num; i++)
  1595. mvs_do_release_task(mvi, phyno[i], dev);
  1596. }
  1597. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1598. {
  1599. phy->phy_attached = 0;
  1600. phy->att_dev_info = 0;
  1601. phy->att_dev_sas_addr = 0;
  1602. }
  1603. static void mvs_work_queue(struct work_struct *work)
  1604. {
  1605. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1606. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1607. struct mvs_info *mvi = mwq->mvi;
  1608. unsigned long flags;
  1609. u32 phy_no = (unsigned long) mwq->data;
  1610. struct sas_ha_struct *sas_ha = mvi->sas;
  1611. struct mvs_phy *phy = &mvi->phy[phy_no];
  1612. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1613. spin_lock_irqsave(&mvi->lock, flags);
  1614. if (mwq->handler & PHY_PLUG_EVENT) {
  1615. if (phy->phy_event & PHY_PLUG_OUT) {
  1616. u32 tmp;
  1617. struct sas_identify_frame *id;
  1618. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1619. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1620. phy->phy_event &= ~PHY_PLUG_OUT;
  1621. if (!(tmp & PHY_READY_MASK)) {
  1622. sas_phy_disconnected(sas_phy);
  1623. mvs_phy_disconnected(phy);
  1624. sas_ha->notify_phy_event(sas_phy,
  1625. PHYE_LOSS_OF_SIGNAL);
  1626. mv_dprintk("phy%d Removed Device\n", phy_no);
  1627. } else {
  1628. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1629. mvs_update_phyinfo(mvi, phy_no, 1);
  1630. mvs_bytes_dmaed(mvi, phy_no);
  1631. mvs_port_notify_formed(sas_phy, 0);
  1632. mv_dprintk("phy%d Attached Device\n", phy_no);
  1633. }
  1634. }
  1635. } else if (mwq->handler & EXP_BRCT_CHG) {
  1636. phy->phy_event &= ~EXP_BRCT_CHG;
  1637. sas_ha->notify_port_event(sas_phy,
  1638. PORTE_BROADCAST_RCVD);
  1639. mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
  1640. }
  1641. list_del(&mwq->entry);
  1642. spin_unlock_irqrestore(&mvi->lock, flags);
  1643. kfree(mwq);
  1644. }
  1645. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1646. {
  1647. struct mvs_wq *mwq;
  1648. int ret = 0;
  1649. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1650. if (mwq) {
  1651. mwq->mvi = mvi;
  1652. mwq->data = data;
  1653. mwq->handler = handler;
  1654. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1655. list_add_tail(&mwq->entry, &mvi->wq_list);
  1656. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1657. } else
  1658. ret = -ENOMEM;
  1659. return ret;
  1660. }
  1661. static void mvs_sig_time_out(unsigned long tphy)
  1662. {
  1663. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1664. struct mvs_info *mvi = phy->mvi;
  1665. u8 phy_no;
  1666. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1667. if (&mvi->phy[phy_no] == phy) {
  1668. mv_dprintk("Get signature time out, reset phy %d\n",
  1669. phy_no+mvi->id*mvi->chip->n_phy);
  1670. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
  1671. }
  1672. }
  1673. }
  1674. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1675. {
  1676. u32 tmp;
  1677. struct mvs_phy *phy = &mvi->phy[phy_no];
  1678. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1679. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1680. mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1681. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1682. mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1683. phy->irq_status);
  1684. /*
  1685. * events is port event now ,
  1686. * we need check the interrupt status which belongs to per port.
  1687. */
  1688. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1689. mv_dprintk("phy %d STP decoding error.\n",
  1690. phy_no + mvi->id*mvi->chip->n_phy);
  1691. }
  1692. if (phy->irq_status & PHYEV_POOF) {
  1693. mdelay(500);
  1694. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1695. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1696. int ready;
  1697. mvs_do_release_task(mvi, phy_no, NULL);
  1698. phy->phy_event |= PHY_PLUG_OUT;
  1699. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1700. mvs_handle_event(mvi,
  1701. (void *)(unsigned long)phy_no,
  1702. PHY_PLUG_EVENT);
  1703. ready = mvs_is_phy_ready(mvi, phy_no);
  1704. if (ready || dev_sata) {
  1705. if (MVS_CHIP_DISP->stp_reset)
  1706. MVS_CHIP_DISP->stp_reset(mvi,
  1707. phy_no);
  1708. else
  1709. MVS_CHIP_DISP->phy_reset(mvi,
  1710. phy_no, MVS_SOFT_RESET);
  1711. return;
  1712. }
  1713. }
  1714. }
  1715. if (phy->irq_status & PHYEV_COMWAKE) {
  1716. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1717. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1718. tmp | PHYEV_SIG_FIS);
  1719. if (phy->timer.function == NULL) {
  1720. phy->timer.data = (unsigned long)phy;
  1721. phy->timer.function = mvs_sig_time_out;
  1722. phy->timer.expires = jiffies + 5*HZ;
  1723. add_timer(&phy->timer);
  1724. }
  1725. }
  1726. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1727. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1728. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1729. if (phy->phy_status) {
  1730. mdelay(10);
  1731. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1732. if (phy->phy_type & PORT_TYPE_SATA) {
  1733. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1734. mvi, phy_no);
  1735. tmp &= ~PHYEV_SIG_FIS;
  1736. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1737. phy_no, tmp);
  1738. }
  1739. mvs_update_phyinfo(mvi, phy_no, 0);
  1740. if (phy->phy_type & PORT_TYPE_SAS) {
  1741. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
  1742. mdelay(10);
  1743. }
  1744. mvs_bytes_dmaed(mvi, phy_no);
  1745. /* whether driver is going to handle hot plug */
  1746. if (phy->phy_event & PHY_PLUG_OUT) {
  1747. mvs_port_notify_formed(&phy->sas_phy, 0);
  1748. phy->phy_event &= ~PHY_PLUG_OUT;
  1749. }
  1750. } else {
  1751. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1752. phy_no + mvi->id*mvi->chip->n_phy);
  1753. }
  1754. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1755. mv_dprintk("phy %d broadcast change.\n",
  1756. phy_no + mvi->id*mvi->chip->n_phy);
  1757. mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
  1758. EXP_BRCT_CHG);
  1759. }
  1760. }
  1761. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1762. {
  1763. u32 rx_prod_idx, rx_desc;
  1764. bool attn = false;
  1765. /* the first dword in the RX ring is special: it contains
  1766. * a mirror of the hardware's RX producer index, so that
  1767. * we don't have to stall the CPU reading that register.
  1768. * The actual RX ring is offset by one dword, due to this.
  1769. */
  1770. rx_prod_idx = mvi->rx_cons;
  1771. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1772. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1773. return 0;
  1774. /* The CMPL_Q may come late, read from register and try again
  1775. * note: if coalescing is enabled,
  1776. * it will need to read from register every time for sure
  1777. */
  1778. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1779. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1780. if (mvi->rx_cons == rx_prod_idx)
  1781. return 0;
  1782. while (mvi->rx_cons != rx_prod_idx) {
  1783. /* increment our internal RX consumer pointer */
  1784. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1785. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1786. if (likely(rx_desc & RXQ_DONE))
  1787. mvs_slot_complete(mvi, rx_desc, 0);
  1788. if (rx_desc & RXQ_ATTN) {
  1789. attn = true;
  1790. } else if (rx_desc & RXQ_ERR) {
  1791. if (!(rx_desc & RXQ_DONE))
  1792. mvs_slot_complete(mvi, rx_desc, 0);
  1793. } else if (rx_desc & RXQ_SLOT_RESET) {
  1794. mvs_slot_free(mvi, rx_desc);
  1795. }
  1796. }
  1797. if (attn && self_clear)
  1798. MVS_CHIP_DISP->int_full(mvi);
  1799. return 0;
  1800. }
  1801. int mvs_gpio_write(struct sas_ha_struct *sha, u8 reg_type, u8 reg_index,
  1802. u8 reg_count, u8 *write_data)
  1803. {
  1804. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  1805. struct mvs_info *mvi = mvs_prv->mvi[0];
  1806. if (MVS_CHIP_DISP->gpio_write) {
  1807. return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type,
  1808. reg_index, reg_count, write_data);
  1809. }
  1810. return -ENOSYS;
  1811. }