rtc-twl.c 16 KB

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  1. /*
  2. * rtc-twl.c -- TWL Real Time Clock interface
  3. *
  4. * Copyright (C) 2007 MontaVista Software, Inc
  5. * Author: Alexandre Rusev <source@mvista.com>
  6. *
  7. * Based on original TI driver twl4030-rtc.c
  8. * Copyright (C) 2006 Texas Instruments, Inc.
  9. *
  10. * Based on rtc-omap.c
  11. * Copyright (C) 2003 MontaVista Software, Inc.
  12. * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
  13. * Copyright (C) 2006 David Brownell
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version
  18. * 2 of the License, or (at your option) any later version.
  19. */
  20. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21. #include <linux/kernel.h>
  22. #include <linux/errno.h>
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/types.h>
  26. #include <linux/rtc.h>
  27. #include <linux/bcd.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/of.h>
  31. #include <linux/i2c/twl.h>
  32. /*
  33. * RTC block register offsets (use TWL_MODULE_RTC)
  34. */
  35. enum {
  36. REG_SECONDS_REG = 0,
  37. REG_MINUTES_REG,
  38. REG_HOURS_REG,
  39. REG_DAYS_REG,
  40. REG_MONTHS_REG,
  41. REG_YEARS_REG,
  42. REG_WEEKS_REG,
  43. REG_ALARM_SECONDS_REG,
  44. REG_ALARM_MINUTES_REG,
  45. REG_ALARM_HOURS_REG,
  46. REG_ALARM_DAYS_REG,
  47. REG_ALARM_MONTHS_REG,
  48. REG_ALARM_YEARS_REG,
  49. REG_RTC_CTRL_REG,
  50. REG_RTC_STATUS_REG,
  51. REG_RTC_INTERRUPTS_REG,
  52. REG_RTC_COMP_LSB_REG,
  53. REG_RTC_COMP_MSB_REG,
  54. };
  55. static const u8 twl4030_rtc_reg_map[] = {
  56. [REG_SECONDS_REG] = 0x00,
  57. [REG_MINUTES_REG] = 0x01,
  58. [REG_HOURS_REG] = 0x02,
  59. [REG_DAYS_REG] = 0x03,
  60. [REG_MONTHS_REG] = 0x04,
  61. [REG_YEARS_REG] = 0x05,
  62. [REG_WEEKS_REG] = 0x06,
  63. [REG_ALARM_SECONDS_REG] = 0x07,
  64. [REG_ALARM_MINUTES_REG] = 0x08,
  65. [REG_ALARM_HOURS_REG] = 0x09,
  66. [REG_ALARM_DAYS_REG] = 0x0A,
  67. [REG_ALARM_MONTHS_REG] = 0x0B,
  68. [REG_ALARM_YEARS_REG] = 0x0C,
  69. [REG_RTC_CTRL_REG] = 0x0D,
  70. [REG_RTC_STATUS_REG] = 0x0E,
  71. [REG_RTC_INTERRUPTS_REG] = 0x0F,
  72. [REG_RTC_COMP_LSB_REG] = 0x10,
  73. [REG_RTC_COMP_MSB_REG] = 0x11,
  74. };
  75. static const u8 twl6030_rtc_reg_map[] = {
  76. [REG_SECONDS_REG] = 0x00,
  77. [REG_MINUTES_REG] = 0x01,
  78. [REG_HOURS_REG] = 0x02,
  79. [REG_DAYS_REG] = 0x03,
  80. [REG_MONTHS_REG] = 0x04,
  81. [REG_YEARS_REG] = 0x05,
  82. [REG_WEEKS_REG] = 0x06,
  83. [REG_ALARM_SECONDS_REG] = 0x08,
  84. [REG_ALARM_MINUTES_REG] = 0x09,
  85. [REG_ALARM_HOURS_REG] = 0x0A,
  86. [REG_ALARM_DAYS_REG] = 0x0B,
  87. [REG_ALARM_MONTHS_REG] = 0x0C,
  88. [REG_ALARM_YEARS_REG] = 0x0D,
  89. [REG_RTC_CTRL_REG] = 0x10,
  90. [REG_RTC_STATUS_REG] = 0x11,
  91. [REG_RTC_INTERRUPTS_REG] = 0x12,
  92. [REG_RTC_COMP_LSB_REG] = 0x13,
  93. [REG_RTC_COMP_MSB_REG] = 0x14,
  94. };
  95. /* RTC_CTRL_REG bitfields */
  96. #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
  97. #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
  98. #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
  99. #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
  100. #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
  101. #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
  102. #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
  103. #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
  104. /* RTC_STATUS_REG bitfields */
  105. #define BIT_RTC_STATUS_REG_RUN_M 0x02
  106. #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
  107. #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
  108. #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
  109. #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
  110. #define BIT_RTC_STATUS_REG_ALARM_M 0x40
  111. #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
  112. /* RTC_INTERRUPTS_REG bitfields */
  113. #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
  114. #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
  115. #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
  116. /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
  117. #define ALL_TIME_REGS 6
  118. /*----------------------------------------------------------------------*/
  119. static u8 *rtc_reg_map;
  120. /*
  121. * Supports 1 byte read from TWL RTC register.
  122. */
  123. static int twl_rtc_read_u8(u8 *data, u8 reg)
  124. {
  125. int ret;
  126. ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
  127. if (ret < 0)
  128. pr_err("Could not read TWL register %X - error %d\n", reg, ret);
  129. return ret;
  130. }
  131. /*
  132. * Supports 1 byte write to TWL RTC registers.
  133. */
  134. static int twl_rtc_write_u8(u8 data, u8 reg)
  135. {
  136. int ret;
  137. ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
  138. if (ret < 0)
  139. pr_err("Could not write TWL register %X - error %d\n",
  140. reg, ret);
  141. return ret;
  142. }
  143. /*
  144. * Cache the value for timer/alarm interrupts register; this is
  145. * only changed by callers holding rtc ops lock (or resume).
  146. */
  147. static unsigned char rtc_irq_bits;
  148. /*
  149. * Enable 1/second update and/or alarm interrupts.
  150. */
  151. static int set_rtc_irq_bit(unsigned char bit)
  152. {
  153. unsigned char val;
  154. int ret;
  155. /* if the bit is set, return from here */
  156. if (rtc_irq_bits & bit)
  157. return 0;
  158. val = rtc_irq_bits | bit;
  159. val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
  160. ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
  161. if (ret == 0)
  162. rtc_irq_bits = val;
  163. return ret;
  164. }
  165. /*
  166. * Disable update and/or alarm interrupts.
  167. */
  168. static int mask_rtc_irq_bit(unsigned char bit)
  169. {
  170. unsigned char val;
  171. int ret;
  172. /* if the bit is clear, return from here */
  173. if (!(rtc_irq_bits & bit))
  174. return 0;
  175. val = rtc_irq_bits & ~bit;
  176. ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
  177. if (ret == 0)
  178. rtc_irq_bits = val;
  179. return ret;
  180. }
  181. static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
  182. {
  183. struct platform_device *pdev = to_platform_device(dev);
  184. int irq = platform_get_irq(pdev, 0);
  185. static bool twl_rtc_wake_enabled;
  186. int ret;
  187. if (enabled) {
  188. ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  189. if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
  190. enable_irq_wake(irq);
  191. twl_rtc_wake_enabled = true;
  192. }
  193. } else {
  194. ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  195. if (twl_rtc_wake_enabled) {
  196. disable_irq_wake(irq);
  197. twl_rtc_wake_enabled = false;
  198. }
  199. }
  200. return ret;
  201. }
  202. /*
  203. * Gets current TWL RTC time and date parameters.
  204. *
  205. * The RTC's time/alarm representation is not what gmtime(3) requires
  206. * Linux to use:
  207. *
  208. * - Months are 1..12 vs Linux 0-11
  209. * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
  210. */
  211. static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
  212. {
  213. unsigned char rtc_data[ALL_TIME_REGS];
  214. int ret;
  215. u8 save_control;
  216. u8 rtc_control;
  217. ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
  218. if (ret < 0) {
  219. dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
  220. return ret;
  221. }
  222. /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
  223. if (twl_class_is_6030()) {
  224. if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
  225. save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
  226. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  227. if (ret < 0) {
  228. dev_err(dev, "%s clr GET_TIME, error %d\n",
  229. __func__, ret);
  230. return ret;
  231. }
  232. }
  233. }
  234. /* Copy RTC counting registers to static registers or latches */
  235. rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
  236. /* for twl6030/32 enable read access to static shadowed registers */
  237. if (twl_class_is_6030())
  238. rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
  239. ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
  240. if (ret < 0) {
  241. dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
  242. return ret;
  243. }
  244. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  245. (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  246. if (ret < 0) {
  247. dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
  248. return ret;
  249. }
  250. /* for twl6030 restore original state of rtc control register */
  251. if (twl_class_is_6030()) {
  252. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  253. if (ret < 0) {
  254. dev_err(dev, "%s: restore CTRL_REG, error %d\n",
  255. __func__, ret);
  256. return ret;
  257. }
  258. }
  259. tm->tm_sec = bcd2bin(rtc_data[0]);
  260. tm->tm_min = bcd2bin(rtc_data[1]);
  261. tm->tm_hour = bcd2bin(rtc_data[2]);
  262. tm->tm_mday = bcd2bin(rtc_data[3]);
  263. tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
  264. tm->tm_year = bcd2bin(rtc_data[5]) + 100;
  265. return ret;
  266. }
  267. static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
  268. {
  269. unsigned char save_control;
  270. unsigned char rtc_data[ALL_TIME_REGS];
  271. int ret;
  272. rtc_data[0] = bin2bcd(tm->tm_sec);
  273. rtc_data[1] = bin2bcd(tm->tm_min);
  274. rtc_data[2] = bin2bcd(tm->tm_hour);
  275. rtc_data[3] = bin2bcd(tm->tm_mday);
  276. rtc_data[4] = bin2bcd(tm->tm_mon + 1);
  277. rtc_data[5] = bin2bcd(tm->tm_year - 100);
  278. /* Stop RTC while updating the TC registers */
  279. ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
  280. if (ret < 0)
  281. goto out;
  282. save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
  283. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  284. if (ret < 0)
  285. goto out;
  286. /* update all the time registers in one shot */
  287. ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
  288. (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
  289. if (ret < 0) {
  290. dev_err(dev, "rtc_set_time error %d\n", ret);
  291. goto out;
  292. }
  293. /* Start back RTC */
  294. save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
  295. ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
  296. out:
  297. return ret;
  298. }
  299. /*
  300. * Gets current TWL RTC alarm time.
  301. */
  302. static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
  303. {
  304. unsigned char rtc_data[ALL_TIME_REGS];
  305. int ret;
  306. ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
  307. (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
  308. if (ret < 0) {
  309. dev_err(dev, "rtc_read_alarm error %d\n", ret);
  310. return ret;
  311. }
  312. /* some of these fields may be wildcard/"match all" */
  313. alm->time.tm_sec = bcd2bin(rtc_data[0]);
  314. alm->time.tm_min = bcd2bin(rtc_data[1]);
  315. alm->time.tm_hour = bcd2bin(rtc_data[2]);
  316. alm->time.tm_mday = bcd2bin(rtc_data[3]);
  317. alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
  318. alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
  319. /* report cached alarm enable state */
  320. if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
  321. alm->enabled = 1;
  322. return ret;
  323. }
  324. static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
  325. {
  326. unsigned char alarm_data[ALL_TIME_REGS];
  327. int ret;
  328. ret = twl_rtc_alarm_irq_enable(dev, 0);
  329. if (ret)
  330. goto out;
  331. alarm_data[0] = bin2bcd(alm->time.tm_sec);
  332. alarm_data[1] = bin2bcd(alm->time.tm_min);
  333. alarm_data[2] = bin2bcd(alm->time.tm_hour);
  334. alarm_data[3] = bin2bcd(alm->time.tm_mday);
  335. alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
  336. alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
  337. /* update all the alarm registers in one shot */
  338. ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
  339. (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
  340. if (ret) {
  341. dev_err(dev, "rtc_set_alarm error %d\n", ret);
  342. goto out;
  343. }
  344. if (alm->enabled)
  345. ret = twl_rtc_alarm_irq_enable(dev, 1);
  346. out:
  347. return ret;
  348. }
  349. static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
  350. {
  351. unsigned long events;
  352. int ret = IRQ_NONE;
  353. int res;
  354. u8 rd_reg;
  355. res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
  356. if (res)
  357. goto out;
  358. /*
  359. * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
  360. * only one (ALARM or RTC) interrupt source may be enabled
  361. * at time, we also could check our results
  362. * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
  363. */
  364. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  365. events = RTC_IRQF | RTC_AF;
  366. else
  367. events = RTC_IRQF | RTC_PF;
  368. res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
  369. REG_RTC_STATUS_REG);
  370. if (res)
  371. goto out;
  372. if (twl_class_is_4030()) {
  373. /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
  374. * needs 2 reads to clear the interrupt. One read is done in
  375. * do_twl_pwrirq(). Doing the second read, to clear
  376. * the bit.
  377. *
  378. * FIXME the reason PWR_ISR1 needs an extra read is that
  379. * RTC_IF retriggered until we cleared REG_ALARM_M above.
  380. * But re-reading like this is a bad hack; by doing so we
  381. * risk wrongly clearing status for some other IRQ (losing
  382. * the interrupt). Be smarter about handling RTC_UF ...
  383. */
  384. res = twl_i2c_read_u8(TWL4030_MODULE_INT,
  385. &rd_reg, TWL4030_INT_PWR_ISR1);
  386. if (res)
  387. goto out;
  388. }
  389. /* Notify RTC core on event */
  390. rtc_update_irq(rtc, 1, events);
  391. ret = IRQ_HANDLED;
  392. out:
  393. return ret;
  394. }
  395. static const struct rtc_class_ops twl_rtc_ops = {
  396. .read_time = twl_rtc_read_time,
  397. .set_time = twl_rtc_set_time,
  398. .read_alarm = twl_rtc_read_alarm,
  399. .set_alarm = twl_rtc_set_alarm,
  400. .alarm_irq_enable = twl_rtc_alarm_irq_enable,
  401. };
  402. /*----------------------------------------------------------------------*/
  403. static int twl_rtc_probe(struct platform_device *pdev)
  404. {
  405. struct rtc_device *rtc;
  406. int ret = -EINVAL;
  407. int irq = platform_get_irq(pdev, 0);
  408. u8 rd_reg;
  409. if (irq <= 0)
  410. return ret;
  411. /* Initialize the register map */
  412. if (twl_class_is_4030())
  413. rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
  414. else
  415. rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
  416. ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
  417. if (ret < 0)
  418. return ret;
  419. if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
  420. dev_warn(&pdev->dev, "Power up reset detected.\n");
  421. if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
  422. dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
  423. /* Clear RTC Power up reset and pending alarm interrupts */
  424. ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
  425. if (ret < 0)
  426. return ret;
  427. if (twl_class_is_6030()) {
  428. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  429. REG_INT_MSK_LINE_A);
  430. twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
  431. REG_INT_MSK_STS_A);
  432. }
  433. dev_info(&pdev->dev, "Enabling TWL-RTC\n");
  434. ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
  435. if (ret < 0)
  436. return ret;
  437. /* ensure interrupts are disabled, bootloaders can be strange */
  438. ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
  439. if (ret < 0)
  440. dev_warn(&pdev->dev, "unable to disable interrupt\n");
  441. /* init cached IRQ enable bits */
  442. ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
  443. if (ret < 0)
  444. return ret;
  445. device_init_wakeup(&pdev->dev, 1);
  446. rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
  447. &twl_rtc_ops, THIS_MODULE);
  448. if (IS_ERR(rtc)) {
  449. dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
  450. PTR_ERR(rtc));
  451. return PTR_ERR(rtc);
  452. }
  453. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  454. twl_rtc_interrupt,
  455. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  456. dev_name(&rtc->dev), rtc);
  457. if (ret < 0) {
  458. dev_err(&pdev->dev, "IRQ is not free.\n");
  459. return ret;
  460. }
  461. platform_set_drvdata(pdev, rtc);
  462. return 0;
  463. }
  464. /*
  465. * Disable all TWL RTC module interrupts.
  466. * Sets status flag to free.
  467. */
  468. static int twl_rtc_remove(struct platform_device *pdev)
  469. {
  470. /* leave rtc running, but disable irqs */
  471. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
  472. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  473. if (twl_class_is_6030()) {
  474. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  475. REG_INT_MSK_LINE_A);
  476. twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
  477. REG_INT_MSK_STS_A);
  478. }
  479. return 0;
  480. }
  481. static void twl_rtc_shutdown(struct platform_device *pdev)
  482. {
  483. /* mask timer interrupts, but leave alarm interrupts on to enable
  484. power-on when alarm is triggered */
  485. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  486. }
  487. #ifdef CONFIG_PM_SLEEP
  488. static unsigned char irqstat;
  489. static int twl_rtc_suspend(struct device *dev)
  490. {
  491. irqstat = rtc_irq_bits;
  492. mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
  493. return 0;
  494. }
  495. static int twl_rtc_resume(struct device *dev)
  496. {
  497. set_rtc_irq_bit(irqstat);
  498. return 0;
  499. }
  500. #endif
  501. static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
  502. #ifdef CONFIG_OF
  503. static const struct of_device_id twl_rtc_of_match[] = {
  504. {.compatible = "ti,twl4030-rtc", },
  505. { },
  506. };
  507. MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
  508. #endif
  509. MODULE_ALIAS("platform:twl_rtc");
  510. static struct platform_driver twl4030rtc_driver = {
  511. .probe = twl_rtc_probe,
  512. .remove = twl_rtc_remove,
  513. .shutdown = twl_rtc_shutdown,
  514. .driver = {
  515. .name = "twl_rtc",
  516. .pm = &twl_rtc_pm_ops,
  517. .of_match_table = of_match_ptr(twl_rtc_of_match),
  518. },
  519. };
  520. module_platform_driver(twl4030rtc_driver);
  521. MODULE_AUTHOR("Texas Instruments, MontaVista Software");
  522. MODULE_LICENSE("GPL");