rtc-sh.c 18 KB

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  1. /*
  2. * SuperH On-Chip RTC Support
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. * Copyright (C) 2008 Angelo Castello
  7. *
  8. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  9. *
  10. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  11. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc.h>
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/io.h>
  27. #include <linux/log2.h>
  28. #include <linux/clk.h>
  29. #include <linux/slab.h>
  30. #include <asm/rtc.h>
  31. #define DRV_NAME "sh-rtc"
  32. #define RTC_REG(r) ((r) * rtc_reg_size)
  33. #define R64CNT RTC_REG(0)
  34. #define RSECCNT RTC_REG(1) /* RTC sec */
  35. #define RMINCNT RTC_REG(2) /* RTC min */
  36. #define RHRCNT RTC_REG(3) /* RTC hour */
  37. #define RWKCNT RTC_REG(4) /* RTC week */
  38. #define RDAYCNT RTC_REG(5) /* RTC day */
  39. #define RMONCNT RTC_REG(6) /* RTC month */
  40. #define RYRCNT RTC_REG(7) /* RTC year */
  41. #define RSECAR RTC_REG(8) /* ALARM sec */
  42. #define RMINAR RTC_REG(9) /* ALARM min */
  43. #define RHRAR RTC_REG(10) /* ALARM hour */
  44. #define RWKAR RTC_REG(11) /* ALARM week */
  45. #define RDAYAR RTC_REG(12) /* ALARM day */
  46. #define RMONAR RTC_REG(13) /* ALARM month */
  47. #define RCR1 RTC_REG(14) /* Control */
  48. #define RCR2 RTC_REG(15) /* Control */
  49. /*
  50. * Note on RYRAR and RCR3: Up until this point most of the register
  51. * definitions are consistent across all of the available parts. However,
  52. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  53. * register used to control RYRCNT/RYRAR compare) varies considerably
  54. * across various parts, occasionally being mapped in to a completely
  55. * unrelated address space. For proper RYRAR support a separate resource
  56. * would have to be handed off, but as this is purely optional in
  57. * practice, we simply opt not to support it, thereby keeping the code
  58. * quite a bit more simplified.
  59. */
  60. /* ALARM Bits - or with BCD encoded value */
  61. #define AR_ENB 0x80 /* Enable for alarm cmp */
  62. /* Period Bits */
  63. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  64. #define PF_COUNT 0x200 /* Half periodic counter */
  65. #define PF_OXS 0x400 /* Periodic One x Second */
  66. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  67. #define PF_MASK 0xf00
  68. /* RCR1 Bits */
  69. #define RCR1_CF 0x80 /* Carry Flag */
  70. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  71. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  72. #define RCR1_AF 0x01 /* Alarm Flag */
  73. /* RCR2 Bits */
  74. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  75. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  76. #define RCR2_RTCEN 0x08 /* ENable RTC */
  77. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  78. #define RCR2_RESET 0x02 /* Reset bit */
  79. #define RCR2_START 0x01 /* Start bit */
  80. struct sh_rtc {
  81. void __iomem *regbase;
  82. unsigned long regsize;
  83. struct resource *res;
  84. int alarm_irq;
  85. int periodic_irq;
  86. int carry_irq;
  87. struct clk *clk;
  88. struct rtc_device *rtc_dev;
  89. spinlock_t lock;
  90. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  91. unsigned short periodic_freq;
  92. };
  93. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  94. {
  95. unsigned int tmp, pending;
  96. tmp = readb(rtc->regbase + RCR1);
  97. pending = tmp & RCR1_CF;
  98. tmp &= ~RCR1_CF;
  99. writeb(tmp, rtc->regbase + RCR1);
  100. /* Users have requested One x Second IRQ */
  101. if (pending && rtc->periodic_freq & PF_OXS)
  102. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  103. return pending;
  104. }
  105. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  106. {
  107. unsigned int tmp, pending;
  108. tmp = readb(rtc->regbase + RCR1);
  109. pending = tmp & RCR1_AF;
  110. tmp &= ~(RCR1_AF | RCR1_AIE);
  111. writeb(tmp, rtc->regbase + RCR1);
  112. if (pending)
  113. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  114. return pending;
  115. }
  116. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  117. {
  118. struct rtc_device *rtc_dev = rtc->rtc_dev;
  119. struct rtc_task *irq_task;
  120. unsigned int tmp, pending;
  121. tmp = readb(rtc->regbase + RCR2);
  122. pending = tmp & RCR2_PEF;
  123. tmp &= ~RCR2_PEF;
  124. writeb(tmp, rtc->regbase + RCR2);
  125. if (!pending)
  126. return 0;
  127. /* Half period enabled than one skipped and the next notified */
  128. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  129. rtc->periodic_freq &= ~PF_COUNT;
  130. else {
  131. if (rtc->periodic_freq & PF_HP)
  132. rtc->periodic_freq |= PF_COUNT;
  133. if (rtc->periodic_freq & PF_KOU) {
  134. spin_lock(&rtc_dev->irq_task_lock);
  135. irq_task = rtc_dev->irq_task;
  136. if (irq_task)
  137. irq_task->func(irq_task->private_data);
  138. spin_unlock(&rtc_dev->irq_task_lock);
  139. } else
  140. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  141. }
  142. return pending;
  143. }
  144. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  145. {
  146. struct sh_rtc *rtc = dev_id;
  147. int ret;
  148. spin_lock(&rtc->lock);
  149. ret = __sh_rtc_interrupt(rtc);
  150. spin_unlock(&rtc->lock);
  151. return IRQ_RETVAL(ret);
  152. }
  153. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  154. {
  155. struct sh_rtc *rtc = dev_id;
  156. int ret;
  157. spin_lock(&rtc->lock);
  158. ret = __sh_rtc_alarm(rtc);
  159. spin_unlock(&rtc->lock);
  160. return IRQ_RETVAL(ret);
  161. }
  162. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  163. {
  164. struct sh_rtc *rtc = dev_id;
  165. int ret;
  166. spin_lock(&rtc->lock);
  167. ret = __sh_rtc_periodic(rtc);
  168. spin_unlock(&rtc->lock);
  169. return IRQ_RETVAL(ret);
  170. }
  171. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  172. {
  173. struct sh_rtc *rtc = dev_id;
  174. int ret;
  175. spin_lock(&rtc->lock);
  176. ret = __sh_rtc_interrupt(rtc);
  177. ret |= __sh_rtc_alarm(rtc);
  178. ret |= __sh_rtc_periodic(rtc);
  179. spin_unlock(&rtc->lock);
  180. return IRQ_RETVAL(ret);
  181. }
  182. static int sh_rtc_irq_set_state(struct device *dev, int enable)
  183. {
  184. struct sh_rtc *rtc = dev_get_drvdata(dev);
  185. unsigned int tmp;
  186. spin_lock_irq(&rtc->lock);
  187. tmp = readb(rtc->regbase + RCR2);
  188. if (enable) {
  189. rtc->periodic_freq |= PF_KOU;
  190. tmp &= ~RCR2_PEF; /* Clear PES bit */
  191. tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
  192. } else {
  193. rtc->periodic_freq &= ~PF_KOU;
  194. tmp &= ~(RCR2_PESMASK | RCR2_PEF);
  195. }
  196. writeb(tmp, rtc->regbase + RCR2);
  197. spin_unlock_irq(&rtc->lock);
  198. return 0;
  199. }
  200. static int sh_rtc_irq_set_freq(struct device *dev, int freq)
  201. {
  202. struct sh_rtc *rtc = dev_get_drvdata(dev);
  203. int tmp, ret = 0;
  204. spin_lock_irq(&rtc->lock);
  205. tmp = rtc->periodic_freq & PF_MASK;
  206. switch (freq) {
  207. case 0:
  208. rtc->periodic_freq = 0x00;
  209. break;
  210. case 1:
  211. rtc->periodic_freq = 0x60;
  212. break;
  213. case 2:
  214. rtc->periodic_freq = 0x50;
  215. break;
  216. case 4:
  217. rtc->periodic_freq = 0x40;
  218. break;
  219. case 8:
  220. rtc->periodic_freq = 0x30 | PF_HP;
  221. break;
  222. case 16:
  223. rtc->periodic_freq = 0x30;
  224. break;
  225. case 32:
  226. rtc->periodic_freq = 0x20 | PF_HP;
  227. break;
  228. case 64:
  229. rtc->periodic_freq = 0x20;
  230. break;
  231. case 128:
  232. rtc->periodic_freq = 0x10 | PF_HP;
  233. break;
  234. case 256:
  235. rtc->periodic_freq = 0x10;
  236. break;
  237. default:
  238. ret = -ENOTSUPP;
  239. }
  240. if (ret == 0)
  241. rtc->periodic_freq |= tmp;
  242. spin_unlock_irq(&rtc->lock);
  243. return ret;
  244. }
  245. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  246. {
  247. struct sh_rtc *rtc = dev_get_drvdata(dev);
  248. unsigned int tmp;
  249. spin_lock_irq(&rtc->lock);
  250. tmp = readb(rtc->regbase + RCR1);
  251. if (enable)
  252. tmp |= RCR1_AIE;
  253. else
  254. tmp &= ~RCR1_AIE;
  255. writeb(tmp, rtc->regbase + RCR1);
  256. spin_unlock_irq(&rtc->lock);
  257. }
  258. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  259. {
  260. struct sh_rtc *rtc = dev_get_drvdata(dev);
  261. unsigned int tmp;
  262. tmp = readb(rtc->regbase + RCR1);
  263. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  264. tmp = readb(rtc->regbase + RCR2);
  265. seq_printf(seq, "periodic_IRQ\t: %s\n",
  266. (tmp & RCR2_PESMASK) ? "yes" : "no");
  267. return 0;
  268. }
  269. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  270. {
  271. struct sh_rtc *rtc = dev_get_drvdata(dev);
  272. unsigned int tmp;
  273. spin_lock_irq(&rtc->lock);
  274. tmp = readb(rtc->regbase + RCR1);
  275. if (!enable)
  276. tmp &= ~RCR1_CIE;
  277. else
  278. tmp |= RCR1_CIE;
  279. writeb(tmp, rtc->regbase + RCR1);
  280. spin_unlock_irq(&rtc->lock);
  281. }
  282. static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  283. {
  284. sh_rtc_setaie(dev, enabled);
  285. return 0;
  286. }
  287. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  288. {
  289. struct platform_device *pdev = to_platform_device(dev);
  290. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  291. unsigned int sec128, sec2, yr, yr100, cf_bit;
  292. do {
  293. unsigned int tmp;
  294. spin_lock_irq(&rtc->lock);
  295. tmp = readb(rtc->regbase + RCR1);
  296. tmp &= ~RCR1_CF; /* Clear CF-bit */
  297. tmp |= RCR1_CIE;
  298. writeb(tmp, rtc->regbase + RCR1);
  299. sec128 = readb(rtc->regbase + R64CNT);
  300. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  301. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  302. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  303. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  304. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  305. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  306. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  307. yr = readw(rtc->regbase + RYRCNT);
  308. yr100 = bcd2bin(yr >> 8);
  309. yr &= 0xff;
  310. } else {
  311. yr = readb(rtc->regbase + RYRCNT);
  312. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  313. }
  314. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  315. sec2 = readb(rtc->regbase + R64CNT);
  316. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  317. spin_unlock_irq(&rtc->lock);
  318. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  319. #if RTC_BIT_INVERTED != 0
  320. if ((sec128 & RTC_BIT_INVERTED))
  321. tm->tm_sec--;
  322. #endif
  323. /* only keep the carry interrupt enabled if UIE is on */
  324. if (!(rtc->periodic_freq & PF_OXS))
  325. sh_rtc_setcie(dev, 0);
  326. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  327. "mday=%d, mon=%d, year=%d, wday=%d\n",
  328. __func__,
  329. tm->tm_sec, tm->tm_min, tm->tm_hour,
  330. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  331. return rtc_valid_tm(tm);
  332. }
  333. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  334. {
  335. struct platform_device *pdev = to_platform_device(dev);
  336. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  337. unsigned int tmp;
  338. int year;
  339. spin_lock_irq(&rtc->lock);
  340. /* Reset pre-scaler & stop RTC */
  341. tmp = readb(rtc->regbase + RCR2);
  342. tmp |= RCR2_RESET;
  343. tmp &= ~RCR2_START;
  344. writeb(tmp, rtc->regbase + RCR2);
  345. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  346. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  347. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  348. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  349. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  350. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  351. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  352. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  353. bin2bcd(tm->tm_year % 100);
  354. writew(year, rtc->regbase + RYRCNT);
  355. } else {
  356. year = tm->tm_year % 100;
  357. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  358. }
  359. /* Start RTC */
  360. tmp = readb(rtc->regbase + RCR2);
  361. tmp &= ~RCR2_RESET;
  362. tmp |= RCR2_RTCEN | RCR2_START;
  363. writeb(tmp, rtc->regbase + RCR2);
  364. spin_unlock_irq(&rtc->lock);
  365. return 0;
  366. }
  367. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  368. {
  369. unsigned int byte;
  370. int value = 0xff; /* return 0xff for ignored values */
  371. byte = readb(rtc->regbase + reg_off);
  372. if (byte & AR_ENB) {
  373. byte &= ~AR_ENB; /* strip the enable bit */
  374. value = bcd2bin(byte);
  375. }
  376. return value;
  377. }
  378. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  379. {
  380. struct platform_device *pdev = to_platform_device(dev);
  381. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  382. struct rtc_time *tm = &wkalrm->time;
  383. spin_lock_irq(&rtc->lock);
  384. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  385. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  386. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  387. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  388. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  389. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  390. if (tm->tm_mon > 0)
  391. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  392. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  393. spin_unlock_irq(&rtc->lock);
  394. return 0;
  395. }
  396. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  397. int value, int reg_off)
  398. {
  399. /* < 0 for a value that is ignored */
  400. if (value < 0)
  401. writeb(0, rtc->regbase + reg_off);
  402. else
  403. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  404. }
  405. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  406. {
  407. struct platform_device *pdev = to_platform_device(dev);
  408. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  409. unsigned int rcr1;
  410. struct rtc_time *tm = &wkalrm->time;
  411. int mon;
  412. spin_lock_irq(&rtc->lock);
  413. /* disable alarm interrupt and clear the alarm flag */
  414. rcr1 = readb(rtc->regbase + RCR1);
  415. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  416. writeb(rcr1, rtc->regbase + RCR1);
  417. /* set alarm time */
  418. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  419. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  420. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  421. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  422. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  423. mon = tm->tm_mon;
  424. if (mon >= 0)
  425. mon += 1;
  426. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  427. if (wkalrm->enabled) {
  428. rcr1 |= RCR1_AIE;
  429. writeb(rcr1, rtc->regbase + RCR1);
  430. }
  431. spin_unlock_irq(&rtc->lock);
  432. return 0;
  433. }
  434. static struct rtc_class_ops sh_rtc_ops = {
  435. .read_time = sh_rtc_read_time,
  436. .set_time = sh_rtc_set_time,
  437. .read_alarm = sh_rtc_read_alarm,
  438. .set_alarm = sh_rtc_set_alarm,
  439. .proc = sh_rtc_proc,
  440. .alarm_irq_enable = sh_rtc_alarm_irq_enable,
  441. };
  442. static int __init sh_rtc_probe(struct platform_device *pdev)
  443. {
  444. struct sh_rtc *rtc;
  445. struct resource *res;
  446. struct rtc_time r;
  447. char clk_name[6];
  448. int clk_id, ret;
  449. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  450. if (unlikely(!rtc))
  451. return -ENOMEM;
  452. spin_lock_init(&rtc->lock);
  453. /* get periodic/carry/alarm irqs */
  454. ret = platform_get_irq(pdev, 0);
  455. if (unlikely(ret <= 0)) {
  456. dev_err(&pdev->dev, "No IRQ resource\n");
  457. return -ENOENT;
  458. }
  459. rtc->periodic_irq = ret;
  460. rtc->carry_irq = platform_get_irq(pdev, 1);
  461. rtc->alarm_irq = platform_get_irq(pdev, 2);
  462. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  463. if (unlikely(res == NULL)) {
  464. dev_err(&pdev->dev, "No IO resource\n");
  465. return -ENOENT;
  466. }
  467. rtc->regsize = resource_size(res);
  468. rtc->res = devm_request_mem_region(&pdev->dev, res->start,
  469. rtc->regsize, pdev->name);
  470. if (unlikely(!rtc->res))
  471. return -EBUSY;
  472. rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
  473. rtc->regsize);
  474. if (unlikely(!rtc->regbase))
  475. return -EINVAL;
  476. clk_id = pdev->id;
  477. /* With a single device, the clock id is still "rtc0" */
  478. if (clk_id < 0)
  479. clk_id = 0;
  480. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  481. rtc->clk = devm_clk_get(&pdev->dev, clk_name);
  482. if (IS_ERR(rtc->clk)) {
  483. /*
  484. * No error handling for rtc->clk intentionally, not all
  485. * platforms will have a unique clock for the RTC, and
  486. * the clk API can handle the struct clk pointer being
  487. * NULL.
  488. */
  489. rtc->clk = NULL;
  490. }
  491. clk_enable(rtc->clk);
  492. rtc->capabilities = RTC_DEF_CAPABILITIES;
  493. if (dev_get_platdata(&pdev->dev)) {
  494. struct sh_rtc_platform_info *pinfo =
  495. dev_get_platdata(&pdev->dev);
  496. /*
  497. * Some CPUs have special capabilities in addition to the
  498. * default set. Add those in here.
  499. */
  500. rtc->capabilities |= pinfo->capabilities;
  501. }
  502. if (rtc->carry_irq <= 0) {
  503. /* register shared periodic/carry/alarm irq */
  504. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  505. sh_rtc_shared, 0, "sh-rtc", rtc);
  506. if (unlikely(ret)) {
  507. dev_err(&pdev->dev,
  508. "request IRQ failed with %d, IRQ %d\n", ret,
  509. rtc->periodic_irq);
  510. goto err_unmap;
  511. }
  512. } else {
  513. /* register periodic/carry/alarm irqs */
  514. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  515. sh_rtc_periodic, 0, "sh-rtc period", rtc);
  516. if (unlikely(ret)) {
  517. dev_err(&pdev->dev,
  518. "request period IRQ failed with %d, IRQ %d\n",
  519. ret, rtc->periodic_irq);
  520. goto err_unmap;
  521. }
  522. ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
  523. sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
  524. if (unlikely(ret)) {
  525. dev_err(&pdev->dev,
  526. "request carry IRQ failed with %d, IRQ %d\n",
  527. ret, rtc->carry_irq);
  528. goto err_unmap;
  529. }
  530. ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
  531. sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
  532. if (unlikely(ret)) {
  533. dev_err(&pdev->dev,
  534. "request alarm IRQ failed with %d, IRQ %d\n",
  535. ret, rtc->alarm_irq);
  536. goto err_unmap;
  537. }
  538. }
  539. platform_set_drvdata(pdev, rtc);
  540. /* everything disabled by default */
  541. sh_rtc_irq_set_freq(&pdev->dev, 0);
  542. sh_rtc_irq_set_state(&pdev->dev, 0);
  543. sh_rtc_setaie(&pdev->dev, 0);
  544. sh_rtc_setcie(&pdev->dev, 0);
  545. rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
  546. &sh_rtc_ops, THIS_MODULE);
  547. if (IS_ERR(rtc->rtc_dev)) {
  548. ret = PTR_ERR(rtc->rtc_dev);
  549. goto err_unmap;
  550. }
  551. rtc->rtc_dev->max_user_freq = 256;
  552. /* reset rtc to epoch 0 if time is invalid */
  553. if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
  554. rtc_time_to_tm(0, &r);
  555. rtc_set_time(rtc->rtc_dev, &r);
  556. }
  557. device_init_wakeup(&pdev->dev, 1);
  558. return 0;
  559. err_unmap:
  560. clk_disable(rtc->clk);
  561. return ret;
  562. }
  563. static int __exit sh_rtc_remove(struct platform_device *pdev)
  564. {
  565. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  566. sh_rtc_irq_set_state(&pdev->dev, 0);
  567. sh_rtc_setaie(&pdev->dev, 0);
  568. sh_rtc_setcie(&pdev->dev, 0);
  569. clk_disable(rtc->clk);
  570. return 0;
  571. }
  572. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  573. {
  574. struct platform_device *pdev = to_platform_device(dev);
  575. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  576. irq_set_irq_wake(rtc->periodic_irq, enabled);
  577. if (rtc->carry_irq > 0) {
  578. irq_set_irq_wake(rtc->carry_irq, enabled);
  579. irq_set_irq_wake(rtc->alarm_irq, enabled);
  580. }
  581. }
  582. #ifdef CONFIG_PM_SLEEP
  583. static int sh_rtc_suspend(struct device *dev)
  584. {
  585. if (device_may_wakeup(dev))
  586. sh_rtc_set_irq_wake(dev, 1);
  587. return 0;
  588. }
  589. static int sh_rtc_resume(struct device *dev)
  590. {
  591. if (device_may_wakeup(dev))
  592. sh_rtc_set_irq_wake(dev, 0);
  593. return 0;
  594. }
  595. #endif
  596. static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
  597. static struct platform_driver sh_rtc_platform_driver = {
  598. .driver = {
  599. .name = DRV_NAME,
  600. .pm = &sh_rtc_pm_ops,
  601. },
  602. .remove = __exit_p(sh_rtc_remove),
  603. };
  604. module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
  605. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  606. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
  607. "Jamie Lenehan <lenehan@twibble.org>, "
  608. "Angelo Castello <angelo.castello@st.com>");
  609. MODULE_LICENSE("GPL");
  610. MODULE_ALIAS("platform:" DRV_NAME);