rtc-s3c.h 2.2 KB

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  1. /*
  2. * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
  3. * http://www.simtec.co.uk/products/SWLINUX/
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * S3C2410 Internal RTC register definition
  10. */
  11. #ifndef __ASM_ARCH_REGS_RTC_H
  12. #define __ASM_ARCH_REGS_RTC_H __FILE__
  13. #define S3C2410_RTCREG(x) (x)
  14. #define S3C2410_INTP S3C2410_RTCREG(0x30)
  15. #define S3C2410_INTP_ALM (1 << 1)
  16. #define S3C2410_INTP_TIC (1 << 0)
  17. #define S3C2410_RTCCON S3C2410_RTCREG(0x40)
  18. #define S3C2410_RTCCON_RTCEN (1 << 0)
  19. #define S3C2410_RTCCON_CNTSEL (1 << 2)
  20. #define S3C2410_RTCCON_CLKRST (1 << 3)
  21. #define S3C2443_RTCCON_TICSEL (1 << 4)
  22. #define S3C64XX_RTCCON_TICEN (1 << 8)
  23. #define S3C2410_TICNT S3C2410_RTCREG(0x44)
  24. #define S3C2410_TICNT_ENABLE (1 << 7)
  25. /* S3C2443: tick count is 15 bit wide
  26. * TICNT[6:0] contains upper 7 bits
  27. * TICNT1[7:0] contains lower 8 bits
  28. */
  29. #define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8)
  30. #define S3C2443_TICNT1 S3C2410_RTCREG(0x4C)
  31. #define S3C2443_TICNT1_PART(x) (x & 0xff)
  32. /* S3C2416: tick count is 32 bit wide
  33. * TICNT[6:0] contains bits [14:8]
  34. * TICNT1[7:0] contains lower 8 bits
  35. * TICNT2[16:0] contains upper 17 bits
  36. */
  37. #define S3C2416_TICNT2 S3C2410_RTCREG(0x48)
  38. #define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15)
  39. #define S3C2410_RTCALM S3C2410_RTCREG(0x50)
  40. #define S3C2410_RTCALM_ALMEN (1 << 6)
  41. #define S3C2410_RTCALM_YEAREN (1 << 5)
  42. #define S3C2410_RTCALM_MONEN (1 << 4)
  43. #define S3C2410_RTCALM_DAYEN (1 << 3)
  44. #define S3C2410_RTCALM_HOUREN (1 << 2)
  45. #define S3C2410_RTCALM_MINEN (1 << 1)
  46. #define S3C2410_RTCALM_SECEN (1 << 0)
  47. #define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
  48. #define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
  49. #define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
  50. #define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
  51. #define S3C2410_ALMMON S3C2410_RTCREG(0x64)
  52. #define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
  53. #define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
  54. #define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
  55. #define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
  56. #define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
  57. #define S3C2410_RTCMON S3C2410_RTCREG(0x84)
  58. #define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
  59. #endif /* __ASM_ARCH_REGS_RTC_H */