rtc-max77686.c 22 KB

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  1. /*
  2. * RTC driver for Maxim MAX77686 and MAX77802
  3. *
  4. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  5. *
  6. * based on rtc-max8997.c
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/i2c.h>
  15. #include <linux/slab.h>
  16. #include <linux/rtc.h>
  17. #include <linux/delay.h>
  18. #include <linux/mutex.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/mfd/max77686-private.h>
  22. #include <linux/irqdomain.h>
  23. #include <linux/regmap.h>
  24. #define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
  25. #define MAX77620_I2C_ADDR_RTC 0x68
  26. #define MAX77686_INVALID_I2C_ADDR (-1)
  27. /* Define non existing register */
  28. #define MAX77686_INVALID_REG (-1)
  29. /* RTC Control Register */
  30. #define BCD_EN_SHIFT 0
  31. #define BCD_EN_MASK BIT(BCD_EN_SHIFT)
  32. #define MODEL24_SHIFT 1
  33. #define MODEL24_MASK BIT(MODEL24_SHIFT)
  34. /* RTC Update Register1 */
  35. #define RTC_UDR_SHIFT 0
  36. #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
  37. #define RTC_RBUDR_SHIFT 4
  38. #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
  39. /* RTC Hour register */
  40. #define HOUR_PM_SHIFT 6
  41. #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT)
  42. /* RTC Alarm Enable */
  43. #define ALARM_ENABLE_SHIFT 7
  44. #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
  45. #define REG_RTC_NONE 0xdeadbeef
  46. /*
  47. * MAX77802 has separate register (RTCAE1) for alarm enable instead
  48. * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
  49. * as in done in MAX77686.
  50. */
  51. #define MAX77802_ALARM_ENABLE_VALUE 0x77
  52. enum {
  53. RTC_SEC = 0,
  54. RTC_MIN,
  55. RTC_HOUR,
  56. RTC_WEEKDAY,
  57. RTC_MONTH,
  58. RTC_YEAR,
  59. RTC_DATE,
  60. RTC_NR_TIME
  61. };
  62. struct max77686_rtc_driver_data {
  63. /* Minimum usecs needed for a RTC update */
  64. unsigned long delay;
  65. /* Mask used to read RTC registers value */
  66. u8 mask;
  67. /* Registers offset to I2C addresses map */
  68. const unsigned int *map;
  69. /* Has a separate alarm enable register? */
  70. bool alarm_enable_reg;
  71. /* I2C address for RTC block */
  72. int rtc_i2c_addr;
  73. /* RTC interrupt via platform resource */
  74. bool rtc_irq_from_platform;
  75. /* Pending alarm status register */
  76. int alarm_pending_status_reg;
  77. /* RTC IRQ CHIP for regmap */
  78. const struct regmap_irq_chip *rtc_irq_chip;
  79. };
  80. struct max77686_rtc_info {
  81. struct device *dev;
  82. struct i2c_client *rtc;
  83. struct rtc_device *rtc_dev;
  84. struct mutex lock;
  85. struct regmap *regmap;
  86. struct regmap *rtc_regmap;
  87. const struct max77686_rtc_driver_data *drv_data;
  88. struct regmap_irq_chip_data *rtc_irq_data;
  89. int rtc_irq;
  90. int virq;
  91. int rtc_24hr_mode;
  92. };
  93. enum MAX77686_RTC_OP {
  94. MAX77686_RTC_WRITE,
  95. MAX77686_RTC_READ,
  96. };
  97. /* These are not registers but just offsets that are mapped to addresses */
  98. enum max77686_rtc_reg_offset {
  99. REG_RTC_CONTROLM = 0,
  100. REG_RTC_CONTROL,
  101. REG_RTC_UPDATE0,
  102. REG_WTSR_SMPL_CNTL,
  103. REG_RTC_SEC,
  104. REG_RTC_MIN,
  105. REG_RTC_HOUR,
  106. REG_RTC_WEEKDAY,
  107. REG_RTC_MONTH,
  108. REG_RTC_YEAR,
  109. REG_RTC_DATE,
  110. REG_ALARM1_SEC,
  111. REG_ALARM1_MIN,
  112. REG_ALARM1_HOUR,
  113. REG_ALARM1_WEEKDAY,
  114. REG_ALARM1_MONTH,
  115. REG_ALARM1_YEAR,
  116. REG_ALARM1_DATE,
  117. REG_ALARM2_SEC,
  118. REG_ALARM2_MIN,
  119. REG_ALARM2_HOUR,
  120. REG_ALARM2_WEEKDAY,
  121. REG_ALARM2_MONTH,
  122. REG_ALARM2_YEAR,
  123. REG_ALARM2_DATE,
  124. REG_RTC_AE1,
  125. REG_RTC_END,
  126. };
  127. /* Maps RTC registers offset to the MAX77686 register addresses */
  128. static const unsigned int max77686_map[REG_RTC_END] = {
  129. [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
  130. [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
  131. [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
  132. [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
  133. [REG_RTC_SEC] = MAX77686_RTC_SEC,
  134. [REG_RTC_MIN] = MAX77686_RTC_MIN,
  135. [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
  136. [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
  137. [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
  138. [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
  139. [REG_RTC_DATE] = MAX77686_RTC_DATE,
  140. [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
  141. [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
  142. [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
  143. [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
  144. [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
  145. [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
  146. [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
  147. [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
  148. [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
  149. [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
  150. [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
  151. [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
  152. [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
  153. [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
  154. [REG_RTC_AE1] = REG_RTC_NONE,
  155. };
  156. static const struct regmap_irq max77686_rtc_irqs[] = {
  157. /* RTC interrupts */
  158. REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
  159. REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
  160. REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
  161. REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
  162. REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
  163. REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
  164. };
  165. static const struct regmap_irq_chip max77686_rtc_irq_chip = {
  166. .name = "max77686-rtc",
  167. .status_base = MAX77686_RTC_INT,
  168. .mask_base = MAX77686_RTC_INTM,
  169. .num_regs = 1,
  170. .irqs = max77686_rtc_irqs,
  171. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  172. };
  173. static const struct max77686_rtc_driver_data max77686_drv_data = {
  174. .delay = 16000,
  175. .mask = 0x7f,
  176. .map = max77686_map,
  177. .alarm_enable_reg = false,
  178. .rtc_irq_from_platform = false,
  179. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  180. .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
  181. .rtc_irq_chip = &max77686_rtc_irq_chip,
  182. };
  183. static const struct max77686_rtc_driver_data max77620_drv_data = {
  184. .delay = 16000,
  185. .mask = 0x7f,
  186. .map = max77686_map,
  187. .alarm_enable_reg = false,
  188. .rtc_irq_from_platform = true,
  189. .alarm_pending_status_reg = MAX77686_INVALID_REG,
  190. .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
  191. .rtc_irq_chip = &max77686_rtc_irq_chip,
  192. };
  193. static const unsigned int max77802_map[REG_RTC_END] = {
  194. [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
  195. [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
  196. [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
  197. [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
  198. [REG_RTC_SEC] = MAX77802_RTC_SEC,
  199. [REG_RTC_MIN] = MAX77802_RTC_MIN,
  200. [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
  201. [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
  202. [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
  203. [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
  204. [REG_RTC_DATE] = MAX77802_RTC_DATE,
  205. [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
  206. [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
  207. [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
  208. [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
  209. [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
  210. [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
  211. [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
  212. [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
  213. [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
  214. [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
  215. [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
  216. [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
  217. [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
  218. [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
  219. [REG_RTC_AE1] = MAX77802_RTC_AE1,
  220. };
  221. static const struct regmap_irq_chip max77802_rtc_irq_chip = {
  222. .name = "max77802-rtc",
  223. .status_base = MAX77802_RTC_INT,
  224. .mask_base = MAX77802_RTC_INTM,
  225. .num_regs = 1,
  226. .irqs = max77686_rtc_irqs, /* same masks as 77686 */
  227. .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
  228. };
  229. static const struct max77686_rtc_driver_data max77802_drv_data = {
  230. .delay = 200,
  231. .mask = 0xff,
  232. .map = max77802_map,
  233. .alarm_enable_reg = true,
  234. .rtc_irq_from_platform = false,
  235. .alarm_pending_status_reg = MAX77686_REG_STATUS2,
  236. .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
  237. .rtc_irq_chip = &max77802_rtc_irq_chip,
  238. };
  239. static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
  240. struct max77686_rtc_info *info)
  241. {
  242. u8 mask = info->drv_data->mask;
  243. tm->tm_sec = data[RTC_SEC] & mask;
  244. tm->tm_min = data[RTC_MIN] & mask;
  245. if (info->rtc_24hr_mode) {
  246. tm->tm_hour = data[RTC_HOUR] & 0x1f;
  247. } else {
  248. tm->tm_hour = data[RTC_HOUR] & 0x0f;
  249. if (data[RTC_HOUR] & HOUR_PM_MASK)
  250. tm->tm_hour += 12;
  251. }
  252. /* Only a single bit is set in data[], so fls() would be equivalent */
  253. tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
  254. tm->tm_mday = data[RTC_DATE] & 0x1f;
  255. tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
  256. tm->tm_year = data[RTC_YEAR] & mask;
  257. tm->tm_yday = 0;
  258. tm->tm_isdst = 0;
  259. /*
  260. * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
  261. * year values are just 0..99 so add 100 to support up to 2099.
  262. */
  263. if (!info->drv_data->alarm_enable_reg)
  264. tm->tm_year += 100;
  265. }
  266. static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
  267. struct max77686_rtc_info *info)
  268. {
  269. data[RTC_SEC] = tm->tm_sec;
  270. data[RTC_MIN] = tm->tm_min;
  271. data[RTC_HOUR] = tm->tm_hour;
  272. data[RTC_WEEKDAY] = 1 << tm->tm_wday;
  273. data[RTC_DATE] = tm->tm_mday;
  274. data[RTC_MONTH] = tm->tm_mon + 1;
  275. if (info->drv_data->alarm_enable_reg) {
  276. data[RTC_YEAR] = tm->tm_year;
  277. return 0;
  278. }
  279. data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
  280. if (tm->tm_year < 100) {
  281. dev_err(info->dev, "RTC cannot handle the year %d.\n",
  282. 1900 + tm->tm_year);
  283. return -EINVAL;
  284. }
  285. return 0;
  286. }
  287. static int max77686_rtc_update(struct max77686_rtc_info *info,
  288. enum MAX77686_RTC_OP op)
  289. {
  290. int ret;
  291. unsigned int data;
  292. unsigned long delay = info->drv_data->delay;
  293. if (op == MAX77686_RTC_WRITE)
  294. data = 1 << RTC_UDR_SHIFT;
  295. else
  296. data = 1 << RTC_RBUDR_SHIFT;
  297. ret = regmap_update_bits(info->rtc_regmap,
  298. info->drv_data->map[REG_RTC_UPDATE0],
  299. data, data);
  300. if (ret < 0)
  301. dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
  302. ret, data);
  303. else {
  304. /* Minimum delay required before RTC update. */
  305. usleep_range(delay, delay * 2);
  306. }
  307. return ret;
  308. }
  309. static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
  310. {
  311. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  312. u8 data[RTC_NR_TIME];
  313. int ret;
  314. mutex_lock(&info->lock);
  315. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  316. if (ret < 0)
  317. goto out;
  318. ret = regmap_bulk_read(info->rtc_regmap,
  319. info->drv_data->map[REG_RTC_SEC],
  320. data, ARRAY_SIZE(data));
  321. if (ret < 0) {
  322. dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
  323. goto out;
  324. }
  325. max77686_rtc_data_to_tm(data, tm, info);
  326. ret = rtc_valid_tm(tm);
  327. out:
  328. mutex_unlock(&info->lock);
  329. return ret;
  330. }
  331. static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
  332. {
  333. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  334. u8 data[RTC_NR_TIME];
  335. int ret;
  336. ret = max77686_rtc_tm_to_data(tm, data, info);
  337. if (ret < 0)
  338. return ret;
  339. mutex_lock(&info->lock);
  340. ret = regmap_bulk_write(info->rtc_regmap,
  341. info->drv_data->map[REG_RTC_SEC],
  342. data, ARRAY_SIZE(data));
  343. if (ret < 0) {
  344. dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
  345. goto out;
  346. }
  347. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  348. out:
  349. mutex_unlock(&info->lock);
  350. return ret;
  351. }
  352. static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  353. {
  354. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  355. u8 data[RTC_NR_TIME];
  356. unsigned int val;
  357. const unsigned int *map = info->drv_data->map;
  358. int i, ret;
  359. mutex_lock(&info->lock);
  360. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  361. if (ret < 0)
  362. goto out;
  363. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  364. data, ARRAY_SIZE(data));
  365. if (ret < 0) {
  366. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  367. goto out;
  368. }
  369. max77686_rtc_data_to_tm(data, &alrm->time, info);
  370. alrm->enabled = 0;
  371. if (info->drv_data->alarm_enable_reg) {
  372. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  373. ret = -EINVAL;
  374. dev_err(info->dev,
  375. "alarm enable register not set(%d)\n", ret);
  376. goto out;
  377. }
  378. ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
  379. if (ret < 0) {
  380. dev_err(info->dev,
  381. "fail to read alarm enable(%d)\n", ret);
  382. goto out;
  383. }
  384. if (val)
  385. alrm->enabled = 1;
  386. } else {
  387. for (i = 0; i < ARRAY_SIZE(data); i++) {
  388. if (data[i] & ALARM_ENABLE_MASK) {
  389. alrm->enabled = 1;
  390. break;
  391. }
  392. }
  393. }
  394. alrm->pending = 0;
  395. if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
  396. goto out;
  397. ret = regmap_read(info->regmap,
  398. info->drv_data->alarm_pending_status_reg, &val);
  399. if (ret < 0) {
  400. dev_err(info->dev,
  401. "Fail to read alarm pending status reg(%d)\n", ret);
  402. goto out;
  403. }
  404. if (val & (1 << 4)) /* RTCA1 */
  405. alrm->pending = 1;
  406. out:
  407. mutex_unlock(&info->lock);
  408. return ret;
  409. }
  410. static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
  411. {
  412. u8 data[RTC_NR_TIME];
  413. int ret, i;
  414. struct rtc_time tm;
  415. const unsigned int *map = info->drv_data->map;
  416. if (!mutex_is_locked(&info->lock))
  417. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  418. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  419. if (ret < 0)
  420. goto out;
  421. if (info->drv_data->alarm_enable_reg) {
  422. if (map[REG_RTC_AE1] == REG_RTC_NONE) {
  423. ret = -EINVAL;
  424. dev_err(info->dev,
  425. "alarm enable register not set(%d)\n", ret);
  426. goto out;
  427. }
  428. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
  429. } else {
  430. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  431. data, ARRAY_SIZE(data));
  432. if (ret < 0) {
  433. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  434. goto out;
  435. }
  436. max77686_rtc_data_to_tm(data, &tm, info);
  437. for (i = 0; i < ARRAY_SIZE(data); i++)
  438. data[i] &= ~ALARM_ENABLE_MASK;
  439. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  440. data, ARRAY_SIZE(data));
  441. }
  442. if (ret < 0) {
  443. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  444. goto out;
  445. }
  446. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  447. out:
  448. return ret;
  449. }
  450. static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
  451. {
  452. u8 data[RTC_NR_TIME];
  453. int ret;
  454. struct rtc_time tm;
  455. const unsigned int *map = info->drv_data->map;
  456. if (!mutex_is_locked(&info->lock))
  457. dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
  458. ret = max77686_rtc_update(info, MAX77686_RTC_READ);
  459. if (ret < 0)
  460. goto out;
  461. if (info->drv_data->alarm_enable_reg) {
  462. ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
  463. MAX77802_ALARM_ENABLE_VALUE);
  464. } else {
  465. ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
  466. data, ARRAY_SIZE(data));
  467. if (ret < 0) {
  468. dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
  469. goto out;
  470. }
  471. max77686_rtc_data_to_tm(data, &tm, info);
  472. data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
  473. data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
  474. data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
  475. data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
  476. if (data[RTC_MONTH] & 0xf)
  477. data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
  478. if (data[RTC_YEAR] & info->drv_data->mask)
  479. data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
  480. if (data[RTC_DATE] & 0x1f)
  481. data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
  482. ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
  483. data, ARRAY_SIZE(data));
  484. }
  485. if (ret < 0) {
  486. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  487. goto out;
  488. }
  489. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  490. out:
  491. return ret;
  492. }
  493. static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
  494. {
  495. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  496. u8 data[RTC_NR_TIME];
  497. int ret;
  498. ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
  499. if (ret < 0)
  500. return ret;
  501. mutex_lock(&info->lock);
  502. ret = max77686_rtc_stop_alarm(info);
  503. if (ret < 0)
  504. goto out;
  505. ret = regmap_bulk_write(info->rtc_regmap,
  506. info->drv_data->map[REG_ALARM1_SEC],
  507. data, ARRAY_SIZE(data));
  508. if (ret < 0) {
  509. dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
  510. goto out;
  511. }
  512. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  513. if (ret < 0)
  514. goto out;
  515. if (alrm->enabled)
  516. ret = max77686_rtc_start_alarm(info);
  517. out:
  518. mutex_unlock(&info->lock);
  519. return ret;
  520. }
  521. static int max77686_rtc_alarm_irq_enable(struct device *dev,
  522. unsigned int enabled)
  523. {
  524. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  525. int ret;
  526. mutex_lock(&info->lock);
  527. if (enabled)
  528. ret = max77686_rtc_start_alarm(info);
  529. else
  530. ret = max77686_rtc_stop_alarm(info);
  531. mutex_unlock(&info->lock);
  532. return ret;
  533. }
  534. static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
  535. {
  536. struct max77686_rtc_info *info = data;
  537. dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
  538. rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
  539. return IRQ_HANDLED;
  540. }
  541. static const struct rtc_class_ops max77686_rtc_ops = {
  542. .read_time = max77686_rtc_read_time,
  543. .set_time = max77686_rtc_set_time,
  544. .read_alarm = max77686_rtc_read_alarm,
  545. .set_alarm = max77686_rtc_set_alarm,
  546. .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
  547. };
  548. static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
  549. {
  550. u8 data[2];
  551. int ret;
  552. /* Set RTC control register : Binary mode, 24hour mdoe */
  553. data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  554. data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
  555. info->rtc_24hr_mode = 1;
  556. ret = regmap_bulk_write(info->rtc_regmap,
  557. info->drv_data->map[REG_RTC_CONTROLM],
  558. data, ARRAY_SIZE(data));
  559. if (ret < 0) {
  560. dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
  561. return ret;
  562. }
  563. ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
  564. return ret;
  565. }
  566. static const struct regmap_config max77686_rtc_regmap_config = {
  567. .reg_bits = 8,
  568. .val_bits = 8,
  569. };
  570. static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
  571. {
  572. struct device *parent = info->dev->parent;
  573. struct i2c_client *parent_i2c = to_i2c_client(parent);
  574. int ret;
  575. if (info->drv_data->rtc_irq_from_platform) {
  576. struct platform_device *pdev = to_platform_device(info->dev);
  577. info->rtc_irq = platform_get_irq(pdev, 0);
  578. if (info->rtc_irq < 0) {
  579. dev_err(info->dev, "Failed to get rtc interrupts: %d\n",
  580. info->rtc_irq);
  581. return info->rtc_irq;
  582. }
  583. } else {
  584. info->rtc_irq = parent_i2c->irq;
  585. }
  586. info->regmap = dev_get_regmap(parent, NULL);
  587. if (!info->regmap) {
  588. dev_err(info->dev, "Failed to get rtc regmap\n");
  589. return -ENODEV;
  590. }
  591. if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
  592. info->rtc_regmap = info->regmap;
  593. goto add_rtc_irq;
  594. }
  595. info->rtc = i2c_new_dummy(parent_i2c->adapter,
  596. info->drv_data->rtc_i2c_addr);
  597. if (!info->rtc) {
  598. dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
  599. return -ENODEV;
  600. }
  601. info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
  602. &max77686_rtc_regmap_config);
  603. if (IS_ERR(info->rtc_regmap)) {
  604. ret = PTR_ERR(info->rtc_regmap);
  605. dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
  606. goto err_unregister_i2c;
  607. }
  608. add_rtc_irq:
  609. ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
  610. IRQF_TRIGGER_FALLING | IRQF_ONESHOT |
  611. IRQF_SHARED, 0, info->drv_data->rtc_irq_chip,
  612. &info->rtc_irq_data);
  613. if (ret < 0) {
  614. dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
  615. goto err_unregister_i2c;
  616. }
  617. return 0;
  618. err_unregister_i2c:
  619. if (info->rtc)
  620. i2c_unregister_device(info->rtc);
  621. return ret;
  622. }
  623. static int max77686_rtc_probe(struct platform_device *pdev)
  624. {
  625. struct max77686_rtc_info *info;
  626. const struct platform_device_id *id = platform_get_device_id(pdev);
  627. int ret;
  628. info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
  629. GFP_KERNEL);
  630. if (!info)
  631. return -ENOMEM;
  632. mutex_init(&info->lock);
  633. info->dev = &pdev->dev;
  634. info->drv_data = (const struct max77686_rtc_driver_data *)
  635. id->driver_data;
  636. ret = max77686_init_rtc_regmap(info);
  637. if (ret < 0)
  638. return ret;
  639. platform_set_drvdata(pdev, info);
  640. ret = max77686_rtc_init_reg(info);
  641. if (ret < 0) {
  642. dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
  643. goto err_rtc;
  644. }
  645. device_init_wakeup(&pdev->dev, 1);
  646. info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
  647. &max77686_rtc_ops, THIS_MODULE);
  648. if (IS_ERR(info->rtc_dev)) {
  649. ret = PTR_ERR(info->rtc_dev);
  650. dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
  651. if (ret == 0)
  652. ret = -EINVAL;
  653. goto err_rtc;
  654. }
  655. info->virq = regmap_irq_get_virq(info->rtc_irq_data,
  656. MAX77686_RTCIRQ_RTCA1);
  657. if (info->virq <= 0) {
  658. ret = -ENXIO;
  659. goto err_rtc;
  660. }
  661. ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
  662. "rtc-alarm1", info);
  663. if (ret < 0) {
  664. dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
  665. info->virq, ret);
  666. goto err_rtc;
  667. }
  668. return 0;
  669. err_rtc:
  670. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  671. if (info->rtc)
  672. i2c_unregister_device(info->rtc);
  673. return ret;
  674. }
  675. static int max77686_rtc_remove(struct platform_device *pdev)
  676. {
  677. struct max77686_rtc_info *info = platform_get_drvdata(pdev);
  678. free_irq(info->virq, info);
  679. regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
  680. if (info->rtc)
  681. i2c_unregister_device(info->rtc);
  682. return 0;
  683. }
  684. #ifdef CONFIG_PM_SLEEP
  685. static int max77686_rtc_suspend(struct device *dev)
  686. {
  687. if (device_may_wakeup(dev)) {
  688. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  689. return enable_irq_wake(info->virq);
  690. }
  691. return 0;
  692. }
  693. static int max77686_rtc_resume(struct device *dev)
  694. {
  695. if (device_may_wakeup(dev)) {
  696. struct max77686_rtc_info *info = dev_get_drvdata(dev);
  697. return disable_irq_wake(info->virq);
  698. }
  699. return 0;
  700. }
  701. #endif
  702. static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
  703. max77686_rtc_suspend, max77686_rtc_resume);
  704. static const struct platform_device_id rtc_id[] = {
  705. { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
  706. { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
  707. { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
  708. {},
  709. };
  710. MODULE_DEVICE_TABLE(platform, rtc_id);
  711. static struct platform_driver max77686_rtc_driver = {
  712. .driver = {
  713. .name = "max77686-rtc",
  714. .pm = &max77686_rtc_pm_ops,
  715. },
  716. .probe = max77686_rtc_probe,
  717. .remove = max77686_rtc_remove,
  718. .id_table = rtc_id,
  719. };
  720. module_platform_driver(max77686_rtc_driver);
  721. MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
  722. MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
  723. MODULE_LICENSE("GPL");