idt_gen3.c 9.8 KB

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  1. /*
  2. * IDT RXS Gen.3 Serial RapidIO switch family support
  3. *
  4. * Copyright 2016 Integrated Device Technology, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/stat.h>
  12. #include <linux/module.h>
  13. #include <linux/rio.h>
  14. #include <linux/rio_drv.h>
  15. #include <linux/rio_ids.h>
  16. #include <linux/delay.h>
  17. #include <asm/page.h>
  18. #include "../rio.h"
  19. #define RIO_EM_PW_STAT 0x40020
  20. #define RIO_PW_CTL 0x40204
  21. #define RIO_PW_CTL_PW_TMR 0xffffff00
  22. #define RIO_PW_ROUTE 0x40208
  23. #define RIO_EM_DEV_INT_EN 0x40030
  24. #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
  25. #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
  26. #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
  27. #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
  28. #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
  29. #define RIO_BC_L2_Gn_ENTRYx_CSR(n, x) (0x31000 + (n)*0x400 + (x)*0x4)
  30. #define RIO_SPx_L2_Gn_ENTRYy_CSR(x, n, y) \
  31. (0x51000 + (x)*0x2000 + (n)*0x400 + (y)*0x4)
  32. static int
  33. idtg3_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
  34. u16 table, u16 route_destid, u8 route_port)
  35. {
  36. u32 rval;
  37. u32 entry = route_port;
  38. int err = 0;
  39. pr_debug("RIO: %s t=0x%x did_%x to p_%x\n",
  40. __func__, table, route_destid, entry);
  41. if (route_destid > 0xFF)
  42. return -EINVAL;
  43. if (route_port == RIO_INVALID_ROUTE)
  44. entry = RIO_RT_ENTRY_DROP_PKT;
  45. if (table == RIO_GLOBAL_TABLE) {
  46. /* Use broadcast register to update all per-port tables */
  47. err = rio_mport_write_config_32(mport, destid, hopcount,
  48. RIO_BC_L2_Gn_ENTRYx_CSR(0, route_destid),
  49. entry);
  50. return err;
  51. }
  52. /*
  53. * Verify that specified port/table number is valid
  54. */
  55. err = rio_mport_read_config_32(mport, destid, hopcount,
  56. RIO_SWP_INFO_CAR, &rval);
  57. if (err)
  58. return err;
  59. if (table >= RIO_GET_TOTAL_PORTS(rval))
  60. return -EINVAL;
  61. err = rio_mport_write_config_32(mport, destid, hopcount,
  62. RIO_SPx_L2_Gn_ENTRYy_CSR(table, 0, route_destid),
  63. entry);
  64. return err;
  65. }
  66. static int
  67. idtg3_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
  68. u16 table, u16 route_destid, u8 *route_port)
  69. {
  70. u32 rval;
  71. int err;
  72. if (route_destid > 0xFF)
  73. return -EINVAL;
  74. err = rio_mport_read_config_32(mport, destid, hopcount,
  75. RIO_SWP_INFO_CAR, &rval);
  76. if (err)
  77. return err;
  78. /*
  79. * This switch device does not have the dedicated global routing table.
  80. * It is substituted by reading routing table of the ingress port of
  81. * maintenance read requests.
  82. */
  83. if (table == RIO_GLOBAL_TABLE)
  84. table = RIO_GET_PORT_NUM(rval);
  85. else if (table >= RIO_GET_TOTAL_PORTS(rval))
  86. return -EINVAL;
  87. err = rio_mport_read_config_32(mport, destid, hopcount,
  88. RIO_SPx_L2_Gn_ENTRYy_CSR(table, 0, route_destid),
  89. &rval);
  90. if (err)
  91. return err;
  92. if (rval == RIO_RT_ENTRY_DROP_PKT)
  93. *route_port = RIO_INVALID_ROUTE;
  94. else
  95. *route_port = (u8)rval;
  96. return 0;
  97. }
  98. static int
  99. idtg3_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
  100. u16 table)
  101. {
  102. u32 i;
  103. u32 rval;
  104. int err;
  105. if (table == RIO_GLOBAL_TABLE) {
  106. for (i = 0; i <= 0xff; i++) {
  107. err = rio_mport_write_config_32(mport, destid, hopcount,
  108. RIO_BC_L2_Gn_ENTRYx_CSR(0, i),
  109. RIO_RT_ENTRY_DROP_PKT);
  110. if (err)
  111. break;
  112. }
  113. return err;
  114. }
  115. err = rio_mport_read_config_32(mport, destid, hopcount,
  116. RIO_SWP_INFO_CAR, &rval);
  117. if (err)
  118. return err;
  119. if (table >= RIO_GET_TOTAL_PORTS(rval))
  120. return -EINVAL;
  121. for (i = 0; i <= 0xff; i++) {
  122. err = rio_mport_write_config_32(mport, destid, hopcount,
  123. RIO_SPx_L2_Gn_ENTRYy_CSR(table, 0, i),
  124. RIO_RT_ENTRY_DROP_PKT);
  125. if (err)
  126. break;
  127. }
  128. return err;
  129. }
  130. /*
  131. * This routine performs device-specific initialization only.
  132. * All standard EM configuration should be performed at upper level.
  133. */
  134. static int
  135. idtg3_em_init(struct rio_dev *rdev)
  136. {
  137. int i, tmp;
  138. u32 rval;
  139. pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
  140. /* Disable assertion of interrupt signal */
  141. rio_write_config_32(rdev, RIO_EM_DEV_INT_EN, 0);
  142. /* Disable port-write event notifications during initialization */
  143. rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL,
  144. RIO_EM_PW_TX_CTRL_PW_DIS);
  145. /* Configure Port-Write notifications for hot-swap events */
  146. tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo);
  147. for (i = 0; i < tmp; i++) {
  148. rio_read_config_32(rdev,
  149. RIO_DEV_PORT_N_ERR_STS_CSR(rdev, i),
  150. &rval);
  151. if (rval & RIO_PORT_N_ERR_STS_PORT_UA)
  152. continue;
  153. /* Clear events signaled before enabling notification */
  154. rio_write_config_32(rdev,
  155. rdev->em_efptr + RIO_EM_PN_ERR_DETECT(i), 0);
  156. /* Enable event notifications */
  157. rio_write_config_32(rdev,
  158. rdev->em_efptr + RIO_EM_PN_ERRRATE_EN(i),
  159. RIO_EM_PN_ERRRATE_EN_OK2U | RIO_EM_PN_ERRRATE_EN_U2OK);
  160. /* Enable port-write generation on events */
  161. rio_write_config_32(rdev, RIO_PLM_SPx_PW_EN(i),
  162. RIO_PLM_SPx_PW_EN_OK2U | RIO_PLM_SPx_PW_EN_LINIT);
  163. }
  164. /* Set Port-Write destination port */
  165. tmp = RIO_GET_PORT_NUM(rdev->swpinfo);
  166. rio_write_config_32(rdev, RIO_PW_ROUTE, 1 << tmp);
  167. /* Enable sending port-write event notifications */
  168. rio_write_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0);
  169. /* set TVAL = ~50us */
  170. rio_write_config_32(rdev,
  171. rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8);
  172. return 0;
  173. }
  174. /*
  175. * idtg3_em_handler - device-specific error handler
  176. *
  177. * If the link is down (PORT_UNINIT) does nothing - this is considered
  178. * as link partner removal from the port.
  179. *
  180. * If the link is up (PORT_OK) - situation is handled as *new* device insertion.
  181. * In this case ERR_STOP bits are cleared by issuing soft reset command to the
  182. * reporting port. Inbound and outbound ackIDs are cleared by the reset as well.
  183. * This way the port is synchronized with freshly inserted device (assuming it
  184. * was reset/powered-up on insertion).
  185. *
  186. * TODO: This is not sufficient in a situation when a link between two devices
  187. * was down and up again (e.g. cable disconnect). For that situation full ackID
  188. * realignment process has to be implemented.
  189. */
  190. static int
  191. idtg3_em_handler(struct rio_dev *rdev, u8 pnum)
  192. {
  193. u32 err_status;
  194. u32 rval;
  195. rio_read_config_32(rdev,
  196. RIO_DEV_PORT_N_ERR_STS_CSR(rdev, pnum),
  197. &err_status);
  198. /* Do nothing for device/link removal */
  199. if (err_status & RIO_PORT_N_ERR_STS_PORT_UNINIT)
  200. return 0;
  201. /* When link is OK we have a device insertion.
  202. * Request port soft reset to clear errors if they present.
  203. * Inbound and outbound ackIDs will be 0 after reset.
  204. */
  205. if (err_status & (RIO_PORT_N_ERR_STS_OUT_ES |
  206. RIO_PORT_N_ERR_STS_INP_ES)) {
  207. rio_read_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), &rval);
  208. rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum),
  209. rval | RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST);
  210. udelay(10);
  211. rio_write_config_32(rdev, RIO_PLM_SPx_IMP_SPEC_CTL(pnum), rval);
  212. msleep(500);
  213. }
  214. return 0;
  215. }
  216. static struct rio_switch_ops idtg3_switch_ops = {
  217. .owner = THIS_MODULE,
  218. .add_entry = idtg3_route_add_entry,
  219. .get_entry = idtg3_route_get_entry,
  220. .clr_table = idtg3_route_clr_table,
  221. .em_init = idtg3_em_init,
  222. .em_handle = idtg3_em_handler,
  223. };
  224. static int idtg3_probe(struct rio_dev *rdev, const struct rio_device_id *id)
  225. {
  226. pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
  227. spin_lock(&rdev->rswitch->lock);
  228. if (rdev->rswitch->ops) {
  229. spin_unlock(&rdev->rswitch->lock);
  230. return -EINVAL;
  231. }
  232. rdev->rswitch->ops = &idtg3_switch_ops;
  233. if (rdev->do_enum) {
  234. /* Disable hierarchical routing support: Existing fabric
  235. * enumeration/discovery process (see rio-scan.c) uses 8-bit
  236. * flat destination ID routing only.
  237. */
  238. rio_write_config_32(rdev, 0x5000 + RIO_BC_RT_CTL_CSR, 0);
  239. }
  240. spin_unlock(&rdev->rswitch->lock);
  241. return 0;
  242. }
  243. static void idtg3_remove(struct rio_dev *rdev)
  244. {
  245. pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
  246. spin_lock(&rdev->rswitch->lock);
  247. if (rdev->rswitch->ops == &idtg3_switch_ops)
  248. rdev->rswitch->ops = NULL;
  249. spin_unlock(&rdev->rswitch->lock);
  250. }
  251. /*
  252. * Gen3 switches repeat sending PW messages until a corresponding event flag
  253. * is cleared. Use shutdown notification to disable generation of port-write
  254. * messages if their destination node is shut down.
  255. */
  256. static void idtg3_shutdown(struct rio_dev *rdev)
  257. {
  258. int i;
  259. u32 rval;
  260. u16 destid;
  261. /* Currently the enumerator node acts also as PW handler */
  262. if (!rdev->do_enum)
  263. return;
  264. pr_debug("RIO: %s(%s)\n", __func__, rio_name(rdev));
  265. rio_read_config_32(rdev, RIO_PW_ROUTE, &rval);
  266. i = RIO_GET_PORT_NUM(rdev->swpinfo);
  267. /* Check port-write destination port */
  268. if (!((1 << i) & rval))
  269. return;
  270. /* Disable sending port-write event notifications if PW destID
  271. * matches to one of the enumerator node
  272. */
  273. rio_read_config_32(rdev, rdev->em_efptr + RIO_EM_PW_TGT_DEVID, &rval);
  274. if (rval & RIO_EM_PW_TGT_DEVID_DEV16)
  275. destid = rval >> 16;
  276. else
  277. destid = ((rval & RIO_EM_PW_TGT_DEVID_D8) >> 16);
  278. if (rdev->net->hport->host_deviceid == destid) {
  279. rio_write_config_32(rdev,
  280. rdev->em_efptr + RIO_EM_PW_TX_CTRL, 0);
  281. pr_debug("RIO: %s(%s) PW transmission disabled\n",
  282. __func__, rio_name(rdev));
  283. }
  284. }
  285. static struct rio_device_id idtg3_id_table[] = {
  286. {RIO_DEVICE(RIO_DID_IDTRXS1632, RIO_VID_IDT)},
  287. {RIO_DEVICE(RIO_DID_IDTRXS2448, RIO_VID_IDT)},
  288. { 0, } /* terminate list */
  289. };
  290. static struct rio_driver idtg3_driver = {
  291. .name = "idt_gen3",
  292. .id_table = idtg3_id_table,
  293. .probe = idtg3_probe,
  294. .remove = idtg3_remove,
  295. .shutdown = idtg3_shutdown,
  296. };
  297. static int __init idtg3_init(void)
  298. {
  299. return rio_register_driver(&idtg3_driver);
  300. }
  301. static void __exit idtg3_exit(void)
  302. {
  303. pr_debug("RIO: %s\n", __func__);
  304. rio_unregister_driver(&idtg3_driver);
  305. pr_debug("RIO: %s done\n", __func__);
  306. }
  307. device_initcall(idtg3_init);
  308. module_exit(idtg3_exit);
  309. MODULE_DESCRIPTION("IDT RXS Gen.3 Serial RapidIO switch family driver");
  310. MODULE_AUTHOR("Integrated Device Technology, Inc.");
  311. MODULE_LICENSE("GPL");