pwm-lpc32xx.c 4.4 KB

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  1. /*
  2. * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2.
  7. *
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/err.h>
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pwm.h>
  18. #include <linux/slab.h>
  19. struct lpc32xx_pwm_chip {
  20. struct pwm_chip chip;
  21. struct clk *clk;
  22. void __iomem *base;
  23. };
  24. #define PWM_ENABLE BIT(31)
  25. #define PWM_PIN_LEVEL BIT(30)
  26. #define to_lpc32xx_pwm_chip(_chip) \
  27. container_of(_chip, struct lpc32xx_pwm_chip, chip)
  28. static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  29. int duty_ns, int period_ns)
  30. {
  31. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  32. unsigned long long c;
  33. int period_cycles, duty_cycles;
  34. u32 val;
  35. c = clk_get_rate(lpc32xx->clk);
  36. /* The highest acceptable divisor is 256, which is represented by 0 */
  37. period_cycles = div64_u64(c * period_ns,
  38. (unsigned long long)NSEC_PER_SEC * 256);
  39. if (!period_cycles || period_cycles > 256)
  40. return -ERANGE;
  41. if (period_cycles == 256)
  42. period_cycles = 0;
  43. /* Compute 256 x #duty/period value and care for corner cases */
  44. duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
  45. period_ns);
  46. if (!duty_cycles)
  47. duty_cycles = 1;
  48. if (duty_cycles > 255)
  49. duty_cycles = 255;
  50. val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  51. val &= ~0xFFFF;
  52. val |= (period_cycles << 8) | duty_cycles;
  53. writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  54. return 0;
  55. }
  56. static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  57. {
  58. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  59. u32 val;
  60. int ret;
  61. ret = clk_prepare_enable(lpc32xx->clk);
  62. if (ret)
  63. return ret;
  64. val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  65. val |= PWM_ENABLE;
  66. writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  67. return 0;
  68. }
  69. static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  70. {
  71. struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
  72. u32 val;
  73. val = readl(lpc32xx->base + (pwm->hwpwm << 2));
  74. val &= ~PWM_ENABLE;
  75. writel(val, lpc32xx->base + (pwm->hwpwm << 2));
  76. clk_disable_unprepare(lpc32xx->clk);
  77. }
  78. static const struct pwm_ops lpc32xx_pwm_ops = {
  79. .config = lpc32xx_pwm_config,
  80. .enable = lpc32xx_pwm_enable,
  81. .disable = lpc32xx_pwm_disable,
  82. .owner = THIS_MODULE,
  83. };
  84. static int lpc32xx_pwm_probe(struct platform_device *pdev)
  85. {
  86. struct lpc32xx_pwm_chip *lpc32xx;
  87. struct resource *res;
  88. int ret;
  89. u32 val;
  90. lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
  91. if (!lpc32xx)
  92. return -ENOMEM;
  93. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  94. lpc32xx->base = devm_ioremap_resource(&pdev->dev, res);
  95. if (IS_ERR(lpc32xx->base))
  96. return PTR_ERR(lpc32xx->base);
  97. lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
  98. if (IS_ERR(lpc32xx->clk))
  99. return PTR_ERR(lpc32xx->clk);
  100. lpc32xx->chip.dev = &pdev->dev;
  101. lpc32xx->chip.ops = &lpc32xx_pwm_ops;
  102. lpc32xx->chip.npwm = 1;
  103. lpc32xx->chip.base = -1;
  104. ret = pwmchip_add(&lpc32xx->chip);
  105. if (ret < 0) {
  106. dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
  107. return ret;
  108. }
  109. /* When PWM is disable, configure the output to the default value */
  110. val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
  111. val &= ~PWM_PIN_LEVEL;
  112. writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
  113. platform_set_drvdata(pdev, lpc32xx);
  114. return 0;
  115. }
  116. static int lpc32xx_pwm_remove(struct platform_device *pdev)
  117. {
  118. struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev);
  119. unsigned int i;
  120. for (i = 0; i < lpc32xx->chip.npwm; i++)
  121. pwm_disable(&lpc32xx->chip.pwms[i]);
  122. return pwmchip_remove(&lpc32xx->chip);
  123. }
  124. static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
  125. { .compatible = "nxp,lpc3220-pwm", },
  126. { /* sentinel */ }
  127. };
  128. MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
  129. static struct platform_driver lpc32xx_pwm_driver = {
  130. .driver = {
  131. .name = "lpc32xx-pwm",
  132. .of_match_table = lpc32xx_pwm_dt_ids,
  133. },
  134. .probe = lpc32xx_pwm_probe,
  135. .remove = lpc32xx_pwm_remove,
  136. };
  137. module_platform_driver(lpc32xx_pwm_driver);
  138. MODULE_ALIAS("platform:lpc32xx-pwm");
  139. MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
  140. MODULE_DESCRIPTION("LPC32XX PWM Driver");
  141. MODULE_LICENSE("GPL v2");