scc.c 54 KB

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  1. #define RCS_ID "$Id: scc.c,v 1.75 1998/11/04 15:15:01 jreuter Exp jreuter $"
  2. #define VERSION "3.0"
  3. /*
  4. * Please use z8530drv-utils-3.0 with this version.
  5. * ------------------
  6. *
  7. * You can find a subset of the documentation in
  8. * Documentation/networking/z8530drv.txt.
  9. */
  10. /*
  11. ********************************************************************
  12. * SCC.C - Linux driver for Z8530 based HDLC cards for AX.25 *
  13. ********************************************************************
  14. ********************************************************************
  15. Copyright (c) 1993, 2000 Joerg Reuter DL1BKE
  16. portions (c) 1993 Guido ten Dolle PE1NNZ
  17. ********************************************************************
  18. The driver and the programs in the archive are UNDER CONSTRUCTION.
  19. The code is likely to fail, and so your kernel could --- even
  20. a whole network.
  21. This driver is intended for Amateur Radio use. If you are running it
  22. for commercial purposes, please drop me a note. I am nosy...
  23. ...BUT:
  24. ! You m u s t recognize the appropriate legislations of your country !
  25. ! before you connect a radio to the SCC board and start to transmit or !
  26. ! receive. The GPL allows you to use the d r i v e r, NOT the RADIO! !
  27. For non-Amateur-Radio use please note that you might need a special
  28. allowance/licence from the designer of the SCC Board and/or the
  29. MODEM.
  30. This program is free software; you can redistribute it and/or modify
  31. it under the terms of the (modified) GNU General Public License
  32. delivered with the Linux kernel source.
  33. This program is distributed in the hope that it will be useful,
  34. but WITHOUT ANY WARRANTY; without even the implied warranty of
  35. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  36. GNU General Public License for more details.
  37. You should find a copy of the GNU General Public License in
  38. /usr/src/linux/COPYING;
  39. ********************************************************************
  40. Incomplete history of z8530drv:
  41. -------------------------------
  42. 1994-09-13 started to write the driver, rescued most of my own
  43. code (and Hans Alblas' memory buffer pool concept) from
  44. an earlier project "sccdrv" which was initiated by
  45. Guido ten Dolle. Not much of the old driver survived,
  46. though. The first version I put my hands on was sccdrv1.3
  47. from August 1993. The memory buffer pool concept
  48. appeared in an unauthorized sccdrv version (1.5) from
  49. August 1994.
  50. 1995-01-31 changed copyright notice to GPL without limitations.
  51. .
  52. . <SNIP>
  53. .
  54. 1996-10-05 New semester, new driver...
  55. * KISS TNC emulator removed (TTY driver)
  56. * Source moved to drivers/net/
  57. * Includes Z8530 defines from drivers/net/z8530.h
  58. * Uses sk_buffer memory management
  59. * Reduced overhead of /proc/net/z8530drv output
  60. * Streamlined quite a lot things
  61. * Invents brand new bugs... ;-)
  62. The move to version number 3.0 reflects theses changes.
  63. You can use 'kissbridge' if you need a KISS TNC emulator.
  64. 1996-12-13 Fixed for Linux networking changes. (G4KLX)
  65. 1997-01-08 Fixed the remaining problems.
  66. 1997-04-02 Hopefully fixed the problems with the new *_timer()
  67. routines, added calibration code.
  68. 1997-10-12 Made SCC_DELAY a CONFIG option, added CONFIG_SCC_TRXECHO
  69. 1998-01-29 Small fix to avoid lock-up on initialization
  70. 1998-09-29 Fixed the "grouping" bugs, tx_inhibit works again,
  71. using dev->tx_queue_len now instead of MAXQUEUE now.
  72. 1998-10-21 Postponed the spinlock changes, would need a lot of
  73. testing I currently don't have the time to. Softdcd doesn't
  74. work.
  75. 1998-11-04 Softdcd does not work correctly in DPLL mode, in fact it
  76. never did. The DPLL locks on noise, the SYNC unit sees
  77. flags that aren't... Restarting the DPLL does not help
  78. either, it resynchronizes too slow and the first received
  79. frame gets lost.
  80. 2000-02-13 Fixed for new network driver interface changes, still
  81. does TX timeouts itself since it uses its own queue
  82. scheme.
  83. Thanks to all who contributed to this driver with ideas and bug
  84. reports!
  85. NB -- if you find errors, change something, please let me know
  86. first before you distribute it... And please don't touch
  87. the version number. Just replace my callsign in
  88. "v3.0.dl1bke" with your own. Just to avoid confusion...
  89. If you want to add your modification to the linux distribution
  90. please (!) contact me first.
  91. New versions of the driver will be announced on the linux-hams
  92. mailing list on vger.kernel.org. To subscribe send an e-mail
  93. to majordomo@vger.kernel.org with the following line in
  94. the body of the mail:
  95. subscribe linux-hams
  96. The content of the "Subject" field will be ignored.
  97. vy 73,
  98. Joerg Reuter ampr-net: dl1bke@db0pra.ampr.org
  99. AX-25 : DL1BKE @ DB0ABH.#BAY.DEU.EU
  100. Internet: jreuter@yaina.de
  101. www : http://yaina.de/jreuter
  102. */
  103. /* ----------------------------------------------------------------------- */
  104. #undef SCC_LDELAY /* slow it even a bit more down */
  105. #undef SCC_DONT_CHECK /* don't look if the SCCs you specified are available */
  106. #define SCC_MAXCHIPS 4 /* number of max. supported chips */
  107. #define SCC_BUFSIZE 384 /* must not exceed 4096 */
  108. #undef SCC_DEBUG
  109. #define SCC_DEFAULT_CLOCK 4915200
  110. /* default pclock if nothing is specified */
  111. /* ----------------------------------------------------------------------- */
  112. #include <linux/module.h>
  113. #include <linux/errno.h>
  114. #include <linux/signal.h>
  115. #include <linux/timer.h>
  116. #include <linux/interrupt.h>
  117. #include <linux/ioport.h>
  118. #include <linux/string.h>
  119. #include <linux/in.h>
  120. #include <linux/fcntl.h>
  121. #include <linux/ptrace.h>
  122. #include <linux/delay.h>
  123. #include <linux/skbuff.h>
  124. #include <linux/netdevice.h>
  125. #include <linux/rtnetlink.h>
  126. #include <linux/if_ether.h>
  127. #include <linux/if_arp.h>
  128. #include <linux/socket.h>
  129. #include <linux/init.h>
  130. #include <linux/scc.h>
  131. #include <linux/ctype.h>
  132. #include <linux/kernel.h>
  133. #include <linux/proc_fs.h>
  134. #include <linux/seq_file.h>
  135. #include <linux/bitops.h>
  136. #include <net/net_namespace.h>
  137. #include <net/ax25.h>
  138. #include <asm/irq.h>
  139. #include <asm/io.h>
  140. #include <asm/uaccess.h>
  141. #include "z8530.h"
  142. static const char banner[] __initconst = KERN_INFO \
  143. "AX.25: Z8530 SCC driver version "VERSION".dl1bke\n";
  144. static void t_dwait(unsigned long);
  145. static void t_txdelay(unsigned long);
  146. static void t_tail(unsigned long);
  147. static void t_busy(unsigned long);
  148. static void t_maxkeyup(unsigned long);
  149. static void t_idle(unsigned long);
  150. static void scc_tx_done(struct scc_channel *);
  151. static void scc_start_tx_timer(struct scc_channel *, void (*)(unsigned long), unsigned long);
  152. static void scc_start_maxkeyup(struct scc_channel *);
  153. static void scc_start_defer(struct scc_channel *);
  154. static void z8530_init(void);
  155. static void init_channel(struct scc_channel *scc);
  156. static void scc_key_trx (struct scc_channel *scc, char tx);
  157. static void scc_init_timer(struct scc_channel *scc);
  158. static int scc_net_alloc(const char *name, struct scc_channel *scc);
  159. static void scc_net_setup(struct net_device *dev);
  160. static int scc_net_open(struct net_device *dev);
  161. static int scc_net_close(struct net_device *dev);
  162. static void scc_net_rx(struct scc_channel *scc, struct sk_buff *skb);
  163. static netdev_tx_t scc_net_tx(struct sk_buff *skb,
  164. struct net_device *dev);
  165. static int scc_net_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
  166. static int scc_net_set_mac_address(struct net_device *dev, void *addr);
  167. static struct net_device_stats * scc_net_get_stats(struct net_device *dev);
  168. static unsigned char SCC_DriverName[] = "scc";
  169. static struct irqflags { unsigned char used : 1; } Ivec[NR_IRQS];
  170. static struct scc_channel SCC_Info[2 * SCC_MAXCHIPS]; /* information per channel */
  171. static struct scc_ctrl {
  172. io_port chan_A;
  173. io_port chan_B;
  174. int irq;
  175. } SCC_ctrl[SCC_MAXCHIPS+1];
  176. static unsigned char Driver_Initialized;
  177. static int Nchips;
  178. static io_port Vector_Latch;
  179. /* ******************************************************************** */
  180. /* * Port Access Functions * */
  181. /* ******************************************************************** */
  182. /* These provide interrupt save 2-step access to the Z8530 registers */
  183. static DEFINE_SPINLOCK(iolock); /* Guards paired accesses */
  184. static inline unsigned char InReg(io_port port, unsigned char reg)
  185. {
  186. unsigned long flags;
  187. unsigned char r;
  188. spin_lock_irqsave(&iolock, flags);
  189. #ifdef SCC_LDELAY
  190. Outb(port, reg);
  191. udelay(SCC_LDELAY);
  192. r=Inb(port);
  193. udelay(SCC_LDELAY);
  194. #else
  195. Outb(port, reg);
  196. r=Inb(port);
  197. #endif
  198. spin_unlock_irqrestore(&iolock, flags);
  199. return r;
  200. }
  201. static inline void OutReg(io_port port, unsigned char reg, unsigned char val)
  202. {
  203. unsigned long flags;
  204. spin_lock_irqsave(&iolock, flags);
  205. #ifdef SCC_LDELAY
  206. Outb(port, reg); udelay(SCC_LDELAY);
  207. Outb(port, val); udelay(SCC_LDELAY);
  208. #else
  209. Outb(port, reg);
  210. Outb(port, val);
  211. #endif
  212. spin_unlock_irqrestore(&iolock, flags);
  213. }
  214. static inline void wr(struct scc_channel *scc, unsigned char reg,
  215. unsigned char val)
  216. {
  217. OutReg(scc->ctrl, reg, (scc->wreg[reg] = val));
  218. }
  219. static inline void or(struct scc_channel *scc, unsigned char reg, unsigned char val)
  220. {
  221. OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val));
  222. }
  223. static inline void cl(struct scc_channel *scc, unsigned char reg, unsigned char val)
  224. {
  225. OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val));
  226. }
  227. /* ******************************************************************** */
  228. /* * Some useful macros * */
  229. /* ******************************************************************** */
  230. static inline void scc_discard_buffers(struct scc_channel *scc)
  231. {
  232. unsigned long flags;
  233. spin_lock_irqsave(&scc->lock, flags);
  234. if (scc->tx_buff != NULL)
  235. {
  236. dev_kfree_skb(scc->tx_buff);
  237. scc->tx_buff = NULL;
  238. }
  239. while (!skb_queue_empty(&scc->tx_queue))
  240. dev_kfree_skb(skb_dequeue(&scc->tx_queue));
  241. spin_unlock_irqrestore(&scc->lock, flags);
  242. }
  243. /* ******************************************************************** */
  244. /* * Interrupt Service Routines * */
  245. /* ******************************************************************** */
  246. /* ----> subroutines for the interrupt handlers <---- */
  247. static inline void scc_notify(struct scc_channel *scc, int event)
  248. {
  249. struct sk_buff *skb;
  250. char *bp;
  251. if (scc->kiss.fulldup != KISS_DUPLEX_OPTIMA)
  252. return;
  253. skb = dev_alloc_skb(2);
  254. if (skb != NULL)
  255. {
  256. bp = skb_put(skb, 2);
  257. *bp++ = PARAM_HWEVENT;
  258. *bp++ = event;
  259. scc_net_rx(scc, skb);
  260. } else
  261. scc->stat.nospace++;
  262. }
  263. static inline void flush_rx_FIFO(struct scc_channel *scc)
  264. {
  265. int k;
  266. for (k=0; k<3; k++)
  267. Inb(scc->data);
  268. if(scc->rx_buff != NULL) /* did we receive something? */
  269. {
  270. scc->stat.rxerrs++; /* then count it as an error */
  271. dev_kfree_skb_irq(scc->rx_buff);
  272. scc->rx_buff = NULL;
  273. }
  274. }
  275. static void start_hunt(struct scc_channel *scc)
  276. {
  277. if ((scc->modem.clocksrc != CLK_EXTERNAL))
  278. OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
  279. or(scc,R3,ENT_HM|RxENABLE); /* enable the receiver, hunt mode */
  280. }
  281. /* ----> four different interrupt handlers for Tx, Rx, changing of */
  282. /* DCD/CTS and Rx/Tx errors */
  283. /* Transmitter interrupt handler */
  284. static inline void scc_txint(struct scc_channel *scc)
  285. {
  286. struct sk_buff *skb;
  287. scc->stat.txints++;
  288. skb = scc->tx_buff;
  289. /* send first octet */
  290. if (skb == NULL)
  291. {
  292. skb = skb_dequeue(&scc->tx_queue);
  293. scc->tx_buff = skb;
  294. netif_wake_queue(scc->dev);
  295. if (skb == NULL)
  296. {
  297. scc_tx_done(scc);
  298. Outb(scc->ctrl, RES_Tx_P);
  299. return;
  300. }
  301. if (skb->len == 0) /* Paranoia... */
  302. {
  303. dev_kfree_skb_irq(skb);
  304. scc->tx_buff = NULL;
  305. scc_tx_done(scc);
  306. Outb(scc->ctrl, RES_Tx_P);
  307. return;
  308. }
  309. scc->stat.tx_state = TXS_ACTIVE;
  310. OutReg(scc->ctrl, R0, RES_Tx_CRC);
  311. /* reset CRC generator */
  312. or(scc,R10,ABUNDER); /* re-install underrun protection */
  313. Outb(scc->data,*skb->data); /* send byte */
  314. skb_pull(skb, 1);
  315. if (!scc->enhanced) /* reset EOM latch */
  316. Outb(scc->ctrl,RES_EOM_L);
  317. return;
  318. }
  319. /* End Of Frame... */
  320. if (skb->len == 0)
  321. {
  322. Outb(scc->ctrl, RES_Tx_P); /* reset pending int */
  323. cl(scc, R10, ABUNDER); /* send CRC */
  324. dev_kfree_skb_irq(skb);
  325. scc->tx_buff = NULL;
  326. scc->stat.tx_state = TXS_NEWFRAME; /* next frame... */
  327. return;
  328. }
  329. /* send octet */
  330. Outb(scc->data,*skb->data);
  331. skb_pull(skb, 1);
  332. }
  333. /* External/Status interrupt handler */
  334. static inline void scc_exint(struct scc_channel *scc)
  335. {
  336. unsigned char status,changes,chg_and_stat;
  337. scc->stat.exints++;
  338. status = InReg(scc->ctrl,R0);
  339. changes = status ^ scc->status;
  340. chg_and_stat = changes & status;
  341. /* ABORT: generated whenever DCD drops while receiving */
  342. if (chg_and_stat & BRK_ABRT) /* Received an ABORT */
  343. flush_rx_FIFO(scc);
  344. /* HUNT: software DCD; on = waiting for SYNC, off = receiving frame */
  345. if ((changes & SYNC_HUNT) && scc->kiss.softdcd)
  346. {
  347. if (status & SYNC_HUNT)
  348. {
  349. scc->dcd = 0;
  350. flush_rx_FIFO(scc);
  351. if ((scc->modem.clocksrc != CLK_EXTERNAL))
  352. OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
  353. } else {
  354. scc->dcd = 1;
  355. }
  356. scc_notify(scc, scc->dcd? HWEV_DCD_OFF:HWEV_DCD_ON);
  357. }
  358. /* DCD: on = start to receive packet, off = ABORT condition */
  359. /* (a successfully received packet generates a special condition int) */
  360. if((changes & DCD) && !scc->kiss.softdcd) /* DCD input changed state */
  361. {
  362. if(status & DCD) /* DCD is now ON */
  363. {
  364. start_hunt(scc);
  365. scc->dcd = 1;
  366. } else { /* DCD is now OFF */
  367. cl(scc,R3,ENT_HM|RxENABLE); /* disable the receiver */
  368. flush_rx_FIFO(scc);
  369. scc->dcd = 0;
  370. }
  371. scc_notify(scc, scc->dcd? HWEV_DCD_ON:HWEV_DCD_OFF);
  372. }
  373. #ifdef notdef
  374. /* CTS: use external TxDelay (what's that good for?!)
  375. * Anyway: If we _could_ use it (BayCom USCC uses CTS for
  376. * own purposes) we _should_ use the "autoenable" feature
  377. * of the Z8530 and not this interrupt...
  378. */
  379. if (chg_and_stat & CTS) /* CTS is now ON */
  380. {
  381. if (scc->kiss.txdelay == 0) /* zero TXDELAY = wait for CTS */
  382. scc_start_tx_timer(scc, t_txdelay, 0);
  383. }
  384. #endif
  385. if (scc->stat.tx_state == TXS_ACTIVE && (status & TxEOM))
  386. {
  387. scc->stat.tx_under++; /* oops, an underrun! count 'em */
  388. Outb(scc->ctrl, RES_EXT_INT); /* reset ext/status interrupts */
  389. if (scc->tx_buff != NULL)
  390. {
  391. dev_kfree_skb_irq(scc->tx_buff);
  392. scc->tx_buff = NULL;
  393. }
  394. or(scc,R10,ABUNDER);
  395. scc_start_tx_timer(scc, t_txdelay, 0); /* restart transmission */
  396. }
  397. scc->status = status;
  398. Outb(scc->ctrl,RES_EXT_INT);
  399. }
  400. /* Receiver interrupt handler */
  401. static inline void scc_rxint(struct scc_channel *scc)
  402. {
  403. struct sk_buff *skb;
  404. scc->stat.rxints++;
  405. if((scc->wreg[5] & RTS) && scc->kiss.fulldup == KISS_DUPLEX_HALF)
  406. {
  407. Inb(scc->data); /* discard char */
  408. or(scc,R3,ENT_HM); /* enter hunt mode for next flag */
  409. return;
  410. }
  411. skb = scc->rx_buff;
  412. if (skb == NULL)
  413. {
  414. skb = dev_alloc_skb(scc->stat.bufsize);
  415. if (skb == NULL)
  416. {
  417. scc->dev_stat.rx_dropped++;
  418. scc->stat.nospace++;
  419. Inb(scc->data);
  420. or(scc, R3, ENT_HM);
  421. return;
  422. }
  423. scc->rx_buff = skb;
  424. *(skb_put(skb, 1)) = 0; /* KISS data */
  425. }
  426. if (skb->len >= scc->stat.bufsize)
  427. {
  428. #ifdef notdef
  429. printk(KERN_DEBUG "z8530drv: oops, scc_rxint() received huge frame...\n");
  430. #endif
  431. dev_kfree_skb_irq(skb);
  432. scc->rx_buff = NULL;
  433. Inb(scc->data);
  434. or(scc, R3, ENT_HM);
  435. return;
  436. }
  437. *(skb_put(skb, 1)) = Inb(scc->data);
  438. }
  439. /* Receive Special Condition interrupt handler */
  440. static inline void scc_spint(struct scc_channel *scc)
  441. {
  442. unsigned char status;
  443. struct sk_buff *skb;
  444. scc->stat.spints++;
  445. status = InReg(scc->ctrl,R1); /* read receiver status */
  446. Inb(scc->data); /* throw away Rx byte */
  447. skb = scc->rx_buff;
  448. if(status & Rx_OVR) /* receiver overrun */
  449. {
  450. scc->stat.rx_over++; /* count them */
  451. or(scc,R3,ENT_HM); /* enter hunt mode for next flag */
  452. if (skb != NULL)
  453. dev_kfree_skb_irq(skb);
  454. scc->rx_buff = skb = NULL;
  455. }
  456. if(status & END_FR && skb != NULL) /* end of frame */
  457. {
  458. /* CRC okay, frame ends on 8 bit boundary and received something ? */
  459. if (!(status & CRC_ERR) && (status & 0xe) == RES8 && skb->len > 0)
  460. {
  461. /* ignore last received byte (first of the CRC bytes) */
  462. skb_trim(skb, skb->len-1);
  463. scc_net_rx(scc, skb);
  464. scc->rx_buff = NULL;
  465. scc->stat.rxframes++;
  466. } else { /* a bad frame */
  467. dev_kfree_skb_irq(skb);
  468. scc->rx_buff = NULL;
  469. scc->stat.rxerrs++;
  470. }
  471. }
  472. Outb(scc->ctrl,ERR_RES);
  473. }
  474. /* ----> interrupt service routine for the Z8530 <---- */
  475. static void scc_isr_dispatch(struct scc_channel *scc, int vector)
  476. {
  477. spin_lock(&scc->lock);
  478. switch (vector & VECTOR_MASK)
  479. {
  480. case TXINT: scc_txint(scc); break;
  481. case EXINT: scc_exint(scc); break;
  482. case RXINT: scc_rxint(scc); break;
  483. case SPINT: scc_spint(scc); break;
  484. }
  485. spin_unlock(&scc->lock);
  486. }
  487. /* If the card has a latch for the interrupt vector (like the PA0HZP card)
  488. use it to get the number of the chip that generated the int.
  489. If not: poll all defined chips.
  490. */
  491. #define SCC_IRQTIMEOUT 30000
  492. static irqreturn_t scc_isr(int irq, void *dev_id)
  493. {
  494. int chip_irq = (long) dev_id;
  495. unsigned char vector;
  496. struct scc_channel *scc;
  497. struct scc_ctrl *ctrl;
  498. int k;
  499. if (Vector_Latch)
  500. {
  501. for(k=0; k < SCC_IRQTIMEOUT; k++)
  502. {
  503. Outb(Vector_Latch, 0); /* Generate INTACK */
  504. /* Read the vector */
  505. if((vector=Inb(Vector_Latch)) >= 16 * Nchips) break;
  506. if (vector & 0x01) break;
  507. scc=&SCC_Info[vector >> 3 ^ 0x01];
  508. if (!scc->dev) break;
  509. scc_isr_dispatch(scc, vector);
  510. OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */
  511. }
  512. if (k == SCC_IRQTIMEOUT)
  513. printk(KERN_WARNING "z8530drv: endless loop in scc_isr()?\n");
  514. return IRQ_HANDLED;
  515. }
  516. /* Find the SCC generating the interrupt by polling all attached SCCs
  517. * reading RR3A (the interrupt pending register)
  518. */
  519. ctrl = SCC_ctrl;
  520. while (ctrl->chan_A)
  521. {
  522. if (ctrl->irq != chip_irq)
  523. {
  524. ctrl++;
  525. continue;
  526. }
  527. scc = NULL;
  528. for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++)
  529. {
  530. vector=InReg(ctrl->chan_B,R2); /* Read the vector */
  531. if (vector & 0x01) break;
  532. scc = &SCC_Info[vector >> 3 ^ 0x01];
  533. if (!scc->dev) break;
  534. scc_isr_dispatch(scc, vector);
  535. }
  536. if (k == SCC_IRQTIMEOUT)
  537. {
  538. printk(KERN_WARNING "z8530drv: endless loop in scc_isr()?!\n");
  539. break;
  540. }
  541. /* This looks weird and it is. At least the BayCom USCC doesn't
  542. * use the Interrupt Daisy Chain, thus we'll have to start
  543. * all over again to be sure not to miss an interrupt from
  544. * (any of) the other chip(s)...
  545. * Honestly, the situation *is* braindamaged...
  546. */
  547. if (scc != NULL)
  548. {
  549. OutReg(scc->ctrl,R0,RES_H_IUS);
  550. ctrl = SCC_ctrl;
  551. } else
  552. ctrl++;
  553. }
  554. return IRQ_HANDLED;
  555. }
  556. /* ******************************************************************** */
  557. /* * Init Channel */
  558. /* ******************************************************************** */
  559. /* ----> set SCC channel speed <---- */
  560. static inline void set_brg(struct scc_channel *scc, unsigned int tc)
  561. {
  562. cl(scc,R14,BRENABL); /* disable baudrate generator */
  563. wr(scc,R12,tc & 255); /* brg rate LOW */
  564. wr(scc,R13,tc >> 8); /* brg rate HIGH */
  565. or(scc,R14,BRENABL); /* enable baudrate generator */
  566. }
  567. static inline void set_speed(struct scc_channel *scc)
  568. {
  569. unsigned long flags;
  570. spin_lock_irqsave(&scc->lock, flags);
  571. if (scc->modem.speed > 0) /* paranoia... */
  572. set_brg(scc, (unsigned) (scc->clock / (scc->modem.speed * 64)) - 2);
  573. spin_unlock_irqrestore(&scc->lock, flags);
  574. }
  575. /* ----> initialize a SCC channel <---- */
  576. static inline void init_brg(struct scc_channel *scc)
  577. {
  578. wr(scc, R14, BRSRC); /* BRG source = PCLK */
  579. OutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]); /* DPLL source = BRG */
  580. OutReg(scc->ctrl, R14, SNRZI|scc->wreg[R14]); /* DPLL NRZI mode */
  581. }
  582. /*
  583. * Initialization according to the Z8530 manual (SGS-Thomson's version):
  584. *
  585. * 1. Modes and constants
  586. *
  587. * WR9 11000000 chip reset
  588. * WR4 XXXXXXXX Tx/Rx control, async or sync mode
  589. * WR1 0XX00X00 select W/REQ (optional)
  590. * WR2 XXXXXXXX program interrupt vector
  591. * WR3 XXXXXXX0 select Rx control
  592. * WR5 XXXX0XXX select Tx control
  593. * WR6 XXXXXXXX sync character
  594. * WR7 XXXXXXXX sync character
  595. * WR9 000X0XXX select interrupt control
  596. * WR10 XXXXXXXX miscellaneous control (optional)
  597. * WR11 XXXXXXXX clock control
  598. * WR12 XXXXXXXX time constant lower byte (optional)
  599. * WR13 XXXXXXXX time constant upper byte (optional)
  600. * WR14 XXXXXXX0 miscellaneous control
  601. * WR14 XXXSSSSS commands (optional)
  602. *
  603. * 2. Enables
  604. *
  605. * WR14 000SSSS1 baud rate enable
  606. * WR3 SSSSSSS1 Rx enable
  607. * WR5 SSSS1SSS Tx enable
  608. * WR0 10000000 reset Tx CRG (optional)
  609. * WR1 XSS00S00 DMA enable (optional)
  610. *
  611. * 3. Interrupt status
  612. *
  613. * WR15 XXXXXXXX enable external/status
  614. * WR0 00010000 reset external status
  615. * WR0 00010000 reset external status twice
  616. * WR1 SSSXXSXX enable Rx, Tx and Ext/status
  617. * WR9 000SXSSS enable master interrupt enable
  618. *
  619. * 1 = set to one, 0 = reset to zero
  620. * X = user defined, S = same as previous init
  621. *
  622. *
  623. * Note that the implementation differs in some points from above scheme.
  624. *
  625. */
  626. static void init_channel(struct scc_channel *scc)
  627. {
  628. del_timer(&scc->tx_t);
  629. del_timer(&scc->tx_wdog);
  630. disable_irq(scc->irq);
  631. wr(scc,R4,X1CLK|SDLC); /* *1 clock, SDLC mode */
  632. wr(scc,R1,0); /* no W/REQ operation */
  633. wr(scc,R3,Rx8|RxCRC_ENAB); /* RX 8 bits/char, CRC, disabled */
  634. wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */
  635. wr(scc,R6,0); /* SDLC address zero (not used) */
  636. wr(scc,R7,FLAG); /* SDLC flag value */
  637. wr(scc,R9,VIS); /* vector includes status */
  638. wr(scc,R10,(scc->modem.nrz? NRZ : NRZI)|CRCPS|ABUNDER); /* abort on underrun, preset CRC generator, NRZ(I) */
  639. wr(scc,R14, 0);
  640. /* set clock sources:
  641. CLK_DPLL: normal halfduplex operation
  642. RxClk: use DPLL
  643. TxClk: use DPLL
  644. TRxC mode DPLL output
  645. CLK_EXTERNAL: external clocking (G3RUH or DF9IC modem)
  646. BayCom: others:
  647. TxClk = pin RTxC TxClk = pin TRxC
  648. RxClk = pin TRxC RxClk = pin RTxC
  649. CLK_DIVIDER:
  650. RxClk = use DPLL
  651. TxClk = pin RTxC
  652. BayCom: others:
  653. pin TRxC = DPLL pin TRxC = BRG
  654. (RxClk * 1) (RxClk * 32)
  655. */
  656. switch(scc->modem.clocksrc)
  657. {
  658. case CLK_DPLL:
  659. wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP);
  660. init_brg(scc);
  661. break;
  662. case CLK_DIVIDER:
  663. wr(scc, R11, ((scc->brand & BAYCOM)? TRxCDP : TRxCBR) | RCDPLL|TCRTxCP|TRxCOI);
  664. init_brg(scc);
  665. break;
  666. case CLK_EXTERNAL:
  667. wr(scc, R11, (scc->brand & BAYCOM)? RCTRxCP|TCRTxCP : RCRTxCP|TCTRxCP);
  668. OutReg(scc->ctrl, R14, DISDPLL);
  669. break;
  670. }
  671. set_speed(scc); /* set baudrate */
  672. if(scc->enhanced)
  673. {
  674. or(scc,R15,SHDLCE|FIFOE); /* enable FIFO, SDLC/HDLC Enhancements (From now R7 is R7') */
  675. wr(scc,R7,AUTOEOM);
  676. }
  677. if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD))
  678. /* DCD is now ON */
  679. {
  680. start_hunt(scc);
  681. }
  682. /* enable ABORT, DCD & SYNC/HUNT interrupts */
  683. wr(scc,R15, BRKIE|TxUIE|(scc->kiss.softdcd? SYNCIE:DCDIE));
  684. Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */
  685. Outb(scc->ctrl,RES_EXT_INT); /* must be done twice */
  686. or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */
  687. scc->status = InReg(scc->ctrl,R0); /* read initial status */
  688. or(scc,R9,MIE); /* master interrupt enable */
  689. scc_init_timer(scc);
  690. enable_irq(scc->irq);
  691. }
  692. /* ******************************************************************** */
  693. /* * SCC timer functions * */
  694. /* ******************************************************************** */
  695. /* ----> scc_key_trx sets the time constant for the baudrate
  696. generator and keys the transmitter <---- */
  697. static void scc_key_trx(struct scc_channel *scc, char tx)
  698. {
  699. unsigned int time_const;
  700. if (scc->brand & PRIMUS)
  701. Outb(scc->ctrl + 4, scc->option | (tx? 0x80 : 0));
  702. if (scc->modem.speed < 300)
  703. scc->modem.speed = 1200;
  704. time_const = (unsigned) (scc->clock / (scc->modem.speed * (tx? 2:64))) - 2;
  705. disable_irq(scc->irq);
  706. if (tx)
  707. {
  708. or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */
  709. or(scc, R15, TxUIE);
  710. }
  711. if (scc->modem.clocksrc == CLK_DPLL)
  712. { /* force simplex operation */
  713. if (tx)
  714. {
  715. #ifdef CONFIG_SCC_TRXECHO
  716. cl(scc, R3, RxENABLE|ENT_HM); /* switch off receiver */
  717. cl(scc, R15, DCDIE|SYNCIE); /* No DCD changes, please */
  718. #endif
  719. set_brg(scc, time_const); /* reprogram baudrate generator */
  720. /* DPLL -> Rx clk, BRG -> Tx CLK, TRxC mode output, TRxC = BRG */
  721. wr(scc, R11, RCDPLL|TCBR|TRxCOI|TRxCBR);
  722. /* By popular demand: tx_inhibit */
  723. if (scc->kiss.tx_inhibit)
  724. {
  725. or(scc,R5, TxENAB);
  726. scc->wreg[R5] |= RTS;
  727. } else {
  728. or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */
  729. }
  730. } else {
  731. cl(scc,R5,RTS|TxENAB);
  732. set_brg(scc, time_const); /* reprogram baudrate generator */
  733. /* DPLL -> Rx clk, DPLL -> Tx CLK, TRxC mode output, TRxC = DPLL */
  734. wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP);
  735. #ifndef CONFIG_SCC_TRXECHO
  736. if (scc->kiss.softdcd)
  737. #endif
  738. {
  739. or(scc,R15, scc->kiss.softdcd? SYNCIE:DCDIE);
  740. start_hunt(scc);
  741. }
  742. }
  743. } else {
  744. if (tx)
  745. {
  746. #ifdef CONFIG_SCC_TRXECHO
  747. if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
  748. {
  749. cl(scc, R3, RxENABLE);
  750. cl(scc, R15, DCDIE|SYNCIE);
  751. }
  752. #endif
  753. if (scc->kiss.tx_inhibit)
  754. {
  755. or(scc,R5, TxENAB);
  756. scc->wreg[R5] |= RTS;
  757. } else {
  758. or(scc,R5,RTS|TxENAB); /* enable tx */
  759. }
  760. } else {
  761. cl(scc,R5,RTS|TxENAB); /* disable tx */
  762. if ((scc->kiss.fulldup == KISS_DUPLEX_HALF) &&
  763. #ifndef CONFIG_SCC_TRXECHO
  764. scc->kiss.softdcd)
  765. #else
  766. 1)
  767. #endif
  768. {
  769. or(scc, R15, scc->kiss.softdcd? SYNCIE:DCDIE);
  770. start_hunt(scc);
  771. }
  772. }
  773. }
  774. enable_irq(scc->irq);
  775. }
  776. /* ----> SCC timer interrupt handler and friends. <---- */
  777. static void __scc_start_tx_timer(struct scc_channel *scc, void (*handler)(unsigned long), unsigned long when)
  778. {
  779. del_timer(&scc->tx_t);
  780. if (when == 0)
  781. {
  782. handler((unsigned long) scc);
  783. } else
  784. if (when != TIMER_OFF)
  785. {
  786. scc->tx_t.data = (unsigned long) scc;
  787. scc->tx_t.function = handler;
  788. scc->tx_t.expires = jiffies + (when*HZ)/100;
  789. add_timer(&scc->tx_t);
  790. }
  791. }
  792. static void scc_start_tx_timer(struct scc_channel *scc, void (*handler)(unsigned long), unsigned long when)
  793. {
  794. unsigned long flags;
  795. spin_lock_irqsave(&scc->lock, flags);
  796. __scc_start_tx_timer(scc, handler, when);
  797. spin_unlock_irqrestore(&scc->lock, flags);
  798. }
  799. static void scc_start_defer(struct scc_channel *scc)
  800. {
  801. unsigned long flags;
  802. spin_lock_irqsave(&scc->lock, flags);
  803. del_timer(&scc->tx_wdog);
  804. if (scc->kiss.maxdefer != 0 && scc->kiss.maxdefer != TIMER_OFF)
  805. {
  806. scc->tx_wdog.data = (unsigned long) scc;
  807. scc->tx_wdog.function = t_busy;
  808. scc->tx_wdog.expires = jiffies + HZ*scc->kiss.maxdefer;
  809. add_timer(&scc->tx_wdog);
  810. }
  811. spin_unlock_irqrestore(&scc->lock, flags);
  812. }
  813. static void scc_start_maxkeyup(struct scc_channel *scc)
  814. {
  815. unsigned long flags;
  816. spin_lock_irqsave(&scc->lock, flags);
  817. del_timer(&scc->tx_wdog);
  818. if (scc->kiss.maxkeyup != 0 && scc->kiss.maxkeyup != TIMER_OFF)
  819. {
  820. scc->tx_wdog.data = (unsigned long) scc;
  821. scc->tx_wdog.function = t_maxkeyup;
  822. scc->tx_wdog.expires = jiffies + HZ*scc->kiss.maxkeyup;
  823. add_timer(&scc->tx_wdog);
  824. }
  825. spin_unlock_irqrestore(&scc->lock, flags);
  826. }
  827. /*
  828. * This is called from scc_txint() when there are no more frames to send.
  829. * Not exactly a timer function, but it is a close friend of the family...
  830. */
  831. static void scc_tx_done(struct scc_channel *scc)
  832. {
  833. /*
  834. * trx remains keyed in fulldup mode 2 until t_idle expires.
  835. */
  836. switch (scc->kiss.fulldup)
  837. {
  838. case KISS_DUPLEX_LINK:
  839. scc->stat.tx_state = TXS_IDLE2;
  840. if (scc->kiss.idletime != TIMER_OFF)
  841. scc_start_tx_timer(scc, t_idle,
  842. scc->kiss.idletime*100);
  843. break;
  844. case KISS_DUPLEX_OPTIMA:
  845. scc_notify(scc, HWEV_ALL_SENT);
  846. break;
  847. default:
  848. scc->stat.tx_state = TXS_BUSY;
  849. scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime);
  850. }
  851. netif_wake_queue(scc->dev);
  852. }
  853. static unsigned char Rand = 17;
  854. static inline int is_grouped(struct scc_channel *scc)
  855. {
  856. int k;
  857. struct scc_channel *scc2;
  858. unsigned char grp1, grp2;
  859. grp1 = scc->kiss.group;
  860. for (k = 0; k < (Nchips * 2); k++)
  861. {
  862. scc2 = &SCC_Info[k];
  863. grp2 = scc2->kiss.group;
  864. if (scc2 == scc || !(scc2->dev && grp2))
  865. continue;
  866. if ((grp1 & 0x3f) == (grp2 & 0x3f))
  867. {
  868. if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) )
  869. return 1;
  870. if ( (grp1 & RXGROUP) && scc2->dcd )
  871. return 1;
  872. }
  873. }
  874. return 0;
  875. }
  876. /* DWAIT and SLOTTIME expired
  877. *
  878. * fulldup == 0: DCD is active or Rand > P-persistence: start t_busy timer
  879. * else key trx and start txdelay
  880. * fulldup == 1: key trx and start txdelay
  881. * fulldup == 2: mintime expired, reset status or key trx and start txdelay
  882. */
  883. static void t_dwait(unsigned long channel)
  884. {
  885. struct scc_channel *scc = (struct scc_channel *) channel;
  886. if (scc->stat.tx_state == TXS_WAIT) /* maxkeyup or idle timeout */
  887. {
  888. if (skb_queue_empty(&scc->tx_queue)) { /* nothing to send */
  889. scc->stat.tx_state = TXS_IDLE;
  890. netif_wake_queue(scc->dev); /* t_maxkeyup locked it. */
  891. return;
  892. }
  893. scc->stat.tx_state = TXS_BUSY;
  894. }
  895. if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
  896. {
  897. Rand = Rand * 17 + 31;
  898. if (scc->dcd || (scc->kiss.persist) < Rand || (scc->kiss.group && is_grouped(scc)) )
  899. {
  900. scc_start_defer(scc);
  901. scc_start_tx_timer(scc, t_dwait, scc->kiss.slottime);
  902. return ;
  903. }
  904. }
  905. if ( !(scc->wreg[R5] & RTS) )
  906. {
  907. scc_key_trx(scc, TX_ON);
  908. scc_start_tx_timer(scc, t_txdelay, scc->kiss.txdelay);
  909. } else {
  910. scc_start_tx_timer(scc, t_txdelay, 0);
  911. }
  912. }
  913. /* TXDELAY expired
  914. *
  915. * kick transmission by a fake scc_txint(scc), start 'maxkeyup' watchdog.
  916. */
  917. static void t_txdelay(unsigned long channel)
  918. {
  919. struct scc_channel *scc = (struct scc_channel *) channel;
  920. scc_start_maxkeyup(scc);
  921. if (scc->tx_buff == NULL)
  922. {
  923. disable_irq(scc->irq);
  924. scc_txint(scc);
  925. enable_irq(scc->irq);
  926. }
  927. }
  928. /* TAILTIME expired
  929. *
  930. * switch off transmitter. If we were stopped by Maxkeyup restart
  931. * transmission after 'mintime' seconds
  932. */
  933. static void t_tail(unsigned long channel)
  934. {
  935. struct scc_channel *scc = (struct scc_channel *) channel;
  936. unsigned long flags;
  937. spin_lock_irqsave(&scc->lock, flags);
  938. del_timer(&scc->tx_wdog);
  939. scc_key_trx(scc, TX_OFF);
  940. spin_unlock_irqrestore(&scc->lock, flags);
  941. if (scc->stat.tx_state == TXS_TIMEOUT) /* we had a timeout? */
  942. {
  943. scc->stat.tx_state = TXS_WAIT;
  944. scc_start_tx_timer(scc, t_dwait, scc->kiss.mintime*100);
  945. return;
  946. }
  947. scc->stat.tx_state = TXS_IDLE;
  948. netif_wake_queue(scc->dev);
  949. }
  950. /* BUSY timeout
  951. *
  952. * throw away send buffers if DCD remains active too long.
  953. */
  954. static void t_busy(unsigned long channel)
  955. {
  956. struct scc_channel *scc = (struct scc_channel *) channel;
  957. del_timer(&scc->tx_t);
  958. netif_stop_queue(scc->dev); /* don't pile on the wabbit! */
  959. scc_discard_buffers(scc);
  960. scc->stat.txerrs++;
  961. scc->stat.tx_state = TXS_IDLE;
  962. netif_wake_queue(scc->dev);
  963. }
  964. /* MAXKEYUP timeout
  965. *
  966. * this is our watchdog.
  967. */
  968. static void t_maxkeyup(unsigned long channel)
  969. {
  970. struct scc_channel *scc = (struct scc_channel *) channel;
  971. unsigned long flags;
  972. spin_lock_irqsave(&scc->lock, flags);
  973. /*
  974. * let things settle down before we start to
  975. * accept new data.
  976. */
  977. netif_stop_queue(scc->dev);
  978. scc_discard_buffers(scc);
  979. del_timer(&scc->tx_t);
  980. cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */
  981. cl(scc, R15, TxUIE); /* count it. */
  982. OutReg(scc->ctrl, R0, RES_Tx_P);
  983. spin_unlock_irqrestore(&scc->lock, flags);
  984. scc->stat.txerrs++;
  985. scc->stat.tx_state = TXS_TIMEOUT;
  986. scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime);
  987. }
  988. /* IDLE timeout
  989. *
  990. * in fulldup mode 2 it keys down the transmitter after 'idle' seconds
  991. * of inactivity. We will not restart transmission before 'mintime'
  992. * expires.
  993. */
  994. static void t_idle(unsigned long channel)
  995. {
  996. struct scc_channel *scc = (struct scc_channel *) channel;
  997. del_timer(&scc->tx_wdog);
  998. scc_key_trx(scc, TX_OFF);
  999. if(scc->kiss.mintime)
  1000. scc_start_tx_timer(scc, t_dwait, scc->kiss.mintime*100);
  1001. scc->stat.tx_state = TXS_WAIT;
  1002. }
  1003. static void scc_init_timer(struct scc_channel *scc)
  1004. {
  1005. unsigned long flags;
  1006. spin_lock_irqsave(&scc->lock, flags);
  1007. scc->stat.tx_state = TXS_IDLE;
  1008. spin_unlock_irqrestore(&scc->lock, flags);
  1009. }
  1010. /* ******************************************************************** */
  1011. /* * Set/get L1 parameters * */
  1012. /* ******************************************************************** */
  1013. /*
  1014. * this will set the "hardware" parameters through KISS commands or ioctl()
  1015. */
  1016. #define CAST(x) (unsigned long)(x)
  1017. static unsigned int scc_set_param(struct scc_channel *scc, unsigned int cmd, unsigned int arg)
  1018. {
  1019. switch (cmd)
  1020. {
  1021. case PARAM_TXDELAY: scc->kiss.txdelay=arg; break;
  1022. case PARAM_PERSIST: scc->kiss.persist=arg; break;
  1023. case PARAM_SLOTTIME: scc->kiss.slottime=arg; break;
  1024. case PARAM_TXTAIL: scc->kiss.tailtime=arg; break;
  1025. case PARAM_FULLDUP: scc->kiss.fulldup=arg; break;
  1026. case PARAM_DTR: break; /* does someone need this? */
  1027. case PARAM_GROUP: scc->kiss.group=arg; break;
  1028. case PARAM_IDLE: scc->kiss.idletime=arg; break;
  1029. case PARAM_MIN: scc->kiss.mintime=arg; break;
  1030. case PARAM_MAXKEY: scc->kiss.maxkeyup=arg; break;
  1031. case PARAM_WAIT: scc->kiss.waittime=arg; break;
  1032. case PARAM_MAXDEFER: scc->kiss.maxdefer=arg; break;
  1033. case PARAM_TX: scc->kiss.tx_inhibit=arg; break;
  1034. case PARAM_SOFTDCD:
  1035. scc->kiss.softdcd=arg;
  1036. if (arg)
  1037. {
  1038. or(scc, R15, SYNCIE);
  1039. cl(scc, R15, DCDIE);
  1040. start_hunt(scc);
  1041. } else {
  1042. or(scc, R15, DCDIE);
  1043. cl(scc, R15, SYNCIE);
  1044. }
  1045. break;
  1046. case PARAM_SPEED:
  1047. if (arg < 256)
  1048. scc->modem.speed=arg*100;
  1049. else
  1050. scc->modem.speed=arg;
  1051. if (scc->stat.tx_state == 0) /* only switch baudrate on rx... ;-) */
  1052. set_speed(scc);
  1053. break;
  1054. case PARAM_RTS:
  1055. if ( !(scc->wreg[R5] & RTS) )
  1056. {
  1057. if (arg != TX_OFF) {
  1058. scc_key_trx(scc, TX_ON);
  1059. scc_start_tx_timer(scc, t_txdelay, scc->kiss.txdelay);
  1060. }
  1061. } else {
  1062. if (arg == TX_OFF)
  1063. {
  1064. scc->stat.tx_state = TXS_BUSY;
  1065. scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime);
  1066. }
  1067. }
  1068. break;
  1069. case PARAM_HWEVENT:
  1070. scc_notify(scc, scc->dcd? HWEV_DCD_ON:HWEV_DCD_OFF);
  1071. break;
  1072. default: return -EINVAL;
  1073. }
  1074. return 0;
  1075. }
  1076. static unsigned long scc_get_param(struct scc_channel *scc, unsigned int cmd)
  1077. {
  1078. switch (cmd)
  1079. {
  1080. case PARAM_TXDELAY: return CAST(scc->kiss.txdelay);
  1081. case PARAM_PERSIST: return CAST(scc->kiss.persist);
  1082. case PARAM_SLOTTIME: return CAST(scc->kiss.slottime);
  1083. case PARAM_TXTAIL: return CAST(scc->kiss.tailtime);
  1084. case PARAM_FULLDUP: return CAST(scc->kiss.fulldup);
  1085. case PARAM_SOFTDCD: return CAST(scc->kiss.softdcd);
  1086. case PARAM_DTR: return CAST((scc->wreg[R5] & DTR)? 1:0);
  1087. case PARAM_RTS: return CAST((scc->wreg[R5] & RTS)? 1:0);
  1088. case PARAM_SPEED: return CAST(scc->modem.speed);
  1089. case PARAM_GROUP: return CAST(scc->kiss.group);
  1090. case PARAM_IDLE: return CAST(scc->kiss.idletime);
  1091. case PARAM_MIN: return CAST(scc->kiss.mintime);
  1092. case PARAM_MAXKEY: return CAST(scc->kiss.maxkeyup);
  1093. case PARAM_WAIT: return CAST(scc->kiss.waittime);
  1094. case PARAM_MAXDEFER: return CAST(scc->kiss.maxdefer);
  1095. case PARAM_TX: return CAST(scc->kiss.tx_inhibit);
  1096. default: return NO_SUCH_PARAM;
  1097. }
  1098. }
  1099. #undef CAST
  1100. /* ******************************************************************* */
  1101. /* * Send calibration pattern * */
  1102. /* ******************************************************************* */
  1103. static void scc_stop_calibrate(unsigned long channel)
  1104. {
  1105. struct scc_channel *scc = (struct scc_channel *) channel;
  1106. unsigned long flags;
  1107. spin_lock_irqsave(&scc->lock, flags);
  1108. del_timer(&scc->tx_wdog);
  1109. scc_key_trx(scc, TX_OFF);
  1110. wr(scc, R6, 0);
  1111. wr(scc, R7, FLAG);
  1112. Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */
  1113. Outb(scc->ctrl,RES_EXT_INT);
  1114. netif_wake_queue(scc->dev);
  1115. spin_unlock_irqrestore(&scc->lock, flags);
  1116. }
  1117. static void
  1118. scc_start_calibrate(struct scc_channel *scc, int duration, unsigned char pattern)
  1119. {
  1120. unsigned long flags;
  1121. spin_lock_irqsave(&scc->lock, flags);
  1122. netif_stop_queue(scc->dev);
  1123. scc_discard_buffers(scc);
  1124. del_timer(&scc->tx_wdog);
  1125. scc->tx_wdog.data = (unsigned long) scc;
  1126. scc->tx_wdog.function = scc_stop_calibrate;
  1127. scc->tx_wdog.expires = jiffies + HZ*duration;
  1128. add_timer(&scc->tx_wdog);
  1129. /* This doesn't seem to work. Why not? */
  1130. wr(scc, R6, 0);
  1131. wr(scc, R7, pattern);
  1132. /*
  1133. * Don't know if this works.
  1134. * Damn, where is my Z8530 programming manual...?
  1135. */
  1136. Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */
  1137. Outb(scc->ctrl,RES_EXT_INT);
  1138. scc_key_trx(scc, TX_ON);
  1139. spin_unlock_irqrestore(&scc->lock, flags);
  1140. }
  1141. /* ******************************************************************* */
  1142. /* * Init channel structures, special HW, etc... * */
  1143. /* ******************************************************************* */
  1144. /*
  1145. * Reset the Z8530s and setup special hardware
  1146. */
  1147. static void z8530_init(void)
  1148. {
  1149. struct scc_channel *scc;
  1150. int chip, k;
  1151. unsigned long flags;
  1152. char *flag;
  1153. printk(KERN_INFO "Init Z8530 driver: %u channels, IRQ", Nchips*2);
  1154. flag=" ";
  1155. for (k = 0; k < nr_irqs; k++)
  1156. if (Ivec[k].used)
  1157. {
  1158. printk("%s%d", flag, k);
  1159. flag=",";
  1160. }
  1161. printk("\n");
  1162. /* reset and pre-init all chips in the system */
  1163. for (chip = 0; chip < Nchips; chip++)
  1164. {
  1165. scc=&SCC_Info[2*chip];
  1166. if (!scc->ctrl) continue;
  1167. /* Special SCC cards */
  1168. if(scc->brand & EAGLE) /* this is an EAGLE card */
  1169. Outb(scc->special,0x08); /* enable interrupt on the board */
  1170. if(scc->brand & (PC100 | PRIMUS)) /* this is a PC100/PRIMUS card */
  1171. Outb(scc->special,scc->option); /* set the MODEM mode (0x22) */
  1172. /* Reset and pre-init Z8530 */
  1173. spin_lock_irqsave(&scc->lock, flags);
  1174. Outb(scc->ctrl, 0);
  1175. OutReg(scc->ctrl,R9,FHWRES); /* force hardware reset */
  1176. udelay(100); /* give it 'a bit' more time than required */
  1177. wr(scc, R2, chip*16); /* interrupt vector */
  1178. wr(scc, R9, VIS); /* vector includes status */
  1179. spin_unlock_irqrestore(&scc->lock, flags);
  1180. }
  1181. Driver_Initialized = 1;
  1182. }
  1183. /*
  1184. * Allocate device structure, err, instance, and register driver
  1185. */
  1186. static int scc_net_alloc(const char *name, struct scc_channel *scc)
  1187. {
  1188. int err;
  1189. struct net_device *dev;
  1190. dev = alloc_netdev(0, name, NET_NAME_UNKNOWN, scc_net_setup);
  1191. if (!dev)
  1192. return -ENOMEM;
  1193. dev->ml_priv = scc;
  1194. scc->dev = dev;
  1195. spin_lock_init(&scc->lock);
  1196. init_timer(&scc->tx_t);
  1197. init_timer(&scc->tx_wdog);
  1198. err = register_netdevice(dev);
  1199. if (err) {
  1200. printk(KERN_ERR "%s: can't register network device (%d)\n",
  1201. name, err);
  1202. free_netdev(dev);
  1203. scc->dev = NULL;
  1204. return err;
  1205. }
  1206. return 0;
  1207. }
  1208. /* ******************************************************************** */
  1209. /* * Network driver methods * */
  1210. /* ******************************************************************** */
  1211. static const struct net_device_ops scc_netdev_ops = {
  1212. .ndo_open = scc_net_open,
  1213. .ndo_stop = scc_net_close,
  1214. .ndo_start_xmit = scc_net_tx,
  1215. .ndo_set_mac_address = scc_net_set_mac_address,
  1216. .ndo_get_stats = scc_net_get_stats,
  1217. .ndo_do_ioctl = scc_net_ioctl,
  1218. };
  1219. /* ----> Initialize device <----- */
  1220. static void scc_net_setup(struct net_device *dev)
  1221. {
  1222. dev->tx_queue_len = 16; /* should be enough... */
  1223. dev->netdev_ops = &scc_netdev_ops;
  1224. dev->header_ops = &ax25_header_ops;
  1225. memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
  1226. memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
  1227. dev->flags = 0;
  1228. dev->type = ARPHRD_AX25;
  1229. dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
  1230. dev->mtu = AX25_DEF_PACLEN;
  1231. dev->addr_len = AX25_ADDR_LEN;
  1232. }
  1233. /* ----> open network device <---- */
  1234. static int scc_net_open(struct net_device *dev)
  1235. {
  1236. struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
  1237. if (!scc->init)
  1238. return -EINVAL;
  1239. scc->tx_buff = NULL;
  1240. skb_queue_head_init(&scc->tx_queue);
  1241. init_channel(scc);
  1242. netif_start_queue(dev);
  1243. return 0;
  1244. }
  1245. /* ----> close network device <---- */
  1246. static int scc_net_close(struct net_device *dev)
  1247. {
  1248. struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
  1249. unsigned long flags;
  1250. netif_stop_queue(dev);
  1251. spin_lock_irqsave(&scc->lock, flags);
  1252. Outb(scc->ctrl,0); /* Make sure pointer is written */
  1253. wr(scc,R1,0); /* disable interrupts */
  1254. wr(scc,R3,0);
  1255. spin_unlock_irqrestore(&scc->lock, flags);
  1256. del_timer_sync(&scc->tx_t);
  1257. del_timer_sync(&scc->tx_wdog);
  1258. scc_discard_buffers(scc);
  1259. return 0;
  1260. }
  1261. /* ----> receive frame, called from scc_rxint() <---- */
  1262. static void scc_net_rx(struct scc_channel *scc, struct sk_buff *skb)
  1263. {
  1264. if (skb->len == 0) {
  1265. dev_kfree_skb_irq(skb);
  1266. return;
  1267. }
  1268. scc->dev_stat.rx_packets++;
  1269. scc->dev_stat.rx_bytes += skb->len;
  1270. skb->protocol = ax25_type_trans(skb, scc->dev);
  1271. netif_rx(skb);
  1272. }
  1273. /* ----> transmit frame <---- */
  1274. static netdev_tx_t scc_net_tx(struct sk_buff *skb, struct net_device *dev)
  1275. {
  1276. struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
  1277. unsigned long flags;
  1278. char kisscmd;
  1279. if (skb->protocol == htons(ETH_P_IP))
  1280. return ax25_ip_xmit(skb);
  1281. if (skb->len > scc->stat.bufsize || skb->len < 2) {
  1282. scc->dev_stat.tx_dropped++; /* bogus frame */
  1283. dev_kfree_skb(skb);
  1284. return NETDEV_TX_OK;
  1285. }
  1286. scc->dev_stat.tx_packets++;
  1287. scc->dev_stat.tx_bytes += skb->len;
  1288. scc->stat.txframes++;
  1289. kisscmd = *skb->data & 0x1f;
  1290. skb_pull(skb, 1);
  1291. if (kisscmd) {
  1292. scc_set_param(scc, kisscmd, *skb->data);
  1293. dev_kfree_skb(skb);
  1294. return NETDEV_TX_OK;
  1295. }
  1296. spin_lock_irqsave(&scc->lock, flags);
  1297. if (skb_queue_len(&scc->tx_queue) > scc->dev->tx_queue_len) {
  1298. struct sk_buff *skb_del;
  1299. skb_del = skb_dequeue(&scc->tx_queue);
  1300. dev_kfree_skb(skb_del);
  1301. }
  1302. skb_queue_tail(&scc->tx_queue, skb);
  1303. netif_trans_update(dev);
  1304. /*
  1305. * Start transmission if the trx state is idle or
  1306. * t_idle hasn't expired yet. Use dwait/persistence/slottime
  1307. * algorithm for normal halfduplex operation.
  1308. */
  1309. if(scc->stat.tx_state == TXS_IDLE || scc->stat.tx_state == TXS_IDLE2) {
  1310. scc->stat.tx_state = TXS_BUSY;
  1311. if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
  1312. __scc_start_tx_timer(scc, t_dwait, scc->kiss.waittime);
  1313. else
  1314. __scc_start_tx_timer(scc, t_dwait, 0);
  1315. }
  1316. spin_unlock_irqrestore(&scc->lock, flags);
  1317. return NETDEV_TX_OK;
  1318. }
  1319. /* ----> ioctl functions <---- */
  1320. /*
  1321. * SIOCSCCCFG - configure driver arg: (struct scc_hw_config *) arg
  1322. * SIOCSCCINI - initialize driver arg: ---
  1323. * SIOCSCCCHANINI - initialize channel arg: (struct scc_modem *) arg
  1324. * SIOCSCCSMEM - set memory arg: (struct scc_mem_config *) arg
  1325. * SIOCSCCGKISS - get level 1 parameter arg: (struct scc_kiss_cmd *) arg
  1326. * SIOCSCCSKISS - set level 1 parameter arg: (struct scc_kiss_cmd *) arg
  1327. * SIOCSCCGSTAT - get driver status arg: (struct scc_stat *) arg
  1328. * SIOCSCCCAL - send calib. pattern arg: (struct scc_calibrate *) arg
  1329. */
  1330. static int scc_net_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1331. {
  1332. struct scc_kiss_cmd kiss_cmd;
  1333. struct scc_mem_config memcfg;
  1334. struct scc_hw_config hwcfg;
  1335. struct scc_calibrate cal;
  1336. struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
  1337. int chan;
  1338. unsigned char device_name[IFNAMSIZ];
  1339. void __user *arg = ifr->ifr_data;
  1340. if (!Driver_Initialized)
  1341. {
  1342. if (cmd == SIOCSCCCFG)
  1343. {
  1344. int found = 1;
  1345. if (!capable(CAP_SYS_RAWIO)) return -EPERM;
  1346. if (!arg) return -EFAULT;
  1347. if (Nchips >= SCC_MAXCHIPS)
  1348. return -EINVAL;
  1349. if (copy_from_user(&hwcfg, arg, sizeof(hwcfg)))
  1350. return -EFAULT;
  1351. if (hwcfg.irq == 2) hwcfg.irq = 9;
  1352. if (hwcfg.irq < 0 || hwcfg.irq >= nr_irqs)
  1353. return -EINVAL;
  1354. if (!Ivec[hwcfg.irq].used && hwcfg.irq)
  1355. {
  1356. if (request_irq(hwcfg.irq, scc_isr,
  1357. 0, "AX.25 SCC",
  1358. (void *)(long) hwcfg.irq))
  1359. printk(KERN_WARNING "z8530drv: warning, cannot get IRQ %d\n", hwcfg.irq);
  1360. else
  1361. Ivec[hwcfg.irq].used = 1;
  1362. }
  1363. if (hwcfg.vector_latch && !Vector_Latch) {
  1364. if (!request_region(hwcfg.vector_latch, 1, "scc vector latch"))
  1365. printk(KERN_WARNING "z8530drv: warning, cannot reserve vector latch port 0x%lx\n, disabled.", hwcfg.vector_latch);
  1366. else
  1367. Vector_Latch = hwcfg.vector_latch;
  1368. }
  1369. if (hwcfg.clock == 0)
  1370. hwcfg.clock = SCC_DEFAULT_CLOCK;
  1371. #ifndef SCC_DONT_CHECK
  1372. if(request_region(hwcfg.ctrl_a, 1, "scc-probe"))
  1373. {
  1374. disable_irq(hwcfg.irq);
  1375. Outb(hwcfg.ctrl_a, 0);
  1376. OutReg(hwcfg.ctrl_a, R9, FHWRES);
  1377. udelay(100);
  1378. OutReg(hwcfg.ctrl_a,R13,0x55); /* is this chip really there? */
  1379. udelay(5);
  1380. if (InReg(hwcfg.ctrl_a,R13) != 0x55)
  1381. found = 0;
  1382. enable_irq(hwcfg.irq);
  1383. release_region(hwcfg.ctrl_a, 1);
  1384. }
  1385. else
  1386. found = 0;
  1387. #endif
  1388. if (found)
  1389. {
  1390. SCC_Info[2*Nchips ].ctrl = hwcfg.ctrl_a;
  1391. SCC_Info[2*Nchips ].data = hwcfg.data_a;
  1392. SCC_Info[2*Nchips ].irq = hwcfg.irq;
  1393. SCC_Info[2*Nchips+1].ctrl = hwcfg.ctrl_b;
  1394. SCC_Info[2*Nchips+1].data = hwcfg.data_b;
  1395. SCC_Info[2*Nchips+1].irq = hwcfg.irq;
  1396. SCC_ctrl[Nchips].chan_A = hwcfg.ctrl_a;
  1397. SCC_ctrl[Nchips].chan_B = hwcfg.ctrl_b;
  1398. SCC_ctrl[Nchips].irq = hwcfg.irq;
  1399. }
  1400. for (chan = 0; chan < 2; chan++)
  1401. {
  1402. sprintf(device_name, "%s%i", SCC_DriverName, 2*Nchips+chan);
  1403. SCC_Info[2*Nchips+chan].special = hwcfg.special;
  1404. SCC_Info[2*Nchips+chan].clock = hwcfg.clock;
  1405. SCC_Info[2*Nchips+chan].brand = hwcfg.brand;
  1406. SCC_Info[2*Nchips+chan].option = hwcfg.option;
  1407. SCC_Info[2*Nchips+chan].enhanced = hwcfg.escc;
  1408. #ifdef SCC_DONT_CHECK
  1409. printk(KERN_INFO "%s: data port = 0x%3.3x control port = 0x%3.3x\n",
  1410. device_name,
  1411. SCC_Info[2*Nchips+chan].data,
  1412. SCC_Info[2*Nchips+chan].ctrl);
  1413. #else
  1414. printk(KERN_INFO "%s: data port = 0x%3.3lx control port = 0x%3.3lx -- %s\n",
  1415. device_name,
  1416. chan? hwcfg.data_b : hwcfg.data_a,
  1417. chan? hwcfg.ctrl_b : hwcfg.ctrl_a,
  1418. found? "found" : "missing");
  1419. #endif
  1420. if (found)
  1421. {
  1422. request_region(SCC_Info[2*Nchips+chan].ctrl, 1, "scc ctrl");
  1423. request_region(SCC_Info[2*Nchips+chan].data, 1, "scc data");
  1424. if (Nchips+chan != 0 &&
  1425. scc_net_alloc(device_name,
  1426. &SCC_Info[2*Nchips+chan]))
  1427. return -EINVAL;
  1428. }
  1429. }
  1430. if (found) Nchips++;
  1431. return 0;
  1432. }
  1433. if (cmd == SIOCSCCINI)
  1434. {
  1435. if (!capable(CAP_SYS_RAWIO))
  1436. return -EPERM;
  1437. if (Nchips == 0)
  1438. return -EINVAL;
  1439. z8530_init();
  1440. return 0;
  1441. }
  1442. return -EINVAL; /* confuse the user */
  1443. }
  1444. if (!scc->init)
  1445. {
  1446. if (cmd == SIOCSCCCHANINI)
  1447. {
  1448. if (!capable(CAP_NET_ADMIN)) return -EPERM;
  1449. if (!arg) return -EINVAL;
  1450. scc->stat.bufsize = SCC_BUFSIZE;
  1451. if (copy_from_user(&scc->modem, arg, sizeof(struct scc_modem)))
  1452. return -EINVAL;
  1453. /* default KISS Params */
  1454. if (scc->modem.speed < 4800)
  1455. {
  1456. scc->kiss.txdelay = 36; /* 360 ms */
  1457. scc->kiss.persist = 42; /* 25% persistence */ /* was 25 */
  1458. scc->kiss.slottime = 16; /* 160 ms */
  1459. scc->kiss.tailtime = 4; /* minimal reasonable value */
  1460. scc->kiss.fulldup = 0; /* CSMA */
  1461. scc->kiss.waittime = 50; /* 500 ms */
  1462. scc->kiss.maxkeyup = 10; /* 10 s */
  1463. scc->kiss.mintime = 3; /* 3 s */
  1464. scc->kiss.idletime = 30; /* 30 s */
  1465. scc->kiss.maxdefer = 120; /* 2 min */
  1466. scc->kiss.softdcd = 0; /* hardware dcd */
  1467. } else {
  1468. scc->kiss.txdelay = 10; /* 100 ms */
  1469. scc->kiss.persist = 64; /* 25% persistence */ /* was 25 */
  1470. scc->kiss.slottime = 8; /* 160 ms */
  1471. scc->kiss.tailtime = 1; /* minimal reasonable value */
  1472. scc->kiss.fulldup = 0; /* CSMA */
  1473. scc->kiss.waittime = 50; /* 500 ms */
  1474. scc->kiss.maxkeyup = 7; /* 7 s */
  1475. scc->kiss.mintime = 3; /* 3 s */
  1476. scc->kiss.idletime = 30; /* 30 s */
  1477. scc->kiss.maxdefer = 120; /* 2 min */
  1478. scc->kiss.softdcd = 0; /* hardware dcd */
  1479. }
  1480. scc->tx_buff = NULL;
  1481. skb_queue_head_init(&scc->tx_queue);
  1482. scc->init = 1;
  1483. return 0;
  1484. }
  1485. return -EINVAL;
  1486. }
  1487. switch(cmd)
  1488. {
  1489. case SIOCSCCRESERVED:
  1490. return -ENOIOCTLCMD;
  1491. case SIOCSCCSMEM:
  1492. if (!capable(CAP_SYS_RAWIO)) return -EPERM;
  1493. if (!arg || copy_from_user(&memcfg, arg, sizeof(memcfg)))
  1494. return -EINVAL;
  1495. scc->stat.bufsize = memcfg.bufsize;
  1496. return 0;
  1497. case SIOCSCCGSTAT:
  1498. if (!arg || copy_to_user(arg, &scc->stat, sizeof(scc->stat)))
  1499. return -EINVAL;
  1500. return 0;
  1501. case SIOCSCCGKISS:
  1502. if (!arg || copy_from_user(&kiss_cmd, arg, sizeof(kiss_cmd)))
  1503. return -EINVAL;
  1504. kiss_cmd.param = scc_get_param(scc, kiss_cmd.command);
  1505. if (copy_to_user(arg, &kiss_cmd, sizeof(kiss_cmd)))
  1506. return -EINVAL;
  1507. return 0;
  1508. case SIOCSCCSKISS:
  1509. if (!capable(CAP_NET_ADMIN)) return -EPERM;
  1510. if (!arg || copy_from_user(&kiss_cmd, arg, sizeof(kiss_cmd)))
  1511. return -EINVAL;
  1512. return scc_set_param(scc, kiss_cmd.command, kiss_cmd.param);
  1513. case SIOCSCCCAL:
  1514. if (!capable(CAP_SYS_RAWIO)) return -EPERM;
  1515. if (!arg || copy_from_user(&cal, arg, sizeof(cal)) || cal.time == 0)
  1516. return -EINVAL;
  1517. scc_start_calibrate(scc, cal.time, cal.pattern);
  1518. return 0;
  1519. default:
  1520. return -ENOIOCTLCMD;
  1521. }
  1522. return -EINVAL;
  1523. }
  1524. /* ----> set interface callsign <---- */
  1525. static int scc_net_set_mac_address(struct net_device *dev, void *addr)
  1526. {
  1527. struct sockaddr *sa = (struct sockaddr *) addr;
  1528. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  1529. return 0;
  1530. }
  1531. /* ----> get statistics <---- */
  1532. static struct net_device_stats *scc_net_get_stats(struct net_device *dev)
  1533. {
  1534. struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
  1535. scc->dev_stat.rx_errors = scc->stat.rxerrs + scc->stat.rx_over;
  1536. scc->dev_stat.tx_errors = scc->stat.txerrs + scc->stat.tx_under;
  1537. scc->dev_stat.rx_fifo_errors = scc->stat.rx_over;
  1538. scc->dev_stat.tx_fifo_errors = scc->stat.tx_under;
  1539. return &scc->dev_stat;
  1540. }
  1541. /* ******************************************************************** */
  1542. /* * dump statistics to /proc/net/z8530drv * */
  1543. /* ******************************************************************** */
  1544. #ifdef CONFIG_PROC_FS
  1545. static inline struct scc_channel *scc_net_seq_idx(loff_t pos)
  1546. {
  1547. int k;
  1548. for (k = 0; k < Nchips*2; ++k) {
  1549. if (!SCC_Info[k].init)
  1550. continue;
  1551. if (pos-- == 0)
  1552. return &SCC_Info[k];
  1553. }
  1554. return NULL;
  1555. }
  1556. static void *scc_net_seq_start(struct seq_file *seq, loff_t *pos)
  1557. {
  1558. return *pos ? scc_net_seq_idx(*pos - 1) : SEQ_START_TOKEN;
  1559. }
  1560. static void *scc_net_seq_next(struct seq_file *seq, void *v, loff_t *pos)
  1561. {
  1562. unsigned k;
  1563. struct scc_channel *scc = v;
  1564. ++*pos;
  1565. for (k = (v == SEQ_START_TOKEN) ? 0 : (scc - SCC_Info)+1;
  1566. k < Nchips*2; ++k) {
  1567. if (SCC_Info[k].init)
  1568. return &SCC_Info[k];
  1569. }
  1570. return NULL;
  1571. }
  1572. static void scc_net_seq_stop(struct seq_file *seq, void *v)
  1573. {
  1574. }
  1575. static int scc_net_seq_show(struct seq_file *seq, void *v)
  1576. {
  1577. if (v == SEQ_START_TOKEN) {
  1578. seq_puts(seq, "z8530drv-"VERSION"\n");
  1579. } else if (!Driver_Initialized) {
  1580. seq_puts(seq, "not initialized\n");
  1581. } else if (!Nchips) {
  1582. seq_puts(seq, "chips missing\n");
  1583. } else {
  1584. const struct scc_channel *scc = v;
  1585. const struct scc_stat *stat = &scc->stat;
  1586. const struct scc_kiss *kiss = &scc->kiss;
  1587. /* dev data ctrl irq clock brand enh vector special option
  1588. * baud nrz clocksrc softdcd bufsize
  1589. * rxints txints exints spints
  1590. * rcvd rxerrs over / xmit txerrs under / nospace bufsize
  1591. * txd pers slot tail ful wait min maxk idl defr txof grp
  1592. * W ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
  1593. * R ## ## XX ## ## ## ## ## XX ## ## ## ## ## ## ##
  1594. */
  1595. seq_printf(seq, "%s\t%3.3lx %3.3lx %d %lu %2.2x %d %3.3lx %3.3lx %d\n",
  1596. scc->dev->name,
  1597. scc->data, scc->ctrl, scc->irq, scc->clock, scc->brand,
  1598. scc->enhanced, Vector_Latch, scc->special,
  1599. scc->option);
  1600. seq_printf(seq, "\t%lu %d %d %d %d\n",
  1601. scc->modem.speed, scc->modem.nrz,
  1602. scc->modem.clocksrc, kiss->softdcd,
  1603. stat->bufsize);
  1604. seq_printf(seq, "\t%lu %lu %lu %lu\n",
  1605. stat->rxints, stat->txints, stat->exints, stat->spints);
  1606. seq_printf(seq, "\t%lu %lu %d / %lu %lu %d / %d %d\n",
  1607. stat->rxframes, stat->rxerrs, stat->rx_over,
  1608. stat->txframes, stat->txerrs, stat->tx_under,
  1609. stat->nospace, stat->tx_state);
  1610. #define K(x) kiss->x
  1611. seq_printf(seq, "\t%d %d %d %d %d %d %d %d %d %d %d %d\n",
  1612. K(txdelay), K(persist), K(slottime), K(tailtime),
  1613. K(fulldup), K(waittime), K(mintime), K(maxkeyup),
  1614. K(idletime), K(maxdefer), K(tx_inhibit), K(group));
  1615. #undef K
  1616. #ifdef SCC_DEBUG
  1617. {
  1618. int reg;
  1619. seq_printf(seq, "\tW ");
  1620. for (reg = 0; reg < 16; reg++)
  1621. seq_printf(seq, "%2.2x ", scc->wreg[reg]);
  1622. seq_printf(seq, "\n");
  1623. seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1));
  1624. for (reg = 3; reg < 8; reg++)
  1625. seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));
  1626. seq_printf(seq, "XX ");
  1627. for (reg = 9; reg < 16; reg++)
  1628. seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));
  1629. seq_printf(seq, "\n");
  1630. }
  1631. #endif
  1632. seq_putc(seq, '\n');
  1633. }
  1634. return 0;
  1635. }
  1636. static const struct seq_operations scc_net_seq_ops = {
  1637. .start = scc_net_seq_start,
  1638. .next = scc_net_seq_next,
  1639. .stop = scc_net_seq_stop,
  1640. .show = scc_net_seq_show,
  1641. };
  1642. static int scc_net_seq_open(struct inode *inode, struct file *file)
  1643. {
  1644. return seq_open(file, &scc_net_seq_ops);
  1645. }
  1646. static const struct file_operations scc_net_seq_fops = {
  1647. .owner = THIS_MODULE,
  1648. .open = scc_net_seq_open,
  1649. .read = seq_read,
  1650. .llseek = seq_lseek,
  1651. .release = seq_release_private,
  1652. };
  1653. #endif /* CONFIG_PROC_FS */
  1654. /* ******************************************************************** */
  1655. /* * Init SCC driver * */
  1656. /* ******************************************************************** */
  1657. static int __init scc_init_driver (void)
  1658. {
  1659. char devname[IFNAMSIZ];
  1660. printk(banner);
  1661. sprintf(devname,"%s0", SCC_DriverName);
  1662. rtnl_lock();
  1663. if (scc_net_alloc(devname, SCC_Info)) {
  1664. rtnl_unlock();
  1665. printk(KERN_ERR "z8530drv: cannot initialize module\n");
  1666. return -EIO;
  1667. }
  1668. rtnl_unlock();
  1669. proc_create("z8530drv", 0, init_net.proc_net, &scc_net_seq_fops);
  1670. return 0;
  1671. }
  1672. static void __exit scc_cleanup_driver(void)
  1673. {
  1674. io_port ctrl;
  1675. int k;
  1676. struct scc_channel *scc;
  1677. struct net_device *dev;
  1678. if (Nchips == 0 && (dev = SCC_Info[0].dev))
  1679. {
  1680. unregister_netdev(dev);
  1681. free_netdev(dev);
  1682. }
  1683. /* Guard against chip prattle */
  1684. local_irq_disable();
  1685. for (k = 0; k < Nchips; k++)
  1686. if ( (ctrl = SCC_ctrl[k].chan_A) )
  1687. {
  1688. Outb(ctrl, 0);
  1689. OutReg(ctrl,R9,FHWRES); /* force hardware reset */
  1690. udelay(50);
  1691. }
  1692. /* To unload the port must be closed so no real IRQ pending */
  1693. for (k = 0; k < nr_irqs ; k++)
  1694. if (Ivec[k].used) free_irq(k, NULL);
  1695. local_irq_enable();
  1696. /* Now clean up */
  1697. for (k = 0; k < Nchips*2; k++)
  1698. {
  1699. scc = &SCC_Info[k];
  1700. if (scc->ctrl)
  1701. {
  1702. release_region(scc->ctrl, 1);
  1703. release_region(scc->data, 1);
  1704. }
  1705. if (scc->dev)
  1706. {
  1707. unregister_netdev(scc->dev);
  1708. free_netdev(scc->dev);
  1709. }
  1710. }
  1711. if (Vector_Latch)
  1712. release_region(Vector_Latch, 1);
  1713. remove_proc_entry("z8530drv", init_net.proc_net);
  1714. }
  1715. MODULE_AUTHOR("Joerg Reuter <jreuter@yaina.de>");
  1716. MODULE_DESCRIPTION("AX.25 Device Driver for Z8530 based HDLC cards");
  1717. MODULE_SUPPORTED_DEVICE("Z8530 based SCC cards for Amateur Radio");
  1718. MODULE_LICENSE("GPL");
  1719. module_init(scc_init_driver);
  1720. module_exit(scc_cleanup_driver);