spider_net.h 15 KB

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  1. /*
  2. * Network device driver for Cell Processor-Based Blade and Celleb platform
  3. *
  4. * (C) Copyright IBM Corp. 2005
  5. * (C) Copyright 2006 TOSHIBA CORPORATION
  6. *
  7. * Authors : Utz Bacher <utz.bacher@de.ibm.com>
  8. * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2, or (at your option)
  13. * any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #ifndef _SPIDER_NET_H
  25. #define _SPIDER_NET_H
  26. #define VERSION "2.0 B"
  27. #include <linux/sungem_phy.h>
  28. int spider_net_stop(struct net_device *netdev);
  29. int spider_net_open(struct net_device *netdev);
  30. extern const struct ethtool_ops spider_net_ethtool_ops;
  31. extern char spider_net_driver_name[];
  32. #define SPIDER_NET_MAX_FRAME 2312
  33. #define SPIDER_NET_MAX_MTU 2294
  34. #define SPIDER_NET_MIN_MTU 64
  35. #define SPIDER_NET_RXBUF_ALIGN 128
  36. #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
  37. #define SPIDER_NET_RX_DESCRIPTORS_MIN 16
  38. #define SPIDER_NET_RX_DESCRIPTORS_MAX 512
  39. #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
  40. #define SPIDER_NET_TX_DESCRIPTORS_MIN 16
  41. #define SPIDER_NET_TX_DESCRIPTORS_MAX 512
  42. #define SPIDER_NET_TX_TIMER (HZ/5)
  43. #define SPIDER_NET_ANEG_TIMER (HZ)
  44. #define SPIDER_NET_ANEG_TIMEOUT 5
  45. #define SPIDER_NET_RX_CSUM_DEFAULT 1
  46. #define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
  47. #define SPIDER_NET_NAPI_WEIGHT 64
  48. #define SPIDER_NET_FIRMWARE_SEQS 6
  49. #define SPIDER_NET_FIRMWARE_SEQWORDS 1024
  50. #define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
  51. SPIDER_NET_FIRMWARE_SEQWORDS * \
  52. sizeof(u32))
  53. #define SPIDER_NET_FIRMWARE_NAME "/*(DEBLOBBED)*/"
  54. /** spider_net SMMIO registers */
  55. #define SPIDER_NET_GHIINT0STS 0x00000000
  56. #define SPIDER_NET_GHIINT1STS 0x00000004
  57. #define SPIDER_NET_GHIINT2STS 0x00000008
  58. #define SPIDER_NET_GHIINT0MSK 0x00000010
  59. #define SPIDER_NET_GHIINT1MSK 0x00000014
  60. #define SPIDER_NET_GHIINT2MSK 0x00000018
  61. #define SPIDER_NET_GRESUMINTNUM 0x00000020
  62. #define SPIDER_NET_GREINTNUM 0x00000024
  63. #define SPIDER_NET_GFFRMNUM 0x00000028
  64. #define SPIDER_NET_GFAFRMNUM 0x0000002c
  65. #define SPIDER_NET_GFBFRMNUM 0x00000030
  66. #define SPIDER_NET_GFCFRMNUM 0x00000034
  67. #define SPIDER_NET_GFDFRMNUM 0x00000038
  68. /* clear them (don't use it) */
  69. #define SPIDER_NET_GFREECNNUM 0x0000003c
  70. #define SPIDER_NET_GONETIMENUM 0x00000040
  71. #define SPIDER_NET_GTOUTFRMNUM 0x00000044
  72. #define SPIDER_NET_GTXMDSET 0x00000050
  73. #define SPIDER_NET_GPCCTRL 0x00000054
  74. #define SPIDER_NET_GRXMDSET 0x00000058
  75. #define SPIDER_NET_GIPSECINIT 0x0000005c
  76. #define SPIDER_NET_GFTRESTRT 0x00000060
  77. #define SPIDER_NET_GRXDMAEN 0x00000064
  78. #define SPIDER_NET_GMRWOLCTRL 0x00000068
  79. #define SPIDER_NET_GPCWOPCMD 0x0000006c
  80. #define SPIDER_NET_GPCROPCMD 0x00000070
  81. #define SPIDER_NET_GTTFRMCNT 0x00000078
  82. #define SPIDER_NET_GTESTMD 0x0000007c
  83. #define SPIDER_NET_GSINIT 0x00000080
  84. #define SPIDER_NET_GSnPRGADR 0x00000084
  85. #define SPIDER_NET_GSnPRGDAT 0x00000088
  86. #define SPIDER_NET_GMACOPEMD 0x00000100
  87. #define SPIDER_NET_GMACLENLMT 0x00000108
  88. #define SPIDER_NET_GMACST 0x00000110
  89. #define SPIDER_NET_GMACINTEN 0x00000118
  90. #define SPIDER_NET_GMACPHYCTRL 0x00000120
  91. #define SPIDER_NET_GMACAPAUSE 0x00000154
  92. #define SPIDER_NET_GMACTXPAUSE 0x00000164
  93. #define SPIDER_NET_GMACMODE 0x000001b0
  94. #define SPIDER_NET_GMACBSTLMT 0x000001b4
  95. #define SPIDER_NET_GMACUNIMACU 0x000001c0
  96. #define SPIDER_NET_GMACUNIMACL 0x000001c8
  97. #define SPIDER_NET_GMRMHFILnR 0x00000400
  98. #define SPIDER_NET_MULTICAST_HASHES 256
  99. #define SPIDER_NET_GMRUAFILnR 0x00000500
  100. #define SPIDER_NET_GMRUA0FIL15R 0x00000578
  101. #define SPIDER_NET_GTTQMSK 0x00000934
  102. /* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
  103. * 0x00000b.. for DMA controller B, etc. */
  104. #define SPIDER_NET_GDADCHA 0x00000a00
  105. #define SPIDER_NET_GDADMACCNTR 0x00000a04
  106. #define SPIDER_NET_GDACTDPA 0x00000a08
  107. #define SPIDER_NET_GDACTDCNT 0x00000a0c
  108. #define SPIDER_NET_GDACDBADDR 0x00000a20
  109. #define SPIDER_NET_GDACDBSIZE 0x00000a24
  110. #define SPIDER_NET_GDACNEXTDA 0x00000a28
  111. #define SPIDER_NET_GDACCOMST 0x00000a2c
  112. #define SPIDER_NET_GDAWBCOMST 0x00000a30
  113. #define SPIDER_NET_GDAWBRSIZE 0x00000a34
  114. #define SPIDER_NET_GDAWBVSIZE 0x00000a38
  115. #define SPIDER_NET_GDAWBTRST 0x00000a3c
  116. #define SPIDER_NET_GDAWBTRERR 0x00000a40
  117. /* TX DMA controller registers */
  118. #define SPIDER_NET_GDTDCHA 0x00000e00
  119. #define SPIDER_NET_GDTDMACCNTR 0x00000e04
  120. #define SPIDER_NET_GDTCDPA 0x00000e08
  121. #define SPIDER_NET_GDTDMASEL 0x00000e14
  122. #define SPIDER_NET_ECMODE 0x00000f00
  123. /* clock and reset control register */
  124. #define SPIDER_NET_CKRCTRL 0x00000ff0
  125. /** SCONFIG registers */
  126. #define SPIDER_NET_SCONFIG_IOACTE 0x00002810
  127. /** interrupt mask registers */
  128. #define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
  129. #define SPIDER_NET_INT1_MASK_VALUE 0x0000fff2
  130. #define SPIDER_NET_INT2_MASK_VALUE 0x000003f1
  131. /* we rely on flagged descriptor interrupts */
  132. #define SPIDER_NET_FRAMENUM_VALUE 0x00000000
  133. /* set this first, then the FRAMENUM_VALUE */
  134. #define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
  135. #define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
  136. #define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
  137. #define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
  138. /* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
  139. #define SPIDER_NET_RXMODE_VALUE 0x00000011
  140. /* auto retransmission in case of MAC aborts */
  141. #define SPIDER_NET_TXMODE_VALUE 0x00010000
  142. #define SPIDER_NET_RESTART_VALUE 0x00000000
  143. #define SPIDER_NET_WOL_VALUE 0x00001111
  144. #if 0
  145. #define SPIDER_NET_WOL_VALUE 0x00000000
  146. #endif
  147. #define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
  148. /* pause frames: automatic, no upper retransmission count */
  149. /* outside loopback mode: ETOMOD signal dont matter, not connected */
  150. /* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */
  151. #define SPIDER_NET_OPMODE_VALUE 0x00000067
  152. /*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/
  153. #define SPIDER_NET_LENLMT_VALUE 0x00000908
  154. #define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
  155. #define SPIDER_NET_TXPAUSE_VALUE 0x00000000
  156. #define SPIDER_NET_MACMODE_VALUE 0x00000001
  157. #define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
  158. /* DMAC control register GDMACCNTR
  159. *
  160. * 1(0) enable r/tx dma
  161. * 0000000 fixed to 0
  162. *
  163. * 000000 fixed to 0
  164. * 0(1) en/disable descr writeback on force end
  165. * 0(1) force end
  166. *
  167. * 000000 fixed to 0
  168. * 00 burst alignment: 128 bytes
  169. * 11 burst alignment: 1024 bytes
  170. *
  171. * 00000 fixed to 0
  172. * 0 descr writeback size 32 bytes
  173. * 0(1) descr chain end interrupt enable
  174. * 0(1) descr status writeback enable */
  175. /* to set RX_DMA_EN */
  176. #define SPIDER_NET_DMA_RX_VALUE 0x80000000
  177. #define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
  178. /* to set TX_DMA_EN */
  179. #define SPIDER_NET_TX_DMA_EN 0x80000000
  180. #define SPIDER_NET_GDTBSTA 0x00000300
  181. #define SPIDER_NET_GDTDCEIDIS 0x00000002
  182. #define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \
  183. SPIDER_NET_GDTDCEIDIS | \
  184. SPIDER_NET_GDTBSTA
  185. #define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
  186. /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
  187. #define SPIDER_NET_UA_DESCR_VALUE 0x00080000
  188. #define SPIDER_NET_PROMISC_VALUE 0x00080000
  189. #define SPIDER_NET_NONPROMISC_VALUE 0x00000000
  190. #define SPIDER_NET_DMASEL_VALUE 0x00000001
  191. #define SPIDER_NET_ECMODE_VALUE 0x00000000
  192. #define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
  193. #define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
  194. #define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
  195. #define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
  196. /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
  197. * with 1 << SPIDER_NET_... */
  198. enum spider_net_int0_status {
  199. SPIDER_NET_GPHYINT = 0,
  200. SPIDER_NET_GMAC2INT,
  201. SPIDER_NET_GMAC1INT,
  202. SPIDER_NET_GIPSINT,
  203. SPIDER_NET_GFIFOINT,
  204. SPIDER_NET_GDMACINT,
  205. SPIDER_NET_GSYSINT,
  206. SPIDER_NET_GPWOPCMPINT,
  207. SPIDER_NET_GPROPCMPINT,
  208. SPIDER_NET_GPWFFINT,
  209. SPIDER_NET_GRMDADRINT,
  210. SPIDER_NET_GRMARPINT,
  211. SPIDER_NET_GRMMPINT,
  212. SPIDER_NET_GDTDEN0INT,
  213. SPIDER_NET_GDDDEN0INT,
  214. SPIDER_NET_GDCDEN0INT,
  215. SPIDER_NET_GDBDEN0INT,
  216. SPIDER_NET_GDADEN0INT,
  217. SPIDER_NET_GDTFDCINT,
  218. SPIDER_NET_GDDFDCINT,
  219. SPIDER_NET_GDCFDCINT,
  220. SPIDER_NET_GDBFDCINT,
  221. SPIDER_NET_GDAFDCINT,
  222. SPIDER_NET_GTTEDINT,
  223. SPIDER_NET_GDTDCEINT,
  224. SPIDER_NET_GRFDNMINT,
  225. SPIDER_NET_GRFCNMINT,
  226. SPIDER_NET_GRFBNMINT,
  227. SPIDER_NET_GRFANMINT,
  228. SPIDER_NET_GRFNMINT,
  229. SPIDER_NET_G1TMCNTINT,
  230. SPIDER_NET_GFREECNTINT
  231. };
  232. /* GHIINT1STS bits */
  233. enum spider_net_int1_status {
  234. SPIDER_NET_GTMFLLINT = 0,
  235. SPIDER_NET_GRMFLLINT,
  236. SPIDER_NET_GTMSHTINT,
  237. SPIDER_NET_GDTINVDINT,
  238. SPIDER_NET_GRFDFLLINT,
  239. SPIDER_NET_GDDDCEINT,
  240. SPIDER_NET_GDDINVDINT,
  241. SPIDER_NET_GRFCFLLINT,
  242. SPIDER_NET_GDCDCEINT,
  243. SPIDER_NET_GDCINVDINT,
  244. SPIDER_NET_GRFBFLLINT,
  245. SPIDER_NET_GDBDCEINT,
  246. SPIDER_NET_GDBINVDINT,
  247. SPIDER_NET_GRFAFLLINT,
  248. SPIDER_NET_GDADCEINT,
  249. SPIDER_NET_GDAINVDINT,
  250. SPIDER_NET_GDTRSERINT,
  251. SPIDER_NET_GDDRSERINT,
  252. SPIDER_NET_GDCRSERINT,
  253. SPIDER_NET_GDBRSERINT,
  254. SPIDER_NET_GDARSERINT,
  255. SPIDER_NET_GDSERINT,
  256. SPIDER_NET_GDTPTERINT,
  257. SPIDER_NET_GDDPTERINT,
  258. SPIDER_NET_GDCPTERINT,
  259. SPIDER_NET_GDBPTERINT,
  260. SPIDER_NET_GDAPTERINT
  261. };
  262. /* GHIINT2STS bits */
  263. enum spider_net_int2_status {
  264. SPIDER_NET_GPROPERINT = 0,
  265. SPIDER_NET_GMCTCRSNGINT,
  266. SPIDER_NET_GMCTLCOLINT,
  267. SPIDER_NET_GMCTTMOTINT,
  268. SPIDER_NET_GMCRCAERINT,
  269. SPIDER_NET_GMCRCALERINT,
  270. SPIDER_NET_GMCRALNERINT,
  271. SPIDER_NET_GMCROVRINT,
  272. SPIDER_NET_GMCRRNTINT,
  273. SPIDER_NET_GMCRRXERINT,
  274. SPIDER_NET_GTITCSERINT,
  275. SPIDER_NET_GTIFMTERINT,
  276. SPIDER_NET_GTIPKTRVKINT,
  277. SPIDER_NET_GTISPINGINT,
  278. SPIDER_NET_GTISADNGINT,
  279. SPIDER_NET_GTISPDNGINT,
  280. SPIDER_NET_GRIFMTERINT,
  281. SPIDER_NET_GRIPKTRVKINT,
  282. SPIDER_NET_GRISPINGINT,
  283. SPIDER_NET_GRISADNGINT,
  284. SPIDER_NET_GRISPDNGINT
  285. };
  286. #define SPIDER_NET_TXINT (1 << SPIDER_NET_GDTFDCINT)
  287. /* We rely on flagged descriptor interrupts */
  288. #define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )
  289. #define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT )
  290. #define SPIDER_NET_ERRINT ( 0xffffffff & \
  291. (~SPIDER_NET_TXINT) & \
  292. (~SPIDER_NET_RXINT) & \
  293. (~SPIDER_NET_LINKINT) )
  294. #define SPIDER_NET_GPREXEC 0x80000000
  295. #define SPIDER_NET_GPRDAT_MASK 0x0000ffff
  296. #define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
  297. #define SPIDER_NET_DMAC_TXFRMTL 0x00040000
  298. #define SPIDER_NET_DMAC_TCP 0x00020000
  299. #define SPIDER_NET_DMAC_UDP 0x00030000
  300. #define SPIDER_NET_TXDCEST 0x08000000
  301. #define SPIDER_NET_DESCR_RXFDIS 0x00000001
  302. #define SPIDER_NET_DESCR_RXDCEIS 0x00000002
  303. #define SPIDER_NET_DESCR_RXDEN0IS 0x00000004
  304. #define SPIDER_NET_DESCR_RXINVDIS 0x00000008
  305. #define SPIDER_NET_DESCR_RXRERRIS 0x00000010
  306. #define SPIDER_NET_DESCR_RXFDCIMS 0x00000100
  307. #define SPIDER_NET_DESCR_RXDCEIMS 0x00000200
  308. #define SPIDER_NET_DESCR_RXDEN0IMS 0x00000400
  309. #define SPIDER_NET_DESCR_RXINVDIMS 0x00000800
  310. #define SPIDER_NET_DESCR_RXRERRMIS 0x00001000
  311. #define SPIDER_NET_DESCR_UNUSED 0x077fe0e0
  312. #define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
  313. #define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
  314. #define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
  315. #define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
  316. #define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
  317. #define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
  318. #define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
  319. #define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
  320. #define SPIDER_NET_DESCR_TXDESFLG 0x00800000
  321. #define SPIDER_NET_DESCR_BAD_STATUS (SPIDER_NET_DESCR_RXDEN0IS | \
  322. SPIDER_NET_DESCR_RXRERRIS | \
  323. SPIDER_NET_DESCR_RXDEN0IMS | \
  324. SPIDER_NET_DESCR_RXINVDIMS | \
  325. SPIDER_NET_DESCR_RXRERRMIS | \
  326. SPIDER_NET_DESCR_UNUSED)
  327. /* Descriptor, as defined by the hardware */
  328. struct spider_net_hw_descr {
  329. u32 buf_addr;
  330. u32 buf_size;
  331. u32 next_descr_addr;
  332. u32 dmac_cmd_status;
  333. u32 result_size;
  334. u32 valid_size; /* all zeroes for tx */
  335. u32 data_status;
  336. u32 data_error; /* all zeroes for tx */
  337. } __attribute__((aligned(32)));
  338. struct spider_net_descr {
  339. struct spider_net_hw_descr *hwdescr;
  340. struct sk_buff *skb;
  341. u32 bus_addr;
  342. struct spider_net_descr *next;
  343. struct spider_net_descr *prev;
  344. };
  345. struct spider_net_descr_chain {
  346. spinlock_t lock;
  347. struct spider_net_descr *head;
  348. struct spider_net_descr *tail;
  349. struct spider_net_descr *ring;
  350. int num_desc;
  351. struct spider_net_hw_descr *hwring;
  352. dma_addr_t dma_addr;
  353. };
  354. /* descriptor data_status bits */
  355. #define SPIDER_NET_RX_IPCHK 29
  356. #define SPIDER_NET_RX_TCPCHK 28
  357. #define SPIDER_NET_VLAN_PACKET 21
  358. #define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
  359. (1 << SPIDER_NET_RX_TCPCHK) )
  360. /* descriptor data_error bits */
  361. #define SPIDER_NET_RX_IPCHKERR 27
  362. #define SPIDER_NET_RX_RXTCPCHKERR 28
  363. #define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
  364. /* the cases we don't pass the packet to the stack.
  365. * 701b8000 would be correct, but every packets gets that flag */
  366. #define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
  367. #define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \
  368. NETIF_MSG_PROBE | \
  369. NETIF_MSG_LINK | \
  370. NETIF_MSG_TIMER | \
  371. NETIF_MSG_IFDOWN | \
  372. NETIF_MSG_IFUP | \
  373. NETIF_MSG_RX_ERR | \
  374. NETIF_MSG_TX_ERR | \
  375. NETIF_MSG_TX_QUEUED | \
  376. NETIF_MSG_INTR | \
  377. NETIF_MSG_TX_DONE | \
  378. NETIF_MSG_RX_STATUS | \
  379. NETIF_MSG_PKTDATA | \
  380. NETIF_MSG_HW | \
  381. NETIF_MSG_WOL )
  382. struct spider_net_extra_stats {
  383. unsigned long rx_desc_error;
  384. unsigned long tx_timeouts;
  385. unsigned long alloc_rx_skb_error;
  386. unsigned long rx_iommu_map_error;
  387. unsigned long tx_iommu_map_error;
  388. unsigned long rx_desc_unk_state;
  389. };
  390. struct spider_net_card {
  391. struct net_device *netdev;
  392. struct pci_dev *pdev;
  393. struct mii_phy phy;
  394. struct napi_struct napi;
  395. int medium;
  396. void __iomem *regs;
  397. struct spider_net_descr_chain tx_chain;
  398. struct spider_net_descr_chain rx_chain;
  399. struct spider_net_descr *low_watermark;
  400. int aneg_count;
  401. struct timer_list aneg_timer;
  402. struct timer_list tx_timer;
  403. struct work_struct tx_timeout_task;
  404. atomic_t tx_timeout_task_counter;
  405. wait_queue_head_t waitq;
  406. int num_rx_ints;
  407. int ignore_rx_ramfull;
  408. /* for ethtool */
  409. int msg_enable;
  410. struct spider_net_extra_stats spider_stats;
  411. /* Must be last item in struct */
  412. struct spider_net_descr darray[0];
  413. };
  414. #endif