ps3_gelic_net.h 12 KB

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  1. /*
  2. * PS3 Platfom gelic network driver.
  3. *
  4. * Copyright (C) 2007 Sony Computer Entertainment Inc.
  5. * Copyright 2006, 2007 Sony Corporation.
  6. *
  7. * This file is based on: spider_net.h
  8. *
  9. * (C) Copyright IBM Corp. 2005
  10. *
  11. * Authors : Utz Bacher <utz.bacher@de.ibm.com>
  12. * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2, or (at your option)
  17. * any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  27. */
  28. #ifndef _GELIC_NET_H
  29. #define _GELIC_NET_H
  30. /* descriptors */
  31. #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */
  32. #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */
  33. #define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN
  34. #define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN
  35. #define GELIC_NET_RXBUF_ALIGN 128
  36. #define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */
  37. #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
  38. #define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
  39. #define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
  40. /* virtual interrupt status register bits */
  41. /* INT1 */
  42. #define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
  43. #define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
  44. #define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
  45. #define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
  46. #define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
  47. #define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
  48. #define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
  49. #define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
  50. #define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
  51. #define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
  52. #define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
  53. #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
  54. #define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
  55. #define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L
  56. #define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L
  57. /* INT 0 */
  58. #define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
  59. #define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
  60. #define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
  61. #define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
  62. #define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
  63. #define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
  64. #define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
  65. /* initial interrupt mask */
  66. #define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
  67. #define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
  68. GELIC_CARD_NUMBER_OF_RX_FRAME)
  69. /* RX descriptor data_status bits */
  70. enum gelic_descr_rx_status {
  71. GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
  72. GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
  73. GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
  74. GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
  75. GELIC_DESCR_RXWTPKT = 0x00C00000, /*
  76. * wakeup trigger packet
  77. * 01: Magic Packet (TM)
  78. * 10: ARP packet
  79. * 11: Multicast MAC addr
  80. */
  81. GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
  82. /* bit 20..16 reserved */
  83. GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
  84. /* bit 7..0 reserved */
  85. };
  86. #define GELIC_DESCR_DATA_STATUS_CHK_MASK \
  87. (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
  88. /* TX descriptor data_status bits */
  89. enum gelic_descr_tx_status {
  90. GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
  91. * descriptor was end of
  92. * a tx frame
  93. */
  94. };
  95. /* RX descriptor data error bits */
  96. enum gelic_descr_rx_error {
  97. /* bit 31 reserved */
  98. GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
  99. GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
  100. GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
  101. GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
  102. GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
  103. GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
  104. GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
  105. /* bit 18 reserved */
  106. GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
  107. GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
  108. * error */
  109. GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extension error */
  110. GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
  111. /* bit 13..0 reserved */
  112. };
  113. #define GELIC_DESCR_DATA_ERROR_CHK_MASK \
  114. (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
  115. /* DMA command and status (RX and TX)*/
  116. enum gelic_descr_dma_status {
  117. GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
  118. GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
  119. GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
  120. GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
  121. GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
  122. GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
  123. GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
  124. GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
  125. };
  126. #define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
  127. /* tx descriptor command and status */
  128. enum gelic_descr_tx_dma_status {
  129. /* [19] */
  130. GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
  131. /* [18] */
  132. GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
  133. * the packet
  134. */
  135. /* [17..16] */
  136. GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
  137. GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
  138. GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
  139. /* [1] */
  140. GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
  141. * due to chain end
  142. */
  143. };
  144. #define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
  145. (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
  146. GELIC_DESCR_TX_DMA_NO_CHKSUM)
  147. #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
  148. (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
  149. GELIC_DESCR_TX_DMA_TCP_CHKSUM)
  150. #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
  151. (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
  152. GELIC_DESCR_TX_DMA_UDP_CHKSUM)
  153. enum gelic_descr_rx_dma_status {
  154. /* [ 1 ] */
  155. GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
  156. * due to chain end
  157. */
  158. };
  159. /* for lv1_net_control */
  160. enum gelic_lv1_net_control_code {
  161. GELIC_LV1_GET_MAC_ADDRESS = 1,
  162. GELIC_LV1_GET_ETH_PORT_STATUS = 2,
  163. GELIC_LV1_SET_NEGOTIATION_MODE = 3,
  164. GELIC_LV1_GET_VLAN_ID = 4,
  165. GELIC_LV1_SET_WOL = 5,
  166. GELIC_LV1_GET_CHANNEL = 6,
  167. GELIC_LV1_POST_WLAN_CMD = 9,
  168. GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
  169. GELIC_LV1_GET_WLAN_EVENT = 11,
  170. };
  171. /* for GELIC_LV1_SET_WOL */
  172. enum gelic_lv1_wol_command {
  173. GELIC_LV1_WOL_MAGIC_PACKET = 1,
  174. GELIC_LV1_WOL_ADD_MATCH_ADDR = 6,
  175. GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
  176. };
  177. /* for GELIC_LV1_WOL_MAGIC_PACKET */
  178. enum gelic_lv1_wol_mp_arg {
  179. GELIC_LV1_WOL_MP_DISABLE = 0,
  180. GELIC_LV1_WOL_MP_ENABLE = 1,
  181. };
  182. /* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
  183. enum gelic_lv1_wol_match_arg {
  184. GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0,
  185. GELIC_LV1_WOL_MATCH_ALL = 1,
  186. };
  187. /* status returened from GET_ETH_PORT_STATUS */
  188. enum gelic_lv1_ether_port_status {
  189. GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
  190. GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
  191. GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
  192. GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
  193. GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
  194. GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
  195. GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L,
  196. };
  197. enum gelic_lv1_vlan_index {
  198. /* for outgoing packets */
  199. GELIC_LV1_VLAN_TX_ETHERNET_0 = 0x0000000000000002L,
  200. GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
  201. /* for incoming packets */
  202. GELIC_LV1_VLAN_RX_ETHERNET_0 = 0x0000000000000012L,
  203. GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L,
  204. };
  205. enum gelic_lv1_phy {
  206. GELIC_LV1_PHY_ETHERNET_0 = 0x0000000000000002L,
  207. };
  208. /* size of hardware part of gelic descriptor */
  209. #define GELIC_DESCR_SIZE (32)
  210. enum gelic_port_type {
  211. GELIC_PORT_ETHERNET_0 = 0,
  212. GELIC_PORT_WIRELESS = 1,
  213. GELIC_PORT_MAX
  214. };
  215. struct gelic_descr {
  216. /* as defined by the hardware */
  217. __be32 buf_addr;
  218. __be32 buf_size;
  219. __be32 next_descr_addr;
  220. __be32 dmac_cmd_status;
  221. __be32 result_size;
  222. __be32 valid_size; /* all zeroes for tx */
  223. __be32 data_status;
  224. __be32 data_error; /* all zeroes for tx */
  225. /* used in the driver */
  226. struct sk_buff *skb;
  227. dma_addr_t bus_addr;
  228. struct gelic_descr *next;
  229. struct gelic_descr *prev;
  230. } __attribute__((aligned(32)));
  231. struct gelic_descr_chain {
  232. /* we walk from tail to head */
  233. struct gelic_descr *head;
  234. struct gelic_descr *tail;
  235. };
  236. struct gelic_vlan_id {
  237. u16 tx;
  238. u16 rx;
  239. };
  240. struct gelic_card {
  241. struct napi_struct napi;
  242. struct net_device *netdev[GELIC_PORT_MAX];
  243. /*
  244. * hypervisor requires irq_status should be
  245. * 8 bytes aligned, but u64 member is
  246. * always disposed in that manner
  247. */
  248. u64 irq_status;
  249. u64 irq_mask;
  250. struct ps3_system_bus_device *dev;
  251. struct gelic_vlan_id vlan[GELIC_PORT_MAX];
  252. int vlan_required;
  253. struct gelic_descr_chain tx_chain;
  254. struct gelic_descr_chain rx_chain;
  255. /*
  256. * tx_lock guards tx descriptor list and
  257. * tx_dma_progress.
  258. */
  259. spinlock_t tx_lock;
  260. int tx_dma_progress;
  261. struct work_struct tx_timeout_task;
  262. atomic_t tx_timeout_task_counter;
  263. wait_queue_head_t waitq;
  264. /* only first user should up the card */
  265. struct mutex updown_lock;
  266. atomic_t users;
  267. u64 ether_port_status;
  268. int link_mode;
  269. /* original address returned by kzalloc */
  270. void *unalign;
  271. /*
  272. * each netdevice has copy of irq
  273. */
  274. unsigned int irq;
  275. struct gelic_descr *tx_top, *rx_top;
  276. struct gelic_descr descr[0]; /* must be the last */
  277. };
  278. struct gelic_port {
  279. struct gelic_card *card;
  280. struct net_device *netdev;
  281. enum gelic_port_type type;
  282. long priv[0]; /* long for alignment */
  283. };
  284. static inline struct gelic_card *port_to_card(struct gelic_port *p)
  285. {
  286. return p->card;
  287. }
  288. static inline struct net_device *port_to_netdev(struct gelic_port *p)
  289. {
  290. return p->netdev;
  291. }
  292. static inline struct gelic_card *netdev_card(struct net_device *d)
  293. {
  294. return ((struct gelic_port *)netdev_priv(d))->card;
  295. }
  296. static inline struct gelic_port *netdev_port(struct net_device *d)
  297. {
  298. return (struct gelic_port *)netdev_priv(d);
  299. }
  300. static inline struct device *ctodev(struct gelic_card *card)
  301. {
  302. return &card->dev->core;
  303. }
  304. static inline u64 bus_id(struct gelic_card *card)
  305. {
  306. return card->dev->bus_id;
  307. }
  308. static inline u64 dev_id(struct gelic_card *card)
  309. {
  310. return card->dev->dev_id;
  311. }
  312. static inline void *port_priv(struct gelic_port *port)
  313. {
  314. return port->priv;
  315. }
  316. #ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
  317. void udbg_shutdown_ps3gelic(void);
  318. #else
  319. static inline void udbg_shutdown_ps3gelic(void) {}
  320. #endif
  321. int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
  322. /* shared netdev ops */
  323. void gelic_card_up(struct gelic_card *card);
  324. void gelic_card_down(struct gelic_card *card);
  325. int gelic_net_open(struct net_device *netdev);
  326. int gelic_net_stop(struct net_device *netdev);
  327. int gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
  328. void gelic_net_set_multi(struct net_device *netdev);
  329. void gelic_net_tx_timeout(struct net_device *netdev);
  330. int gelic_net_change_mtu(struct net_device *netdev, int new_mtu);
  331. int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card);
  332. /* shared ethtool ops */
  333. void gelic_net_get_drvinfo(struct net_device *netdev,
  334. struct ethtool_drvinfo *info);
  335. void gelic_net_poll_controller(struct net_device *netdev);
  336. #endif /* _GELIC_NET_H */