qca_spi.c 24 KB

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  1. /*
  2. * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
  3. * Copyright (c) 2014, I2SE GmbH
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software
  6. * for any purpose with or without fee is hereby granted, provided
  7. * that the above copyright notice and this permission notice appear
  8. * in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
  13. * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
  14. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  15. * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
  16. * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. /* This module implements the Qualcomm Atheros SPI protocol for
  20. * kernel-based SPI device; it is essentially an Ethernet-to-SPI
  21. * serial converter;
  22. */
  23. #include <linux/errno.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/if_arp.h>
  26. #include <linux/if_ether.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/jiffies.h>
  30. #include <linux/kernel.h>
  31. #include <linux/kthread.h>
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/of.h>
  36. #include <linux/of_device.h>
  37. #include <linux/of_net.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/spi/spi.h>
  41. #include <linux/types.h>
  42. #include "qca_7k.h"
  43. #include "qca_debug.h"
  44. #include "qca_framing.h"
  45. #include "qca_spi.h"
  46. #define MAX_DMA_BURST_LEN 5000
  47. /* Modules parameters */
  48. #define QCASPI_CLK_SPEED_MIN 1000000
  49. #define QCASPI_CLK_SPEED_MAX 16000000
  50. #define QCASPI_CLK_SPEED 8000000
  51. static int qcaspi_clkspeed;
  52. module_param(qcaspi_clkspeed, int, 0);
  53. MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
  54. #define QCASPI_BURST_LEN_MIN 1
  55. #define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
  56. static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
  57. module_param(qcaspi_burst_len, int, 0);
  58. MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
  59. #define QCASPI_PLUGGABLE_MIN 0
  60. #define QCASPI_PLUGGABLE_MAX 1
  61. static int qcaspi_pluggable = QCASPI_PLUGGABLE_MIN;
  62. module_param(qcaspi_pluggable, int, 0);
  63. MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
  64. #define QCASPI_MTU QCAFRM_ETHMAXMTU
  65. #define QCASPI_TX_TIMEOUT (1 * HZ)
  66. #define QCASPI_QCA7K_REBOOT_TIME_MS 1000
  67. static void
  68. start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
  69. {
  70. *intr_cause = 0;
  71. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  72. qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  73. netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
  74. }
  75. static void
  76. end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
  77. {
  78. u16 intr_enable = (SPI_INT_CPU_ON |
  79. SPI_INT_PKT_AVLBL |
  80. SPI_INT_RDBUF_ERR |
  81. SPI_INT_WRBUF_ERR);
  82. qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  83. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable);
  84. netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
  85. }
  86. static u32
  87. qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
  88. {
  89. __be16 cmd;
  90. struct spi_message *msg = &qca->spi_msg2;
  91. struct spi_transfer *transfer = &qca->spi_xfer2[0];
  92. int ret;
  93. cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  94. transfer->tx_buf = &cmd;
  95. transfer->rx_buf = NULL;
  96. transfer->len = QCASPI_CMD_LEN;
  97. transfer = &qca->spi_xfer2[1];
  98. transfer->tx_buf = src;
  99. transfer->rx_buf = NULL;
  100. transfer->len = len;
  101. ret = spi_sync(qca->spi_dev, msg);
  102. if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) {
  103. qcaspi_spi_error(qca);
  104. return 0;
  105. }
  106. return len;
  107. }
  108. static u32
  109. qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
  110. {
  111. struct spi_message *msg = &qca->spi_msg1;
  112. struct spi_transfer *transfer = &qca->spi_xfer1;
  113. int ret;
  114. transfer->tx_buf = src;
  115. transfer->rx_buf = NULL;
  116. transfer->len = len;
  117. ret = spi_sync(qca->spi_dev, msg);
  118. if (ret || (msg->actual_length != len)) {
  119. qcaspi_spi_error(qca);
  120. return 0;
  121. }
  122. return len;
  123. }
  124. static u32
  125. qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
  126. {
  127. struct spi_message *msg = &qca->spi_msg2;
  128. __be16 cmd;
  129. struct spi_transfer *transfer = &qca->spi_xfer2[0];
  130. int ret;
  131. cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  132. transfer->tx_buf = &cmd;
  133. transfer->rx_buf = NULL;
  134. transfer->len = QCASPI_CMD_LEN;
  135. transfer = &qca->spi_xfer2[1];
  136. transfer->tx_buf = NULL;
  137. transfer->rx_buf = dst;
  138. transfer->len = len;
  139. ret = spi_sync(qca->spi_dev, msg);
  140. if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) {
  141. qcaspi_spi_error(qca);
  142. return 0;
  143. }
  144. return len;
  145. }
  146. static u32
  147. qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
  148. {
  149. struct spi_message *msg = &qca->spi_msg1;
  150. struct spi_transfer *transfer = &qca->spi_xfer1;
  151. int ret;
  152. transfer->tx_buf = NULL;
  153. transfer->rx_buf = dst;
  154. transfer->len = len;
  155. ret = spi_sync(qca->spi_dev, msg);
  156. if (ret || (msg->actual_length != len)) {
  157. qcaspi_spi_error(qca);
  158. return 0;
  159. }
  160. return len;
  161. }
  162. static int
  163. qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
  164. {
  165. u32 count;
  166. u32 written;
  167. u32 offset;
  168. u32 len;
  169. len = skb->len;
  170. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len);
  171. if (qca->legacy_mode)
  172. qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  173. offset = 0;
  174. while (len) {
  175. count = len;
  176. if (count > qca->burst_len)
  177. count = qca->burst_len;
  178. if (qca->legacy_mode) {
  179. written = qcaspi_write_legacy(qca,
  180. skb->data + offset,
  181. count);
  182. } else {
  183. written = qcaspi_write_burst(qca,
  184. skb->data + offset,
  185. count);
  186. }
  187. if (written != count)
  188. return -1;
  189. offset += count;
  190. len -= count;
  191. }
  192. return 0;
  193. }
  194. static int
  195. qcaspi_transmit(struct qcaspi *qca)
  196. {
  197. struct net_device_stats *n_stats = &qca->net_dev->stats;
  198. u16 available = 0;
  199. u32 pkt_len;
  200. u16 new_head;
  201. u16 packets = 0;
  202. if (qca->txr.skb[qca->txr.head] == NULL)
  203. return 0;
  204. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
  205. while (qca->txr.skb[qca->txr.head]) {
  206. pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
  207. if (available < pkt_len) {
  208. if (packets == 0)
  209. qca->stats.write_buf_miss++;
  210. break;
  211. }
  212. if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
  213. qca->stats.write_err++;
  214. return -1;
  215. }
  216. packets++;
  217. n_stats->tx_packets++;
  218. n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
  219. available -= pkt_len;
  220. /* remove the skb from the queue */
  221. /* XXX After inconsistent lock states netif_tx_lock()
  222. * has been replaced by netif_tx_lock_bh() and so on.
  223. */
  224. netif_tx_lock_bh(qca->net_dev);
  225. dev_kfree_skb(qca->txr.skb[qca->txr.head]);
  226. qca->txr.skb[qca->txr.head] = NULL;
  227. qca->txr.size -= pkt_len;
  228. new_head = qca->txr.head + 1;
  229. if (new_head >= qca->txr.count)
  230. new_head = 0;
  231. qca->txr.head = new_head;
  232. if (netif_queue_stopped(qca->net_dev))
  233. netif_wake_queue(qca->net_dev);
  234. netif_tx_unlock_bh(qca->net_dev);
  235. }
  236. return 0;
  237. }
  238. static int
  239. qcaspi_receive(struct qcaspi *qca)
  240. {
  241. struct net_device *net_dev = qca->net_dev;
  242. struct net_device_stats *n_stats = &net_dev->stats;
  243. u16 available = 0;
  244. u32 bytes_read;
  245. u8 *cp;
  246. /* Allocate rx SKB if we don't have one available. */
  247. if (!qca->rx_skb) {
  248. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  249. net_dev->mtu +
  250. VLAN_ETH_HLEN);
  251. if (!qca->rx_skb) {
  252. netdev_dbg(net_dev, "out of RX resources\n");
  253. qca->stats.out_of_mem++;
  254. return -1;
  255. }
  256. }
  257. /* Read the packet size. */
  258. qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
  259. netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %08x\n",
  260. available);
  261. if (available == 0) {
  262. netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
  263. return -1;
  264. }
  265. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available);
  266. if (qca->legacy_mode)
  267. qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  268. while (available) {
  269. u32 count = available;
  270. if (count > qca->burst_len)
  271. count = qca->burst_len;
  272. if (qca->legacy_mode) {
  273. bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
  274. count);
  275. } else {
  276. bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
  277. count);
  278. }
  279. netdev_dbg(net_dev, "available: %d, byte read: %d\n",
  280. available, bytes_read);
  281. if (bytes_read) {
  282. available -= bytes_read;
  283. } else {
  284. qca->stats.read_err++;
  285. return -1;
  286. }
  287. cp = qca->rx_buffer;
  288. while ((bytes_read--) && (qca->rx_skb)) {
  289. s32 retcode;
  290. retcode = qcafrm_fsm_decode(&qca->frm_handle,
  291. qca->rx_skb->data,
  292. skb_tailroom(qca->rx_skb),
  293. *cp);
  294. cp++;
  295. switch (retcode) {
  296. case QCAFRM_GATHER:
  297. case QCAFRM_NOHEAD:
  298. break;
  299. case QCAFRM_NOTAIL:
  300. netdev_dbg(net_dev, "no RX tail\n");
  301. n_stats->rx_errors++;
  302. n_stats->rx_dropped++;
  303. break;
  304. case QCAFRM_INVLEN:
  305. netdev_dbg(net_dev, "invalid RX length\n");
  306. n_stats->rx_errors++;
  307. n_stats->rx_dropped++;
  308. break;
  309. default:
  310. qca->rx_skb->dev = qca->net_dev;
  311. n_stats->rx_packets++;
  312. n_stats->rx_bytes += retcode;
  313. skb_put(qca->rx_skb, retcode);
  314. qca->rx_skb->protocol = eth_type_trans(
  315. qca->rx_skb, qca->rx_skb->dev);
  316. qca->rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
  317. netif_rx_ni(qca->rx_skb);
  318. qca->rx_skb = netdev_alloc_skb_ip_align(net_dev,
  319. net_dev->mtu + VLAN_ETH_HLEN);
  320. if (!qca->rx_skb) {
  321. netdev_dbg(net_dev, "out of RX resources\n");
  322. n_stats->rx_errors++;
  323. qca->stats.out_of_mem++;
  324. break;
  325. }
  326. }
  327. }
  328. }
  329. return 0;
  330. }
  331. /* Check that tx ring stores only so much bytes
  332. * that fit into the internal QCA buffer.
  333. */
  334. static int
  335. qcaspi_tx_ring_has_space(struct tx_ring *txr)
  336. {
  337. if (txr->skb[txr->tail])
  338. return 0;
  339. return (txr->size + QCAFRM_ETHMAXLEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
  340. }
  341. /* Flush the tx ring. This function is only safe to
  342. * call from the qcaspi_spi_thread.
  343. */
  344. static void
  345. qcaspi_flush_tx_ring(struct qcaspi *qca)
  346. {
  347. int i;
  348. /* XXX After inconsistent lock states netif_tx_lock()
  349. * has been replaced by netif_tx_lock_bh() and so on.
  350. */
  351. netif_tx_lock_bh(qca->net_dev);
  352. for (i = 0; i < TX_RING_MAX_LEN; i++) {
  353. if (qca->txr.skb[i]) {
  354. dev_kfree_skb(qca->txr.skb[i]);
  355. qca->txr.skb[i] = NULL;
  356. qca->net_dev->stats.tx_dropped++;
  357. }
  358. }
  359. qca->txr.tail = 0;
  360. qca->txr.head = 0;
  361. qca->txr.size = 0;
  362. netif_tx_unlock_bh(qca->net_dev);
  363. }
  364. static void
  365. qcaspi_qca7k_sync(struct qcaspi *qca, int event)
  366. {
  367. u16 signature = 0;
  368. u16 spi_config;
  369. u16 wrbuf_space = 0;
  370. static u16 reset_count;
  371. if (event == QCASPI_EVENT_CPUON) {
  372. /* Read signature twice, if not valid
  373. * go back to unknown state.
  374. */
  375. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  376. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  377. if (signature != QCASPI_GOOD_SIGNATURE) {
  378. qca->sync = QCASPI_SYNC_UNKNOWN;
  379. netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
  380. } else {
  381. /* ensure that the WRBUF is empty */
  382. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
  383. &wrbuf_space);
  384. if (wrbuf_space != QCASPI_HW_BUF_LEN) {
  385. netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
  386. qca->sync = QCASPI_SYNC_UNKNOWN;
  387. } else {
  388. netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
  389. qca->sync = QCASPI_SYNC_READY;
  390. return;
  391. }
  392. }
  393. }
  394. switch (qca->sync) {
  395. case QCASPI_SYNC_READY:
  396. /* Read signature, if not valid go to unknown state. */
  397. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  398. if (signature != QCASPI_GOOD_SIGNATURE) {
  399. qca->sync = QCASPI_SYNC_UNKNOWN;
  400. netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
  401. /* don't reset right away */
  402. return;
  403. }
  404. break;
  405. case QCASPI_SYNC_UNKNOWN:
  406. /* Read signature, if not valid stay in unknown state */
  407. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  408. if (signature != QCASPI_GOOD_SIGNATURE) {
  409. netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
  410. return;
  411. }
  412. /* TODO: use GPIO to reset QCA7000 in legacy mode*/
  413. netdev_dbg(qca->net_dev, "sync: resetting device.\n");
  414. qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
  415. spi_config |= QCASPI_SLAVE_RESET_BIT;
  416. qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config);
  417. qca->sync = QCASPI_SYNC_RESET;
  418. qca->stats.trig_reset++;
  419. reset_count = 0;
  420. break;
  421. case QCASPI_SYNC_RESET:
  422. reset_count++;
  423. netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
  424. reset_count);
  425. if (reset_count >= QCASPI_RESET_TIMEOUT) {
  426. /* reset did not seem to take place, try again */
  427. qca->sync = QCASPI_SYNC_UNKNOWN;
  428. qca->stats.reset_timeout++;
  429. netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
  430. }
  431. break;
  432. }
  433. }
  434. static int
  435. qcaspi_spi_thread(void *data)
  436. {
  437. struct qcaspi *qca = data;
  438. u16 intr_cause = 0;
  439. netdev_info(qca->net_dev, "SPI thread created\n");
  440. while (!kthread_should_stop()) {
  441. set_current_state(TASK_INTERRUPTIBLE);
  442. if ((qca->intr_req == qca->intr_svc) &&
  443. (qca->txr.skb[qca->txr.head] == NULL) &&
  444. (qca->sync == QCASPI_SYNC_READY))
  445. schedule();
  446. set_current_state(TASK_RUNNING);
  447. netdev_dbg(qca->net_dev, "have work to do. int: %d, tx_skb: %p\n",
  448. qca->intr_req - qca->intr_svc,
  449. qca->txr.skb[qca->txr.head]);
  450. qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
  451. if (qca->sync != QCASPI_SYNC_READY) {
  452. netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
  453. (unsigned int)qca->sync);
  454. netif_stop_queue(qca->net_dev);
  455. netif_carrier_off(qca->net_dev);
  456. qcaspi_flush_tx_ring(qca);
  457. msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
  458. }
  459. if (qca->intr_svc != qca->intr_req) {
  460. qca->intr_svc = qca->intr_req;
  461. start_spi_intr_handling(qca, &intr_cause);
  462. if (intr_cause & SPI_INT_CPU_ON) {
  463. qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
  464. /* not synced. */
  465. if (qca->sync != QCASPI_SYNC_READY)
  466. continue;
  467. qca->stats.device_reset++;
  468. netif_wake_queue(qca->net_dev);
  469. netif_carrier_on(qca->net_dev);
  470. }
  471. if (intr_cause & SPI_INT_RDBUF_ERR) {
  472. /* restart sync */
  473. netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
  474. qca->stats.read_buf_err++;
  475. qca->sync = QCASPI_SYNC_UNKNOWN;
  476. continue;
  477. }
  478. if (intr_cause & SPI_INT_WRBUF_ERR) {
  479. /* restart sync */
  480. netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
  481. qca->stats.write_buf_err++;
  482. qca->sync = QCASPI_SYNC_UNKNOWN;
  483. continue;
  484. }
  485. /* can only handle other interrupts
  486. * if sync has occurred
  487. */
  488. if (qca->sync == QCASPI_SYNC_READY) {
  489. if (intr_cause & SPI_INT_PKT_AVLBL)
  490. qcaspi_receive(qca);
  491. }
  492. end_spi_intr_handling(qca, intr_cause);
  493. }
  494. if (qca->sync == QCASPI_SYNC_READY)
  495. qcaspi_transmit(qca);
  496. }
  497. set_current_state(TASK_RUNNING);
  498. netdev_info(qca->net_dev, "SPI thread exit\n");
  499. return 0;
  500. }
  501. static irqreturn_t
  502. qcaspi_intr_handler(int irq, void *data)
  503. {
  504. struct qcaspi *qca = data;
  505. qca->intr_req++;
  506. if (qca->spi_thread &&
  507. qca->spi_thread->state != TASK_RUNNING)
  508. wake_up_process(qca->spi_thread);
  509. return IRQ_HANDLED;
  510. }
  511. int
  512. qcaspi_netdev_open(struct net_device *dev)
  513. {
  514. struct qcaspi *qca = netdev_priv(dev);
  515. int ret = 0;
  516. if (!qca)
  517. return -EINVAL;
  518. qca->intr_req = 1;
  519. qca->intr_svc = 0;
  520. qca->sync = QCASPI_SYNC_UNKNOWN;
  521. qcafrm_fsm_init(&qca->frm_handle);
  522. qca->spi_thread = kthread_run((void *)qcaspi_spi_thread,
  523. qca, "%s", dev->name);
  524. if (IS_ERR(qca->spi_thread)) {
  525. netdev_err(dev, "%s: unable to start kernel thread.\n",
  526. QCASPI_DRV_NAME);
  527. return PTR_ERR(qca->spi_thread);
  528. }
  529. ret = request_irq(qca->spi_dev->irq, qcaspi_intr_handler, 0,
  530. dev->name, qca);
  531. if (ret) {
  532. netdev_err(dev, "%s: unable to get IRQ %d (irqval=%d).\n",
  533. QCASPI_DRV_NAME, qca->spi_dev->irq, ret);
  534. kthread_stop(qca->spi_thread);
  535. return ret;
  536. }
  537. netif_start_queue(qca->net_dev);
  538. return 0;
  539. }
  540. int
  541. qcaspi_netdev_close(struct net_device *dev)
  542. {
  543. struct qcaspi *qca = netdev_priv(dev);
  544. netif_stop_queue(dev);
  545. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  546. free_irq(qca->spi_dev->irq, qca);
  547. kthread_stop(qca->spi_thread);
  548. qca->spi_thread = NULL;
  549. qcaspi_flush_tx_ring(qca);
  550. return 0;
  551. }
  552. static netdev_tx_t
  553. qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
  554. {
  555. u32 frame_len;
  556. u8 *ptmp;
  557. struct qcaspi *qca = netdev_priv(dev);
  558. u16 new_tail;
  559. struct sk_buff *tskb;
  560. u8 pad_len = 0;
  561. if (skb->len < QCAFRM_ETHMINLEN)
  562. pad_len = QCAFRM_ETHMINLEN - skb->len;
  563. if (qca->txr.skb[qca->txr.tail]) {
  564. netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
  565. netif_stop_queue(qca->net_dev);
  566. qca->stats.ring_full++;
  567. return NETDEV_TX_BUSY;
  568. }
  569. if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
  570. (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
  571. tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
  572. QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
  573. if (!tskb) {
  574. netdev_dbg(qca->net_dev, "could not allocate tx_buff\n");
  575. qca->stats.out_of_mem++;
  576. return NETDEV_TX_BUSY;
  577. }
  578. dev_kfree_skb(skb);
  579. skb = tskb;
  580. }
  581. frame_len = skb->len + pad_len;
  582. ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
  583. qcafrm_create_header(ptmp, frame_len);
  584. if (pad_len) {
  585. ptmp = skb_put(skb, pad_len);
  586. memset(ptmp, 0, pad_len);
  587. }
  588. ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
  589. qcafrm_create_footer(ptmp);
  590. netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
  591. skb->len);
  592. qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
  593. new_tail = qca->txr.tail + 1;
  594. if (new_tail >= qca->txr.count)
  595. new_tail = 0;
  596. qca->txr.skb[qca->txr.tail] = skb;
  597. qca->txr.tail = new_tail;
  598. if (!qcaspi_tx_ring_has_space(&qca->txr)) {
  599. netif_stop_queue(qca->net_dev);
  600. qca->stats.ring_full++;
  601. }
  602. netif_trans_update(dev);
  603. if (qca->spi_thread &&
  604. qca->spi_thread->state != TASK_RUNNING)
  605. wake_up_process(qca->spi_thread);
  606. return NETDEV_TX_OK;
  607. }
  608. static void
  609. qcaspi_netdev_tx_timeout(struct net_device *dev)
  610. {
  611. struct qcaspi *qca = netdev_priv(dev);
  612. netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
  613. jiffies, jiffies - dev_trans_start(dev));
  614. qca->net_dev->stats.tx_errors++;
  615. /* Trigger tx queue flush and QCA7000 reset */
  616. qca->sync = QCASPI_SYNC_UNKNOWN;
  617. }
  618. static int
  619. qcaspi_netdev_init(struct net_device *dev)
  620. {
  621. struct qcaspi *qca = netdev_priv(dev);
  622. dev->mtu = QCASPI_MTU;
  623. dev->type = ARPHRD_ETHER;
  624. qca->clkspeed = qcaspi_clkspeed;
  625. qca->burst_len = qcaspi_burst_len;
  626. qca->spi_thread = NULL;
  627. qca->buffer_size = (dev->mtu + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
  628. QCAFRM_FOOTER_LEN + 4) * 4;
  629. memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
  630. qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
  631. if (!qca->rx_buffer)
  632. return -ENOBUFS;
  633. qca->rx_skb = netdev_alloc_skb_ip_align(dev, qca->net_dev->mtu +
  634. VLAN_ETH_HLEN);
  635. if (!qca->rx_skb) {
  636. kfree(qca->rx_buffer);
  637. netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
  638. return -ENOBUFS;
  639. }
  640. return 0;
  641. }
  642. static void
  643. qcaspi_netdev_uninit(struct net_device *dev)
  644. {
  645. struct qcaspi *qca = netdev_priv(dev);
  646. kfree(qca->rx_buffer);
  647. qca->buffer_size = 0;
  648. if (qca->rx_skb)
  649. dev_kfree_skb(qca->rx_skb);
  650. }
  651. static int
  652. qcaspi_netdev_change_mtu(struct net_device *dev, int new_mtu)
  653. {
  654. if ((new_mtu < QCAFRM_ETHMINMTU) || (new_mtu > QCAFRM_ETHMAXMTU))
  655. return -EINVAL;
  656. dev->mtu = new_mtu;
  657. return 0;
  658. }
  659. static const struct net_device_ops qcaspi_netdev_ops = {
  660. .ndo_init = qcaspi_netdev_init,
  661. .ndo_uninit = qcaspi_netdev_uninit,
  662. .ndo_open = qcaspi_netdev_open,
  663. .ndo_stop = qcaspi_netdev_close,
  664. .ndo_start_xmit = qcaspi_netdev_xmit,
  665. .ndo_change_mtu = qcaspi_netdev_change_mtu,
  666. .ndo_set_mac_address = eth_mac_addr,
  667. .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
  668. .ndo_validate_addr = eth_validate_addr,
  669. };
  670. static void
  671. qcaspi_netdev_setup(struct net_device *dev)
  672. {
  673. struct qcaspi *qca = NULL;
  674. dev->netdev_ops = &qcaspi_netdev_ops;
  675. qcaspi_set_ethtool_ops(dev);
  676. dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
  677. dev->priv_flags &= ~IFF_TX_SKB_SHARING;
  678. dev->tx_queue_len = 100;
  679. qca = netdev_priv(dev);
  680. memset(qca, 0, sizeof(struct qcaspi));
  681. memset(&qca->spi_xfer1, 0, sizeof(struct spi_transfer));
  682. memset(&qca->spi_xfer2, 0, sizeof(struct spi_transfer) * 2);
  683. spi_message_init(&qca->spi_msg1);
  684. spi_message_add_tail(&qca->spi_xfer1, &qca->spi_msg1);
  685. spi_message_init(&qca->spi_msg2);
  686. spi_message_add_tail(&qca->spi_xfer2[0], &qca->spi_msg2);
  687. spi_message_add_tail(&qca->spi_xfer2[1], &qca->spi_msg2);
  688. memset(&qca->txr, 0, sizeof(qca->txr));
  689. qca->txr.count = TX_RING_MAX_LEN;
  690. }
  691. static const struct of_device_id qca_spi_of_match[] = {
  692. { .compatible = "qca,qca7000" },
  693. { /* sentinel */ }
  694. };
  695. MODULE_DEVICE_TABLE(of, qca_spi_of_match);
  696. static int
  697. qca_spi_probe(struct spi_device *spi)
  698. {
  699. struct qcaspi *qca = NULL;
  700. struct net_device *qcaspi_devs = NULL;
  701. u8 legacy_mode = 0;
  702. u16 signature;
  703. const char *mac;
  704. if (!spi->dev.of_node) {
  705. dev_err(&spi->dev, "Missing device tree\n");
  706. return -EINVAL;
  707. }
  708. legacy_mode = of_property_read_bool(spi->dev.of_node,
  709. "qca,legacy-mode");
  710. if (qcaspi_clkspeed == 0) {
  711. if (spi->max_speed_hz)
  712. qcaspi_clkspeed = spi->max_speed_hz;
  713. else
  714. qcaspi_clkspeed = QCASPI_CLK_SPEED;
  715. }
  716. if ((qcaspi_clkspeed < QCASPI_CLK_SPEED_MIN) ||
  717. (qcaspi_clkspeed > QCASPI_CLK_SPEED_MAX)) {
  718. dev_info(&spi->dev, "Invalid clkspeed: %d\n",
  719. qcaspi_clkspeed);
  720. return -EINVAL;
  721. }
  722. if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
  723. (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
  724. dev_info(&spi->dev, "Invalid burst len: %d\n",
  725. qcaspi_burst_len);
  726. return -EINVAL;
  727. }
  728. if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
  729. (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
  730. dev_info(&spi->dev, "Invalid pluggable: %d\n",
  731. qcaspi_pluggable);
  732. return -EINVAL;
  733. }
  734. dev_info(&spi->dev, "ver=%s, clkspeed=%d, burst_len=%d, pluggable=%d\n",
  735. QCASPI_DRV_VERSION,
  736. qcaspi_clkspeed,
  737. qcaspi_burst_len,
  738. qcaspi_pluggable);
  739. spi->mode = SPI_MODE_3;
  740. spi->max_speed_hz = qcaspi_clkspeed;
  741. if (spi_setup(spi) < 0) {
  742. dev_err(&spi->dev, "Unable to setup SPI device\n");
  743. return -EFAULT;
  744. }
  745. qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
  746. if (!qcaspi_devs)
  747. return -ENOMEM;
  748. qcaspi_netdev_setup(qcaspi_devs);
  749. qca = netdev_priv(qcaspi_devs);
  750. if (!qca) {
  751. free_netdev(qcaspi_devs);
  752. dev_err(&spi->dev, "Fail to retrieve private structure\n");
  753. return -ENOMEM;
  754. }
  755. qca->net_dev = qcaspi_devs;
  756. qca->spi_dev = spi;
  757. qca->legacy_mode = legacy_mode;
  758. spi_set_drvdata(spi, qcaspi_devs);
  759. mac = of_get_mac_address(spi->dev.of_node);
  760. if (mac)
  761. ether_addr_copy(qca->net_dev->dev_addr, mac);
  762. if (!is_valid_ether_addr(qca->net_dev->dev_addr)) {
  763. eth_hw_addr_random(qca->net_dev);
  764. dev_info(&spi->dev, "Using random MAC address: %pM\n",
  765. qca->net_dev->dev_addr);
  766. }
  767. netif_carrier_off(qca->net_dev);
  768. if (!qcaspi_pluggable) {
  769. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  770. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  771. if (signature != QCASPI_GOOD_SIGNATURE) {
  772. dev_err(&spi->dev, "Invalid signature (0x%04X)\n",
  773. signature);
  774. free_netdev(qcaspi_devs);
  775. return -EFAULT;
  776. }
  777. }
  778. if (register_netdev(qcaspi_devs)) {
  779. dev_info(&spi->dev, "Unable to register net device %s\n",
  780. qcaspi_devs->name);
  781. free_netdev(qcaspi_devs);
  782. return -EFAULT;
  783. }
  784. qcaspi_init_device_debugfs(qca);
  785. return 0;
  786. }
  787. static int
  788. qca_spi_remove(struct spi_device *spi)
  789. {
  790. struct net_device *qcaspi_devs = spi_get_drvdata(spi);
  791. struct qcaspi *qca = netdev_priv(qcaspi_devs);
  792. qcaspi_remove_device_debugfs(qca);
  793. unregister_netdev(qcaspi_devs);
  794. free_netdev(qcaspi_devs);
  795. return 0;
  796. }
  797. static const struct spi_device_id qca_spi_id[] = {
  798. { "qca7000", 0 },
  799. { /* sentinel */ }
  800. };
  801. MODULE_DEVICE_TABLE(spi, qca_spi_id);
  802. static struct spi_driver qca_spi_driver = {
  803. .driver = {
  804. .name = QCASPI_DRV_NAME,
  805. .of_match_table = qca_spi_of_match,
  806. },
  807. .id_table = qca_spi_id,
  808. .probe = qca_spi_probe,
  809. .remove = qca_spi_remove,
  810. };
  811. module_spi_driver(qca_spi_driver);
  812. MODULE_DESCRIPTION("Qualcomm Atheros SPI Driver");
  813. MODULE_AUTHOR("Qualcomm Atheros Communications");
  814. MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
  815. MODULE_LICENSE("Dual BSD/GPL");
  816. MODULE_VERSION(QCASPI_DRV_VERSION);