i40e_hmc.h 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239
  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 - 2014 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program. If not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * The full GNU General Public License is included in this distribution in
  19. * the file called "COPYING".
  20. *
  21. * Contact Information:
  22. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. ******************************************************************************/
  26. #ifndef _I40E_HMC_H_
  27. #define _I40E_HMC_H_
  28. #define I40E_HMC_MAX_BP_COUNT 512
  29. /* forward-declare the HW struct for the compiler */
  30. struct i40e_hw;
  31. #define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */
  32. #define I40E_HMC_PD_CNT_IN_SD 512
  33. #define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
  34. #define I40E_HMC_PAGED_BP_SIZE 4096
  35. #define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096
  36. #define I40E_FIRST_VF_FPM_ID 16
  37. struct i40e_hmc_obj_info {
  38. u64 base; /* base addr in FPM */
  39. u32 max_cnt; /* max count available for this hmc func */
  40. u32 cnt; /* count of objects driver actually wants to create */
  41. u64 size; /* size in bytes of one object */
  42. };
  43. enum i40e_sd_entry_type {
  44. I40E_SD_TYPE_INVALID = 0,
  45. I40E_SD_TYPE_PAGED = 1,
  46. I40E_SD_TYPE_DIRECT = 2
  47. };
  48. struct i40e_hmc_bp {
  49. enum i40e_sd_entry_type entry_type;
  50. struct i40e_dma_mem addr; /* populate to be used by hw */
  51. u32 sd_pd_index;
  52. u32 ref_cnt;
  53. };
  54. struct i40e_hmc_pd_entry {
  55. struct i40e_hmc_bp bp;
  56. u32 sd_index;
  57. bool rsrc_pg;
  58. bool valid;
  59. };
  60. struct i40e_hmc_pd_table {
  61. struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */
  62. struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */
  63. struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */
  64. u32 ref_cnt;
  65. u32 sd_index;
  66. };
  67. struct i40e_hmc_sd_entry {
  68. enum i40e_sd_entry_type entry_type;
  69. bool valid;
  70. union {
  71. struct i40e_hmc_pd_table pd_table;
  72. struct i40e_hmc_bp bp;
  73. } u;
  74. };
  75. struct i40e_hmc_sd_table {
  76. struct i40e_virt_mem addr; /* used to track sd_entry allocations */
  77. u32 sd_cnt;
  78. u32 ref_cnt;
  79. struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */
  80. };
  81. struct i40e_hmc_info {
  82. u32 signature;
  83. /* equals to pci func num for PF and dynamically allocated for VFs */
  84. u8 hmc_fn_id;
  85. u16 first_sd_index; /* index of the first available SD */
  86. /* hmc objects */
  87. struct i40e_hmc_obj_info *hmc_obj;
  88. struct i40e_virt_mem hmc_obj_virt_mem;
  89. struct i40e_hmc_sd_table sd_table;
  90. };
  91. #define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
  92. #define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
  93. #define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)
  94. #define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
  95. #define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
  96. #define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)
  97. /**
  98. * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware
  99. * @hw: pointer to our hw struct
  100. * @pa: pointer to physical address
  101. * @sd_index: segment descriptor index
  102. * @type: if sd entry is direct or paged
  103. **/
  104. #define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \
  105. { \
  106. u32 val1, val2, val3; \
  107. val1 = (u32)(upper_32_bits(pa)); \
  108. val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \
  109. I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
  110. ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
  111. I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
  112. BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
  113. val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
  114. wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
  115. wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
  116. wr32((hw), I40E_PFHMC_SDCMD, val3); \
  117. }
  118. /**
  119. * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware
  120. * @hw: pointer to our hw struct
  121. * @sd_index: segment descriptor index
  122. * @type: if sd entry is direct or paged
  123. **/
  124. #define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \
  125. { \
  126. u32 val2, val3; \
  127. val2 = (I40E_HMC_MAX_BP_COUNT << \
  128. I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
  129. ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
  130. I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
  131. val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
  132. wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
  133. wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
  134. wr32((hw), I40E_PFHMC_SDCMD, val3); \
  135. }
  136. /**
  137. * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
  138. * @hw: pointer to our hw struct
  139. * @sd_idx: segment descriptor index
  140. * @pd_idx: page descriptor index
  141. **/
  142. #define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
  143. wr32((hw), I40E_PFHMC_PDINV, \
  144. (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
  145. ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
  146. /**
  147. * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit
  148. * @hmc_info: pointer to the HMC configuration information structure
  149. * @type: type of HMC resources we're searching
  150. * @index: starting index for the object
  151. * @cnt: number of objects we're trying to create
  152. * @sd_idx: pointer to return index of the segment descriptor in question
  153. * @sd_limit: pointer to return the maximum number of segment descriptors
  154. *
  155. * This function calculates the segment descriptor index and index limit
  156. * for the resource defined by i40e_hmc_rsrc_type.
  157. **/
  158. #define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\
  159. { \
  160. u64 fpm_addr, fpm_limit; \
  161. fpm_addr = (hmc_info)->hmc_obj[(type)].base + \
  162. (hmc_info)->hmc_obj[(type)].size * (index); \
  163. fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\
  164. *(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \
  165. *(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \
  166. /* add one more to the limit to correct our range */ \
  167. *(sd_limit) += 1; \
  168. }
  169. /**
  170. * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit
  171. * @hmc_info: pointer to the HMC configuration information struct
  172. * @type: HMC resource type we're examining
  173. * @idx: starting index for the object
  174. * @cnt: number of objects we're trying to create
  175. * @pd_index: pointer to return page descriptor index
  176. * @pd_limit: pointer to return page descriptor index limit
  177. *
  178. * Calculates the page descriptor index and index limit for the resource
  179. * defined by i40e_hmc_rsrc_type.
  180. **/
  181. #define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\
  182. { \
  183. u64 fpm_adr, fpm_limit; \
  184. fpm_adr = (hmc_info)->hmc_obj[(type)].base + \
  185. (hmc_info)->hmc_obj[(type)].size * (idx); \
  186. fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \
  187. *(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \
  188. *(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \
  189. /* add one more to the limit to correct our range */ \
  190. *(pd_limit) += 1; \
  191. }
  192. i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
  193. struct i40e_hmc_info *hmc_info,
  194. u32 sd_index,
  195. enum i40e_sd_entry_type type,
  196. u64 direct_mode_sz);
  197. i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
  198. struct i40e_hmc_info *hmc_info,
  199. u32 pd_index,
  200. struct i40e_dma_mem *rsrc_pg);
  201. i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
  202. struct i40e_hmc_info *hmc_info,
  203. u32 idx);
  204. i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
  205. u32 idx);
  206. i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
  207. struct i40e_hmc_info *hmc_info,
  208. u32 idx, bool is_pf);
  209. i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
  210. u32 idx);
  211. i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
  212. struct i40e_hmc_info *hmc_info,
  213. u32 idx, bool is_pf);
  214. #endif /* _I40E_HMC_H_ */