emac_main.c 23 KB

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  1. /*
  2. * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Driver for the ARC EMAC 10100 (hardware revision 5)
  9. *
  10. * Contributors:
  11. * Amit Bhor
  12. * Sameer Dhavale
  13. * Vineet Gupta
  14. */
  15. #include <linux/crc32.h>
  16. #include <linux/etherdevice.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/module.h>
  20. #include <linux/of_address.h>
  21. #include <linux/of_irq.h>
  22. #include <linux/of_mdio.h>
  23. #include <linux/of_net.h>
  24. #include <linux/of_platform.h>
  25. #include "emac.h"
  26. /**
  27. * arc_emac_tx_avail - Return the number of available slots in the tx ring.
  28. * @priv: Pointer to ARC EMAC private data structure.
  29. *
  30. * returns: the number of slots available for transmission in tx the ring.
  31. */
  32. static inline int arc_emac_tx_avail(struct arc_emac_priv *priv)
  33. {
  34. return (priv->txbd_dirty + TX_BD_NUM - priv->txbd_curr - 1) % TX_BD_NUM;
  35. }
  36. /**
  37. * arc_emac_adjust_link - Adjust the PHY link duplex.
  38. * @ndev: Pointer to the net_device structure.
  39. *
  40. * This function is called to change the duplex setting after auto negotiation
  41. * is done by the PHY.
  42. */
  43. static void arc_emac_adjust_link(struct net_device *ndev)
  44. {
  45. struct arc_emac_priv *priv = netdev_priv(ndev);
  46. struct phy_device *phy_dev = ndev->phydev;
  47. unsigned int reg, state_changed = 0;
  48. if (priv->link != phy_dev->link) {
  49. priv->link = phy_dev->link;
  50. state_changed = 1;
  51. }
  52. if (priv->speed != phy_dev->speed) {
  53. priv->speed = phy_dev->speed;
  54. state_changed = 1;
  55. if (priv->set_mac_speed)
  56. priv->set_mac_speed(priv, priv->speed);
  57. }
  58. if (priv->duplex != phy_dev->duplex) {
  59. reg = arc_reg_get(priv, R_CTRL);
  60. if (phy_dev->duplex == DUPLEX_FULL)
  61. reg |= ENFL_MASK;
  62. else
  63. reg &= ~ENFL_MASK;
  64. arc_reg_set(priv, R_CTRL, reg);
  65. priv->duplex = phy_dev->duplex;
  66. state_changed = 1;
  67. }
  68. if (state_changed)
  69. phy_print_status(phy_dev);
  70. }
  71. /**
  72. * arc_emac_get_drvinfo - Get EMAC driver information.
  73. * @ndev: Pointer to net_device structure.
  74. * @info: Pointer to ethtool_drvinfo structure.
  75. *
  76. * This implements ethtool command for getting the driver information.
  77. * Issue "ethtool -i ethX" under linux prompt to execute this function.
  78. */
  79. static void arc_emac_get_drvinfo(struct net_device *ndev,
  80. struct ethtool_drvinfo *info)
  81. {
  82. struct arc_emac_priv *priv = netdev_priv(ndev);
  83. strlcpy(info->driver, priv->drv_name, sizeof(info->driver));
  84. strlcpy(info->version, priv->drv_version, sizeof(info->version));
  85. }
  86. static const struct ethtool_ops arc_emac_ethtool_ops = {
  87. .get_drvinfo = arc_emac_get_drvinfo,
  88. .get_link = ethtool_op_get_link,
  89. .get_link_ksettings = phy_ethtool_get_link_ksettings,
  90. .set_link_ksettings = phy_ethtool_set_link_ksettings,
  91. };
  92. #define FIRST_OR_LAST_MASK (FIRST_MASK | LAST_MASK)
  93. /**
  94. * arc_emac_tx_clean - clears processed by EMAC Tx BDs.
  95. * @ndev: Pointer to the network device.
  96. */
  97. static void arc_emac_tx_clean(struct net_device *ndev)
  98. {
  99. struct arc_emac_priv *priv = netdev_priv(ndev);
  100. struct net_device_stats *stats = &ndev->stats;
  101. unsigned int i;
  102. for (i = 0; i < TX_BD_NUM; i++) {
  103. unsigned int *txbd_dirty = &priv->txbd_dirty;
  104. struct arc_emac_bd *txbd = &priv->txbd[*txbd_dirty];
  105. struct buffer_state *tx_buff = &priv->tx_buff[*txbd_dirty];
  106. struct sk_buff *skb = tx_buff->skb;
  107. unsigned int info = le32_to_cpu(txbd->info);
  108. if ((info & FOR_EMAC) || !txbd->data || !skb)
  109. break;
  110. if (unlikely(info & (DROP | DEFR | LTCL | UFLO))) {
  111. stats->tx_errors++;
  112. stats->tx_dropped++;
  113. if (info & DEFR)
  114. stats->tx_carrier_errors++;
  115. if (info & LTCL)
  116. stats->collisions++;
  117. if (info & UFLO)
  118. stats->tx_fifo_errors++;
  119. } else if (likely(info & FIRST_OR_LAST_MASK)) {
  120. stats->tx_packets++;
  121. stats->tx_bytes += skb->len;
  122. }
  123. dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
  124. dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
  125. /* return the sk_buff to system */
  126. dev_kfree_skb_irq(skb);
  127. txbd->data = 0;
  128. txbd->info = 0;
  129. tx_buff->skb = NULL;
  130. *txbd_dirty = (*txbd_dirty + 1) % TX_BD_NUM;
  131. }
  132. /* Ensure that txbd_dirty is visible to tx() before checking
  133. * for queue stopped.
  134. */
  135. smp_mb();
  136. if (netif_queue_stopped(ndev) && arc_emac_tx_avail(priv))
  137. netif_wake_queue(ndev);
  138. }
  139. /**
  140. * arc_emac_rx - processing of Rx packets.
  141. * @ndev: Pointer to the network device.
  142. * @budget: How many BDs to process on 1 call.
  143. *
  144. * returns: Number of processed BDs
  145. *
  146. * Iterate through Rx BDs and deliver received packages to upper layer.
  147. */
  148. static int arc_emac_rx(struct net_device *ndev, int budget)
  149. {
  150. struct arc_emac_priv *priv = netdev_priv(ndev);
  151. unsigned int work_done;
  152. for (work_done = 0; work_done < budget; work_done++) {
  153. unsigned int *last_rx_bd = &priv->last_rx_bd;
  154. struct net_device_stats *stats = &ndev->stats;
  155. struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
  156. struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
  157. unsigned int pktlen, info = le32_to_cpu(rxbd->info);
  158. struct sk_buff *skb;
  159. dma_addr_t addr;
  160. if (unlikely((info & OWN_MASK) == FOR_EMAC))
  161. break;
  162. /* Make a note that we saw a packet at this BD.
  163. * So next time, driver starts from this + 1
  164. */
  165. *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
  166. if (unlikely((info & FIRST_OR_LAST_MASK) !=
  167. FIRST_OR_LAST_MASK)) {
  168. /* We pre-allocate buffers of MTU size so incoming
  169. * packets won't be split/chained.
  170. */
  171. if (net_ratelimit())
  172. netdev_err(ndev, "incomplete packet received\n");
  173. /* Return ownership to EMAC */
  174. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  175. stats->rx_errors++;
  176. stats->rx_length_errors++;
  177. continue;
  178. }
  179. /* Prepare the BD for next cycle. netif_receive_skb()
  180. * only if new skb was allocated and mapped to avoid holes
  181. * in the RX fifo.
  182. */
  183. skb = netdev_alloc_skb_ip_align(ndev, EMAC_BUFFER_SIZE);
  184. if (unlikely(!skb)) {
  185. if (net_ratelimit())
  186. netdev_err(ndev, "cannot allocate skb\n");
  187. /* Return ownership to EMAC */
  188. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  189. stats->rx_errors++;
  190. stats->rx_dropped++;
  191. continue;
  192. }
  193. addr = dma_map_single(&ndev->dev, (void *)skb->data,
  194. EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
  195. if (dma_mapping_error(&ndev->dev, addr)) {
  196. if (net_ratelimit())
  197. netdev_err(ndev, "cannot map dma buffer\n");
  198. dev_kfree_skb(skb);
  199. /* Return ownership to EMAC */
  200. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  201. stats->rx_errors++;
  202. stats->rx_dropped++;
  203. continue;
  204. }
  205. /* unmap previosly mapped skb */
  206. dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
  207. dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
  208. pktlen = info & LEN_MASK;
  209. stats->rx_packets++;
  210. stats->rx_bytes += pktlen;
  211. skb_put(rx_buff->skb, pktlen);
  212. rx_buff->skb->dev = ndev;
  213. rx_buff->skb->protocol = eth_type_trans(rx_buff->skb, ndev);
  214. netif_receive_skb(rx_buff->skb);
  215. rx_buff->skb = skb;
  216. dma_unmap_addr_set(rx_buff, addr, addr);
  217. dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
  218. rxbd->data = cpu_to_le32(addr);
  219. /* Make sure pointer to data buffer is set */
  220. wmb();
  221. /* Return ownership to EMAC */
  222. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  223. }
  224. return work_done;
  225. }
  226. /**
  227. * arc_emac_poll - NAPI poll handler.
  228. * @napi: Pointer to napi_struct structure.
  229. * @budget: How many BDs to process on 1 call.
  230. *
  231. * returns: Number of processed BDs
  232. */
  233. static int arc_emac_poll(struct napi_struct *napi, int budget)
  234. {
  235. struct net_device *ndev = napi->dev;
  236. struct arc_emac_priv *priv = netdev_priv(ndev);
  237. unsigned int work_done;
  238. arc_emac_tx_clean(ndev);
  239. work_done = arc_emac_rx(ndev, budget);
  240. if (work_done < budget) {
  241. napi_complete(napi);
  242. arc_reg_or(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
  243. }
  244. return work_done;
  245. }
  246. /**
  247. * arc_emac_intr - Global interrupt handler for EMAC.
  248. * @irq: irq number.
  249. * @dev_instance: device instance.
  250. *
  251. * returns: IRQ_HANDLED for all cases.
  252. *
  253. * ARC EMAC has only 1 interrupt line, and depending on bits raised in
  254. * STATUS register we may tell what is a reason for interrupt to fire.
  255. */
  256. static irqreturn_t arc_emac_intr(int irq, void *dev_instance)
  257. {
  258. struct net_device *ndev = dev_instance;
  259. struct arc_emac_priv *priv = netdev_priv(ndev);
  260. struct net_device_stats *stats = &ndev->stats;
  261. unsigned int status;
  262. status = arc_reg_get(priv, R_STATUS);
  263. status &= ~MDIO_MASK;
  264. /* Reset all flags except "MDIO complete" */
  265. arc_reg_set(priv, R_STATUS, status);
  266. if (status & (RXINT_MASK | TXINT_MASK)) {
  267. if (likely(napi_schedule_prep(&priv->napi))) {
  268. arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK);
  269. __napi_schedule(&priv->napi);
  270. }
  271. }
  272. if (status & ERR_MASK) {
  273. /* MSER/RXCR/RXFR/RXFL interrupt fires on corresponding
  274. * 8-bit error counter overrun.
  275. */
  276. if (status & MSER_MASK) {
  277. stats->rx_missed_errors += 0x100;
  278. stats->rx_errors += 0x100;
  279. }
  280. if (status & RXCR_MASK) {
  281. stats->rx_crc_errors += 0x100;
  282. stats->rx_errors += 0x100;
  283. }
  284. if (status & RXFR_MASK) {
  285. stats->rx_frame_errors += 0x100;
  286. stats->rx_errors += 0x100;
  287. }
  288. if (status & RXFL_MASK) {
  289. stats->rx_over_errors += 0x100;
  290. stats->rx_errors += 0x100;
  291. }
  292. }
  293. return IRQ_HANDLED;
  294. }
  295. #ifdef CONFIG_NET_POLL_CONTROLLER
  296. static void arc_emac_poll_controller(struct net_device *dev)
  297. {
  298. disable_irq(dev->irq);
  299. arc_emac_intr(dev->irq, dev);
  300. enable_irq(dev->irq);
  301. }
  302. #endif
  303. /**
  304. * arc_emac_open - Open the network device.
  305. * @ndev: Pointer to the network device.
  306. *
  307. * returns: 0, on success or non-zero error value on failure.
  308. *
  309. * This function sets the MAC address, requests and enables an IRQ
  310. * for the EMAC device and starts the Tx queue.
  311. * It also connects to the phy device.
  312. */
  313. static int arc_emac_open(struct net_device *ndev)
  314. {
  315. struct arc_emac_priv *priv = netdev_priv(ndev);
  316. struct phy_device *phy_dev = ndev->phydev;
  317. int i;
  318. phy_dev->autoneg = AUTONEG_ENABLE;
  319. phy_dev->speed = 0;
  320. phy_dev->duplex = 0;
  321. phy_dev->advertising &= phy_dev->supported;
  322. priv->last_rx_bd = 0;
  323. /* Allocate and set buffers for Rx BD's */
  324. for (i = 0; i < RX_BD_NUM; i++) {
  325. dma_addr_t addr;
  326. unsigned int *last_rx_bd = &priv->last_rx_bd;
  327. struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd];
  328. struct buffer_state *rx_buff = &priv->rx_buff[*last_rx_bd];
  329. rx_buff->skb = netdev_alloc_skb_ip_align(ndev,
  330. EMAC_BUFFER_SIZE);
  331. if (unlikely(!rx_buff->skb))
  332. return -ENOMEM;
  333. addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
  334. EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
  335. if (dma_mapping_error(&ndev->dev, addr)) {
  336. netdev_err(ndev, "cannot dma map\n");
  337. dev_kfree_skb(rx_buff->skb);
  338. return -ENOMEM;
  339. }
  340. dma_unmap_addr_set(rx_buff, addr, addr);
  341. dma_unmap_len_set(rx_buff, len, EMAC_BUFFER_SIZE);
  342. rxbd->data = cpu_to_le32(addr);
  343. /* Make sure pointer to data buffer is set */
  344. wmb();
  345. /* Return ownership to EMAC */
  346. rxbd->info = cpu_to_le32(FOR_EMAC | EMAC_BUFFER_SIZE);
  347. *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM;
  348. }
  349. priv->txbd_curr = 0;
  350. priv->txbd_dirty = 0;
  351. /* Clean Tx BD's */
  352. memset(priv->txbd, 0, TX_RING_SZ);
  353. /* Initialize logical address filter */
  354. arc_reg_set(priv, R_LAFL, 0);
  355. arc_reg_set(priv, R_LAFH, 0);
  356. /* Set BD ring pointers for device side */
  357. arc_reg_set(priv, R_RX_RING, (unsigned int)priv->rxbd_dma);
  358. arc_reg_set(priv, R_TX_RING, (unsigned int)priv->txbd_dma);
  359. /* Enable interrupts */
  360. arc_reg_set(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
  361. /* Set CONTROL */
  362. arc_reg_set(priv, R_CTRL,
  363. (RX_BD_NUM << 24) | /* RX BD table length */
  364. (TX_BD_NUM << 16) | /* TX BD table length */
  365. TXRN_MASK | RXRN_MASK);
  366. napi_enable(&priv->napi);
  367. /* Enable EMAC */
  368. arc_reg_or(priv, R_CTRL, EN_MASK);
  369. phy_start_aneg(ndev->phydev);
  370. netif_start_queue(ndev);
  371. return 0;
  372. }
  373. /**
  374. * arc_emac_set_rx_mode - Change the receive filtering mode.
  375. * @ndev: Pointer to the network device.
  376. *
  377. * This function enables/disables promiscuous or all-multicast mode
  378. * and updates the multicast filtering list of the network device.
  379. */
  380. static void arc_emac_set_rx_mode(struct net_device *ndev)
  381. {
  382. struct arc_emac_priv *priv = netdev_priv(ndev);
  383. if (ndev->flags & IFF_PROMISC) {
  384. arc_reg_or(priv, R_CTRL, PROM_MASK);
  385. } else {
  386. arc_reg_clr(priv, R_CTRL, PROM_MASK);
  387. if (ndev->flags & IFF_ALLMULTI) {
  388. arc_reg_set(priv, R_LAFL, ~0);
  389. arc_reg_set(priv, R_LAFH, ~0);
  390. } else if (ndev->flags & IFF_MULTICAST) {
  391. struct netdev_hw_addr *ha;
  392. unsigned int filter[2] = { 0, 0 };
  393. int bit;
  394. netdev_for_each_mc_addr(ha, ndev) {
  395. bit = ether_crc_le(ETH_ALEN, ha->addr) >> 26;
  396. filter[bit >> 5] |= 1 << (bit & 31);
  397. }
  398. arc_reg_set(priv, R_LAFL, filter[0]);
  399. arc_reg_set(priv, R_LAFH, filter[1]);
  400. } else {
  401. arc_reg_set(priv, R_LAFL, 0);
  402. arc_reg_set(priv, R_LAFH, 0);
  403. }
  404. }
  405. }
  406. /**
  407. * arc_free_tx_queue - free skb from tx queue
  408. * @ndev: Pointer to the network device.
  409. *
  410. * This function must be called while EMAC disable
  411. */
  412. static void arc_free_tx_queue(struct net_device *ndev)
  413. {
  414. struct arc_emac_priv *priv = netdev_priv(ndev);
  415. unsigned int i;
  416. for (i = 0; i < TX_BD_NUM; i++) {
  417. struct arc_emac_bd *txbd = &priv->txbd[i];
  418. struct buffer_state *tx_buff = &priv->tx_buff[i];
  419. if (tx_buff->skb) {
  420. dma_unmap_single(&ndev->dev,
  421. dma_unmap_addr(tx_buff, addr),
  422. dma_unmap_len(tx_buff, len),
  423. DMA_TO_DEVICE);
  424. /* return the sk_buff to system */
  425. dev_kfree_skb_irq(tx_buff->skb);
  426. }
  427. txbd->info = 0;
  428. txbd->data = 0;
  429. tx_buff->skb = NULL;
  430. }
  431. }
  432. /**
  433. * arc_free_rx_queue - free skb from rx queue
  434. * @ndev: Pointer to the network device.
  435. *
  436. * This function must be called while EMAC disable
  437. */
  438. static void arc_free_rx_queue(struct net_device *ndev)
  439. {
  440. struct arc_emac_priv *priv = netdev_priv(ndev);
  441. unsigned int i;
  442. for (i = 0; i < RX_BD_NUM; i++) {
  443. struct arc_emac_bd *rxbd = &priv->rxbd[i];
  444. struct buffer_state *rx_buff = &priv->rx_buff[i];
  445. if (rx_buff->skb) {
  446. dma_unmap_single(&ndev->dev,
  447. dma_unmap_addr(rx_buff, addr),
  448. dma_unmap_len(rx_buff, len),
  449. DMA_FROM_DEVICE);
  450. /* return the sk_buff to system */
  451. dev_kfree_skb_irq(rx_buff->skb);
  452. }
  453. rxbd->info = 0;
  454. rxbd->data = 0;
  455. rx_buff->skb = NULL;
  456. }
  457. }
  458. /**
  459. * arc_emac_stop - Close the network device.
  460. * @ndev: Pointer to the network device.
  461. *
  462. * This function stops the Tx queue, disables interrupts and frees the IRQ for
  463. * the EMAC device.
  464. * It also disconnects the PHY device associated with the EMAC device.
  465. */
  466. static int arc_emac_stop(struct net_device *ndev)
  467. {
  468. struct arc_emac_priv *priv = netdev_priv(ndev);
  469. napi_disable(&priv->napi);
  470. netif_stop_queue(ndev);
  471. /* Disable interrupts */
  472. arc_reg_clr(priv, R_ENABLE, RXINT_MASK | TXINT_MASK | ERR_MASK);
  473. /* Disable EMAC */
  474. arc_reg_clr(priv, R_CTRL, EN_MASK);
  475. /* Return the sk_buff to system */
  476. arc_free_tx_queue(ndev);
  477. arc_free_rx_queue(ndev);
  478. return 0;
  479. }
  480. /**
  481. * arc_emac_stats - Get system network statistics.
  482. * @ndev: Pointer to net_device structure.
  483. *
  484. * Returns the address of the device statistics structure.
  485. * Statistics are updated in interrupt handler.
  486. */
  487. static struct net_device_stats *arc_emac_stats(struct net_device *ndev)
  488. {
  489. struct arc_emac_priv *priv = netdev_priv(ndev);
  490. struct net_device_stats *stats = &ndev->stats;
  491. unsigned long miss, rxerr;
  492. u8 rxcrc, rxfram, rxoflow;
  493. rxerr = arc_reg_get(priv, R_RXERR);
  494. miss = arc_reg_get(priv, R_MISS);
  495. rxcrc = rxerr;
  496. rxfram = rxerr >> 8;
  497. rxoflow = rxerr >> 16;
  498. stats->rx_errors += miss;
  499. stats->rx_errors += rxcrc + rxfram + rxoflow;
  500. stats->rx_over_errors += rxoflow;
  501. stats->rx_frame_errors += rxfram;
  502. stats->rx_crc_errors += rxcrc;
  503. stats->rx_missed_errors += miss;
  504. return stats;
  505. }
  506. /**
  507. * arc_emac_tx - Starts the data transmission.
  508. * @skb: sk_buff pointer that contains data to be Transmitted.
  509. * @ndev: Pointer to net_device structure.
  510. *
  511. * returns: NETDEV_TX_OK, on success
  512. * NETDEV_TX_BUSY, if any of the descriptors are not free.
  513. *
  514. * This function is invoked from upper layers to initiate transmission.
  515. */
  516. static int arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
  517. {
  518. struct arc_emac_priv *priv = netdev_priv(ndev);
  519. unsigned int len, *txbd_curr = &priv->txbd_curr;
  520. struct net_device_stats *stats = &ndev->stats;
  521. __le32 *info = &priv->txbd[*txbd_curr].info;
  522. dma_addr_t addr;
  523. if (skb_padto(skb, ETH_ZLEN))
  524. return NETDEV_TX_OK;
  525. len = max_t(unsigned int, ETH_ZLEN, skb->len);
  526. if (unlikely(!arc_emac_tx_avail(priv))) {
  527. netif_stop_queue(ndev);
  528. netdev_err(ndev, "BUG! Tx Ring full when queue awake!\n");
  529. return NETDEV_TX_BUSY;
  530. }
  531. addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
  532. DMA_TO_DEVICE);
  533. if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
  534. stats->tx_dropped++;
  535. stats->tx_errors++;
  536. dev_kfree_skb(skb);
  537. return NETDEV_TX_OK;
  538. }
  539. dma_unmap_addr_set(&priv->tx_buff[*txbd_curr], addr, addr);
  540. dma_unmap_len_set(&priv->tx_buff[*txbd_curr], len, len);
  541. priv->txbd[*txbd_curr].data = cpu_to_le32(addr);
  542. /* Make sure pointer to data buffer is set */
  543. wmb();
  544. skb_tx_timestamp(skb);
  545. *info = cpu_to_le32(FOR_EMAC | FIRST_OR_LAST_MASK | len);
  546. /* Make sure info word is set */
  547. wmb();
  548. priv->tx_buff[*txbd_curr].skb = skb;
  549. /* Increment index to point to the next BD */
  550. *txbd_curr = (*txbd_curr + 1) % TX_BD_NUM;
  551. /* Ensure that tx_clean() sees the new txbd_curr before
  552. * checking the queue status. This prevents an unneeded wake
  553. * of the queue in tx_clean().
  554. */
  555. smp_mb();
  556. if (!arc_emac_tx_avail(priv)) {
  557. netif_stop_queue(ndev);
  558. /* Refresh tx_dirty */
  559. smp_mb();
  560. if (arc_emac_tx_avail(priv))
  561. netif_start_queue(ndev);
  562. }
  563. arc_reg_set(priv, R_STATUS, TXPL_MASK);
  564. return NETDEV_TX_OK;
  565. }
  566. static void arc_emac_set_address_internal(struct net_device *ndev)
  567. {
  568. struct arc_emac_priv *priv = netdev_priv(ndev);
  569. unsigned int addr_low, addr_hi;
  570. addr_low = le32_to_cpu(*(__le32 *)&ndev->dev_addr[0]);
  571. addr_hi = le16_to_cpu(*(__le16 *)&ndev->dev_addr[4]);
  572. arc_reg_set(priv, R_ADDRL, addr_low);
  573. arc_reg_set(priv, R_ADDRH, addr_hi);
  574. }
  575. /**
  576. * arc_emac_set_address - Set the MAC address for this device.
  577. * @ndev: Pointer to net_device structure.
  578. * @p: 6 byte Address to be written as MAC address.
  579. *
  580. * This function copies the HW address from the sockaddr structure to the
  581. * net_device structure and updates the address in HW.
  582. *
  583. * returns: -EBUSY if the net device is busy or 0 if the address is set
  584. * successfully.
  585. */
  586. static int arc_emac_set_address(struct net_device *ndev, void *p)
  587. {
  588. struct sockaddr *addr = p;
  589. if (netif_running(ndev))
  590. return -EBUSY;
  591. if (!is_valid_ether_addr(addr->sa_data))
  592. return -EADDRNOTAVAIL;
  593. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  594. arc_emac_set_address_internal(ndev);
  595. return 0;
  596. }
  597. static const struct net_device_ops arc_emac_netdev_ops = {
  598. .ndo_open = arc_emac_open,
  599. .ndo_stop = arc_emac_stop,
  600. .ndo_start_xmit = arc_emac_tx,
  601. .ndo_set_mac_address = arc_emac_set_address,
  602. .ndo_get_stats = arc_emac_stats,
  603. .ndo_set_rx_mode = arc_emac_set_rx_mode,
  604. #ifdef CONFIG_NET_POLL_CONTROLLER
  605. .ndo_poll_controller = arc_emac_poll_controller,
  606. #endif
  607. };
  608. int arc_emac_probe(struct net_device *ndev, int interface)
  609. {
  610. struct device *dev = ndev->dev.parent;
  611. struct resource res_regs;
  612. struct device_node *phy_node;
  613. struct phy_device *phydev = NULL;
  614. struct arc_emac_priv *priv;
  615. const char *mac_addr;
  616. unsigned int id, clock_frequency, irq;
  617. int err;
  618. /* Get PHY from device tree */
  619. phy_node = of_parse_phandle(dev->of_node, "phy", 0);
  620. if (!phy_node) {
  621. dev_err(dev, "failed to retrieve phy description from device tree\n");
  622. return -ENODEV;
  623. }
  624. /* Get EMAC registers base address from device tree */
  625. err = of_address_to_resource(dev->of_node, 0, &res_regs);
  626. if (err) {
  627. dev_err(dev, "failed to retrieve registers base from device tree\n");
  628. err = -ENODEV;
  629. goto out_put_node;
  630. }
  631. /* Get IRQ from device tree */
  632. irq = irq_of_parse_and_map(dev->of_node, 0);
  633. if (!irq) {
  634. dev_err(dev, "failed to retrieve <irq> value from device tree\n");
  635. err = -ENODEV;
  636. goto out_put_node;
  637. }
  638. ndev->netdev_ops = &arc_emac_netdev_ops;
  639. ndev->ethtool_ops = &arc_emac_ethtool_ops;
  640. ndev->watchdog_timeo = TX_TIMEOUT;
  641. priv = netdev_priv(ndev);
  642. priv->dev = dev;
  643. priv->regs = devm_ioremap_resource(dev, &res_regs);
  644. if (IS_ERR(priv->regs)) {
  645. err = PTR_ERR(priv->regs);
  646. goto out_put_node;
  647. }
  648. dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs);
  649. if (priv->clk) {
  650. err = clk_prepare_enable(priv->clk);
  651. if (err) {
  652. dev_err(dev, "failed to enable clock\n");
  653. goto out_put_node;
  654. }
  655. clock_frequency = clk_get_rate(priv->clk);
  656. } else {
  657. /* Get CPU clock frequency from device tree */
  658. if (of_property_read_u32(dev->of_node, "clock-frequency",
  659. &clock_frequency)) {
  660. dev_err(dev, "failed to retrieve <clock-frequency> from device tree\n");
  661. err = -EINVAL;
  662. goto out_put_node;
  663. }
  664. }
  665. id = arc_reg_get(priv, R_ID);
  666. /* Check for EMAC revision 5 or 7, magic number */
  667. if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
  668. dev_err(dev, "ARC EMAC not detected, id=0x%x\n", id);
  669. err = -ENODEV;
  670. goto out_clken;
  671. }
  672. dev_info(dev, "ARC EMAC detected with id: 0x%x\n", id);
  673. /* Set poll rate so that it polls every 1 ms */
  674. arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
  675. ndev->irq = irq;
  676. dev_info(dev, "IRQ is %d\n", ndev->irq);
  677. /* Register interrupt handler for device */
  678. err = devm_request_irq(dev, ndev->irq, arc_emac_intr, 0,
  679. ndev->name, ndev);
  680. if (err) {
  681. dev_err(dev, "could not allocate IRQ\n");
  682. goto out_clken;
  683. }
  684. /* Get MAC address from device tree */
  685. mac_addr = of_get_mac_address(dev->of_node);
  686. if (mac_addr)
  687. memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
  688. else
  689. eth_hw_addr_random(ndev);
  690. arc_emac_set_address_internal(ndev);
  691. dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
  692. /* Do 1 allocation instead of 2 separate ones for Rx and Tx BD rings */
  693. priv->rxbd = dmam_alloc_coherent(dev, RX_RING_SZ + TX_RING_SZ,
  694. &priv->rxbd_dma, GFP_KERNEL);
  695. if (!priv->rxbd) {
  696. dev_err(dev, "failed to allocate data buffers\n");
  697. err = -ENOMEM;
  698. goto out_clken;
  699. }
  700. priv->txbd = priv->rxbd + RX_BD_NUM;
  701. priv->txbd_dma = priv->rxbd_dma + RX_RING_SZ;
  702. dev_dbg(dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
  703. (unsigned int)priv->rxbd_dma, (unsigned int)priv->txbd_dma);
  704. err = arc_mdio_probe(priv);
  705. if (err) {
  706. dev_err(dev, "failed to probe MII bus\n");
  707. goto out_clken;
  708. }
  709. phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
  710. interface);
  711. if (!phydev) {
  712. dev_err(dev, "of_phy_connect() failed\n");
  713. err = -ENODEV;
  714. goto out_mdio;
  715. }
  716. dev_info(dev, "connected to %s phy with id 0x%x\n",
  717. phydev->drv->name, phydev->phy_id);
  718. netif_napi_add(ndev, &priv->napi, arc_emac_poll, ARC_EMAC_NAPI_WEIGHT);
  719. err = register_netdev(ndev);
  720. if (err) {
  721. dev_err(dev, "failed to register network device\n");
  722. goto out_netif_api;
  723. }
  724. of_node_put(phy_node);
  725. return 0;
  726. out_netif_api:
  727. netif_napi_del(&priv->napi);
  728. phy_disconnect(phydev);
  729. out_mdio:
  730. arc_mdio_remove(priv);
  731. out_clken:
  732. if (priv->clk)
  733. clk_disable_unprepare(priv->clk);
  734. out_put_node:
  735. of_node_put(phy_node);
  736. return err;
  737. }
  738. EXPORT_SYMBOL_GPL(arc_emac_probe);
  739. int arc_emac_remove(struct net_device *ndev)
  740. {
  741. struct arc_emac_priv *priv = netdev_priv(ndev);
  742. phy_disconnect(ndev->phydev);
  743. arc_mdio_remove(priv);
  744. unregister_netdev(ndev);
  745. netif_napi_del(&priv->napi);
  746. if (!IS_ERR(priv->clk))
  747. clk_disable_unprepare(priv->clk);
  748. return 0;
  749. }
  750. EXPORT_SYMBOL_GPL(arc_emac_remove);
  751. MODULE_AUTHOR("Alexey Brodkin <abrodkin@synopsys.com>");
  752. MODULE_DESCRIPTION("ARC EMAC driver");
  753. MODULE_LICENSE("GPL");