emac.h 6.2 KB

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  1. /*
  2. * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * Registers and bits definitions of ARC EMAC
  5. */
  6. #ifndef ARC_EMAC_H
  7. #define ARC_EMAC_H
  8. #include <linux/device.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/netdevice.h>
  11. #include <linux/phy.h>
  12. #include <linux/clk.h>
  13. /* STATUS and ENABLE Register bit masks */
  14. #define TXINT_MASK (1 << 0) /* Transmit interrupt */
  15. #define RXINT_MASK (1 << 1) /* Receive interrupt */
  16. #define ERR_MASK (1 << 2) /* Error interrupt */
  17. #define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
  18. #define MSER_MASK (1 << 4) /* Missed packet counter error */
  19. #define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
  20. #define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
  21. #define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
  22. #define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
  23. #define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
  24. /* CONTROL Register bit masks */
  25. #define EN_MASK (1 << 0) /* VMAC enable */
  26. #define TXRN_MASK (1 << 3) /* TX enable */
  27. #define RXRN_MASK (1 << 4) /* RX enable */
  28. #define DSBC_MASK (1 << 8) /* Disable receive broadcast */
  29. #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
  30. #define PROM_MASK (1 << 11) /* Promiscuous mode */
  31. /* Buffer descriptor INFO bit masks */
  32. #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
  33. #define FIRST_MASK (1 << 16) /* First buffer in chain */
  34. #define LAST_MASK (1 << 17) /* Last buffer in chain */
  35. #define LEN_MASK 0x000007FF /* last 11 bits */
  36. #define CRLS (1 << 21)
  37. #define DEFR (1 << 22)
  38. #define DROP (1 << 23)
  39. #define RTRY (1 << 24)
  40. #define LTCL (1 << 28)
  41. #define UFLO (1 << 29)
  42. #define FOR_EMAC OWN_MASK
  43. #define FOR_CPU 0
  44. /* ARC EMAC register set combines entries for MAC and MDIO */
  45. enum {
  46. R_ID = 0,
  47. R_STATUS,
  48. R_ENABLE,
  49. R_CTRL,
  50. R_POLLRATE,
  51. R_RXERR,
  52. R_MISS,
  53. R_TX_RING,
  54. R_RX_RING,
  55. R_ADDRL,
  56. R_ADDRH,
  57. R_LAFL,
  58. R_LAFH,
  59. R_MDIO,
  60. };
  61. #define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
  62. #define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
  63. #define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
  64. /**
  65. * struct arc_emac_bd - EMAC buffer descriptor (BD).
  66. *
  67. * @info: Contains status information on the buffer itself.
  68. * @data: 32-bit byte addressable pointer to the packet data.
  69. */
  70. struct arc_emac_bd {
  71. __le32 info;
  72. dma_addr_t data;
  73. };
  74. /* Number of Rx/Tx BD's */
  75. #define RX_BD_NUM 128
  76. #define TX_BD_NUM 128
  77. #define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
  78. #define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
  79. /**
  80. * struct buffer_state - Stores Rx/Tx buffer state.
  81. * @sk_buff: Pointer to socket buffer.
  82. * @addr: Start address of DMA-mapped memory region.
  83. * @len: Length of DMA-mapped memory region.
  84. */
  85. struct buffer_state {
  86. struct sk_buff *skb;
  87. DEFINE_DMA_UNMAP_ADDR(addr);
  88. DEFINE_DMA_UNMAP_LEN(len);
  89. };
  90. struct arc_emac_mdio_bus_data {
  91. struct gpio_desc *reset_gpio;
  92. int msec;
  93. };
  94. /**
  95. * struct arc_emac_priv - Storage of EMAC's private information.
  96. * @dev: Pointer to the current device.
  97. * @phy_dev: Pointer to attached PHY device.
  98. * @bus: Pointer to the current MII bus.
  99. * @regs: Base address of EMAC memory-mapped control registers.
  100. * @napi: Structure for NAPI.
  101. * @rxbd: Pointer to Rx BD ring.
  102. * @txbd: Pointer to Tx BD ring.
  103. * @rxbd_dma: DMA handle for Rx BD ring.
  104. * @txbd_dma: DMA handle for Tx BD ring.
  105. * @rx_buff: Storage for Rx buffers states.
  106. * @tx_buff: Storage for Tx buffers states.
  107. * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
  108. * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
  109. * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
  110. * @link: PHY's last seen link state.
  111. * @duplex: PHY's last set duplex mode.
  112. * @speed: PHY's last set speed.
  113. */
  114. struct arc_emac_priv {
  115. const char *drv_name;
  116. const char *drv_version;
  117. void (*set_mac_speed)(void *priv, unsigned int speed);
  118. /* Devices */
  119. struct device *dev;
  120. struct mii_bus *bus;
  121. struct arc_emac_mdio_bus_data bus_data;
  122. void __iomem *regs;
  123. struct clk *clk;
  124. struct napi_struct napi;
  125. struct arc_emac_bd *rxbd;
  126. struct arc_emac_bd *txbd;
  127. dma_addr_t rxbd_dma;
  128. dma_addr_t txbd_dma;
  129. struct buffer_state rx_buff[RX_BD_NUM];
  130. struct buffer_state tx_buff[TX_BD_NUM];
  131. unsigned int txbd_curr;
  132. unsigned int txbd_dirty;
  133. unsigned int last_rx_bd;
  134. unsigned int link;
  135. unsigned int duplex;
  136. unsigned int speed;
  137. };
  138. /**
  139. * arc_reg_set - Sets EMAC register with provided value.
  140. * @priv: Pointer to ARC EMAC private data structure.
  141. * @reg: Register offset from base address.
  142. * @value: Value to set in register.
  143. */
  144. static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
  145. {
  146. iowrite32(value, priv->regs + reg * sizeof(int));
  147. }
  148. /**
  149. * arc_reg_get - Gets value of specified EMAC register.
  150. * @priv: Pointer to ARC EMAC private data structure.
  151. * @reg: Register offset from base address.
  152. *
  153. * returns: Value of requested register.
  154. */
  155. static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
  156. {
  157. return ioread32(priv->regs + reg * sizeof(int));
  158. }
  159. /**
  160. * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
  161. * @priv: Pointer to ARC EMAC private data structure.
  162. * @reg: Register offset from base address.
  163. * @mask: Mask to apply to specified register.
  164. *
  165. * This function reads initial register value, then applies provided mask
  166. * to it and then writes register back.
  167. */
  168. static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
  169. {
  170. unsigned int value = arc_reg_get(priv, reg);
  171. arc_reg_set(priv, reg, value | mask);
  172. }
  173. /**
  174. * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
  175. * @priv: Pointer to ARC EMAC private data structure.
  176. * @reg: Register offset from base address.
  177. * @mask: Mask to apply to specified register.
  178. *
  179. * This function reads initial register value, then applies provided mask
  180. * to it and then writes register back.
  181. */
  182. static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
  183. {
  184. unsigned int value = arc_reg_get(priv, reg);
  185. arc_reg_set(priv, reg, value & ~mask);
  186. }
  187. int arc_mdio_probe(struct arc_emac_priv *priv);
  188. int arc_mdio_remove(struct arc_emac_priv *priv);
  189. int arc_emac_probe(struct net_device *ndev, int interface);
  190. int arc_emac_remove(struct net_device *ndev);
  191. #endif /* ARC_EMAC_H */