qca8k.h 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189
  1. /*
  2. * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
  3. * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  4. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 and
  8. * only version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #ifndef __QCA8K_H
  16. #define __QCA8K_H
  17. #include <linux/delay.h>
  18. #include <linux/regmap.h>
  19. #define QCA8K_NUM_PORTS 7
  20. #define PHY_ID_QCA8337 0x004dd036
  21. #define QCA8K_ID_QCA8337 0x13
  22. #define QCA8K_NUM_FDB_RECORDS 2048
  23. #define QCA8K_CPU_PORT 0
  24. /* Global control registers */
  25. #define QCA8K_REG_MASK_CTRL 0x000
  26. #define QCA8K_MASK_CTRL_ID_M 0xff
  27. #define QCA8K_MASK_CTRL_ID_S 8
  28. #define QCA8K_REG_PORT0_PAD_CTRL 0x004
  29. #define QCA8K_REG_PORT5_PAD_CTRL 0x008
  30. #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
  31. #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
  32. #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \
  33. ((0x8 + (x & 0x3)) << 22)
  34. #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \
  35. ((0x10 + (x & 0x3)) << 20)
  36. #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
  37. #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
  38. #define QCA8K_REG_MODULE_EN 0x030
  39. #define QCA8K_MODULE_EN_MIB BIT(0)
  40. #define QCA8K_REG_MIB 0x034
  41. #define QCA8K_MIB_FLUSH BIT(24)
  42. #define QCA8K_MIB_CPU_KEEP BIT(20)
  43. #define QCA8K_MIB_BUSY BIT(17)
  44. #define QCA8K_GOL_MAC_ADDR0 0x60
  45. #define QCA8K_GOL_MAC_ADDR1 0x64
  46. #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
  47. #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
  48. #define QCA8K_PORT_STATUS_SPEED_10 0
  49. #define QCA8K_PORT_STATUS_SPEED_100 0x1
  50. #define QCA8K_PORT_STATUS_SPEED_1000 0x2
  51. #define QCA8K_PORT_STATUS_TXMAC BIT(2)
  52. #define QCA8K_PORT_STATUS_RXMAC BIT(3)
  53. #define QCA8K_PORT_STATUS_TXFLOW BIT(4)
  54. #define QCA8K_PORT_STATUS_RXFLOW BIT(5)
  55. #define QCA8K_PORT_STATUS_DUPLEX BIT(6)
  56. #define QCA8K_PORT_STATUS_LINK_UP BIT(8)
  57. #define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
  58. #define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
  59. #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
  60. #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
  61. #define QCA8K_PORT_HDR_CTRL_RX_S 2
  62. #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
  63. #define QCA8K_PORT_HDR_CTRL_TX_S 0
  64. #define QCA8K_PORT_HDR_CTRL_ALL 2
  65. #define QCA8K_PORT_HDR_CTRL_MGMT 1
  66. #define QCA8K_PORT_HDR_CTRL_NONE 0
  67. /* EEE control registers */
  68. #define QCA8K_REG_EEE_CTRL 0x100
  69. #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
  70. /* ACL registers */
  71. #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
  72. #define QCA8K_PORT_VLAN_CVID(x) (x << 16)
  73. #define QCA8K_PORT_VLAN_SVID(x) x
  74. #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
  75. #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
  76. #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
  77. /* Lookup registers */
  78. #define QCA8K_REG_ATU_DATA0 0x600
  79. #define QCA8K_ATU_ADDR2_S 24
  80. #define QCA8K_ATU_ADDR3_S 16
  81. #define QCA8K_ATU_ADDR4_S 8
  82. #define QCA8K_REG_ATU_DATA1 0x604
  83. #define QCA8K_ATU_PORT_M 0x7f
  84. #define QCA8K_ATU_PORT_S 16
  85. #define QCA8K_ATU_ADDR0_S 8
  86. #define QCA8K_REG_ATU_DATA2 0x608
  87. #define QCA8K_ATU_VID_M 0xfff
  88. #define QCA8K_ATU_VID_S 8
  89. #define QCA8K_ATU_STATUS_M 0xf
  90. #define QCA8K_ATU_STATUS_STATIC 0xf
  91. #define QCA8K_REG_ATU_FUNC 0x60c
  92. #define QCA8K_ATU_FUNC_BUSY BIT(31)
  93. #define QCA8K_ATU_FUNC_PORT_EN BIT(14)
  94. #define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
  95. #define QCA8K_ATU_FUNC_FULL BIT(12)
  96. #define QCA8K_ATU_FUNC_PORT_M 0xf
  97. #define QCA8K_ATU_FUNC_PORT_S 8
  98. #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
  99. #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
  100. #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
  101. #define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
  102. #define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
  103. #define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
  104. #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
  105. #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
  106. #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
  107. #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
  108. #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
  109. #define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
  110. #define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
  111. #define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
  112. #define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
  113. #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
  114. #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
  115. /* Pkt edit registers */
  116. #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
  117. /* L3 registers */
  118. #define QCA8K_HROUTER_CONTROL 0xe00
  119. #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
  120. #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
  121. #define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
  122. #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
  123. #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
  124. #define QCA8K_HNAT_CONTROL 0xe38
  125. /* MIB registers */
  126. #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
  127. /* QCA specific MII registers */
  128. #define MII_ATH_MMD_ADDR 0x0d
  129. #define MII_ATH_MMD_DATA 0x0e
  130. enum {
  131. QCA8K_PORT_SPEED_10M = 0,
  132. QCA8K_PORT_SPEED_100M = 1,
  133. QCA8K_PORT_SPEED_1000M = 2,
  134. QCA8K_PORT_SPEED_ERR = 3,
  135. };
  136. enum qca8k_fdb_cmd {
  137. QCA8K_FDB_FLUSH = 1,
  138. QCA8K_FDB_LOAD = 2,
  139. QCA8K_FDB_PURGE = 3,
  140. QCA8K_FDB_NEXT = 6,
  141. QCA8K_FDB_SEARCH = 7,
  142. };
  143. struct ar8xxx_port_status {
  144. struct ethtool_eee eee;
  145. struct net_device *bridge_dev;
  146. int enabled;
  147. };
  148. struct qca8k_priv {
  149. struct regmap *regmap;
  150. struct mii_bus *bus;
  151. struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
  152. struct dsa_switch *ds;
  153. struct mutex reg_mutex;
  154. struct device *dev;
  155. };
  156. struct qca8k_mib_desc {
  157. unsigned int size;
  158. unsigned int offset;
  159. const char *name;
  160. };
  161. struct qca8k_fdb {
  162. u16 vid;
  163. u8 port_mask;
  164. u8 aging;
  165. u8 mac[6];
  166. };
  167. #endif /* __QCA8K_H */