omap-usb-tll.c 13 KB

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  1. /**
  2. * omap-usb-tll.c - The USB TLL driver for OMAP EHCI & OHCI
  3. *
  4. * Copyright (C) 2012-2013 Texas Instruments Incorporated - http://www.ti.com
  5. * Author: Keshava Munegowda <keshava_mgowda@ti.com>
  6. * Author: Roger Quadros <rogerq@ti.com>
  7. *
  8. * This program is free software: you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 of
  10. * the License as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/types.h>
  23. #include <linux/slab.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/clk.h>
  27. #include <linux/io.h>
  28. #include <linux/err.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/platform_data/usb-omap.h>
  31. #include <linux/of.h>
  32. #include "omap-usb.h"
  33. #define USBTLL_DRIVER_NAME "usbhs_tll"
  34. /* TLL Register Set */
  35. #define OMAP_USBTLL_REVISION (0x00)
  36. #define OMAP_USBTLL_SYSCONFIG (0x10)
  37. #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
  38. #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
  39. #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
  40. #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
  41. #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
  42. #define OMAP_USBTLL_SYSSTATUS (0x14)
  43. #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
  44. #define OMAP_USBTLL_IRQSTATUS (0x18)
  45. #define OMAP_USBTLL_IRQENABLE (0x1C)
  46. #define OMAP_TLL_SHARED_CONF (0x30)
  47. #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
  48. #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
  49. #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
  50. #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
  51. #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
  52. #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
  53. #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
  54. #define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16)
  55. #define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15)
  56. #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
  57. #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
  58. #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
  59. #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
  60. #define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI (2 << 1)
  61. #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
  62. #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
  63. #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
  64. #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
  65. #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
  66. #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
  67. #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
  68. #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
  69. #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
  70. #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
  71. #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
  72. #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
  73. #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
  74. #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
  75. #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
  76. #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
  77. #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
  78. #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
  79. #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
  80. #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
  81. #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
  82. #define OMAP_REV2_TLL_CHANNEL_COUNT 2
  83. #define OMAP_TLL_CHANNEL_COUNT 3
  84. #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
  85. #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
  86. #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
  87. /* Values of USBTLL_REVISION - Note: these are not given in the TRM */
  88. #define OMAP_USBTLL_REV1 0x00000015 /* OMAP3 */
  89. #define OMAP_USBTLL_REV2 0x00000018 /* OMAP 3630 */
  90. #define OMAP_USBTLL_REV3 0x00000004 /* OMAP4 */
  91. #define OMAP_USBTLL_REV4 0x00000006 /* OMAP5 */
  92. #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
  93. /* only PHY and UNUSED modes don't need TLL */
  94. #define omap_usb_mode_needs_tll(x) ((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\
  95. (x) != OMAP_EHCI_PORT_MODE_PHY)
  96. struct usbtll_omap {
  97. int nch; /* num. of channels */
  98. struct clk **ch_clk;
  99. void __iomem *base;
  100. };
  101. /*-------------------------------------------------------------------------*/
  102. static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME;
  103. static struct device *tll_dev;
  104. static DEFINE_SPINLOCK(tll_lock); /* serialize access to tll_dev */
  105. /*-------------------------------------------------------------------------*/
  106. static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
  107. {
  108. writel_relaxed(val, base + reg);
  109. }
  110. static inline u32 usbtll_read(void __iomem *base, u32 reg)
  111. {
  112. return readl_relaxed(base + reg);
  113. }
  114. static inline void usbtll_writeb(void __iomem *base, u8 reg, u8 val)
  115. {
  116. writeb_relaxed(val, base + reg);
  117. }
  118. static inline u8 usbtll_readb(void __iomem *base, u8 reg)
  119. {
  120. return readb_relaxed(base + reg);
  121. }
  122. /*-------------------------------------------------------------------------*/
  123. static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
  124. {
  125. switch (pmode) {
  126. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
  127. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
  128. case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
  129. case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
  130. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
  131. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
  132. case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
  133. case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
  134. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
  135. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
  136. return true;
  137. default:
  138. return false;
  139. }
  140. }
  141. /*
  142. * convert the port-mode enum to a value we can use in the FSLSMODE
  143. * field of USBTLL_CHANNEL_CONF
  144. */
  145. static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
  146. {
  147. switch (mode) {
  148. case OMAP_USBHS_PORT_MODE_UNUSED:
  149. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
  150. return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
  151. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
  152. return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
  153. case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
  154. return OMAP_TLL_FSLSMODE_3PIN_PHY;
  155. case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
  156. return OMAP_TLL_FSLSMODE_4PIN_PHY;
  157. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
  158. return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
  159. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
  160. return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
  161. case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
  162. return OMAP_TLL_FSLSMODE_3PIN_TLL;
  163. case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
  164. return OMAP_TLL_FSLSMODE_4PIN_TLL;
  165. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
  166. return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
  167. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
  168. return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
  169. default:
  170. pr_warn("Invalid port mode, using default\n");
  171. return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
  172. }
  173. }
  174. /**
  175. * usbtll_omap_probe - initialize TI-based HCDs
  176. *
  177. * Allocates basic resources for this USB host controller.
  178. */
  179. static int usbtll_omap_probe(struct platform_device *pdev)
  180. {
  181. struct device *dev = &pdev->dev;
  182. struct resource *res;
  183. struct usbtll_omap *tll;
  184. int ret = 0;
  185. int i, ver;
  186. dev_dbg(dev, "starting TI HSUSB TLL Controller\n");
  187. tll = devm_kzalloc(dev, sizeof(struct usbtll_omap), GFP_KERNEL);
  188. if (!tll) {
  189. dev_err(dev, "Memory allocation failed\n");
  190. return -ENOMEM;
  191. }
  192. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  193. tll->base = devm_ioremap_resource(dev, res);
  194. if (IS_ERR(tll->base))
  195. return PTR_ERR(tll->base);
  196. platform_set_drvdata(pdev, tll);
  197. pm_runtime_enable(dev);
  198. pm_runtime_get_sync(dev);
  199. ver = usbtll_read(tll->base, OMAP_USBTLL_REVISION);
  200. switch (ver) {
  201. case OMAP_USBTLL_REV1:
  202. case OMAP_USBTLL_REV4:
  203. tll->nch = OMAP_TLL_CHANNEL_COUNT;
  204. break;
  205. case OMAP_USBTLL_REV2:
  206. case OMAP_USBTLL_REV3:
  207. tll->nch = OMAP_REV2_TLL_CHANNEL_COUNT;
  208. break;
  209. default:
  210. tll->nch = OMAP_TLL_CHANNEL_COUNT;
  211. dev_dbg(dev,
  212. "USB TLL Rev : 0x%x not recognized, assuming %d channels\n",
  213. ver, tll->nch);
  214. break;
  215. }
  216. tll->ch_clk = devm_kzalloc(dev, sizeof(struct clk *) * tll->nch,
  217. GFP_KERNEL);
  218. if (!tll->ch_clk) {
  219. ret = -ENOMEM;
  220. dev_err(dev, "Couldn't allocate memory for channel clocks\n");
  221. goto err_clk_alloc;
  222. }
  223. for (i = 0; i < tll->nch; i++) {
  224. char clkname[] = "usb_tll_hs_usb_chx_clk";
  225. snprintf(clkname, sizeof(clkname),
  226. "usb_tll_hs_usb_ch%d_clk", i);
  227. tll->ch_clk[i] = clk_get(dev, clkname);
  228. if (IS_ERR(tll->ch_clk[i]))
  229. dev_dbg(dev, "can't get clock : %s\n", clkname);
  230. else
  231. clk_prepare(tll->ch_clk[i]);
  232. }
  233. pm_runtime_put_sync(dev);
  234. /* only after this can omap_tll_enable/disable work */
  235. spin_lock(&tll_lock);
  236. tll_dev = dev;
  237. spin_unlock(&tll_lock);
  238. return 0;
  239. err_clk_alloc:
  240. pm_runtime_put_sync(dev);
  241. pm_runtime_disable(dev);
  242. return ret;
  243. }
  244. /**
  245. * usbtll_omap_remove - shutdown processing for UHH & TLL HCDs
  246. * @pdev: USB Host Controller being removed
  247. *
  248. * Reverses the effect of usbtll_omap_probe().
  249. */
  250. static int usbtll_omap_remove(struct platform_device *pdev)
  251. {
  252. struct usbtll_omap *tll = platform_get_drvdata(pdev);
  253. int i;
  254. spin_lock(&tll_lock);
  255. tll_dev = NULL;
  256. spin_unlock(&tll_lock);
  257. for (i = 0; i < tll->nch; i++) {
  258. if (!IS_ERR(tll->ch_clk[i])) {
  259. clk_unprepare(tll->ch_clk[i]);
  260. clk_put(tll->ch_clk[i]);
  261. }
  262. }
  263. pm_runtime_disable(&pdev->dev);
  264. return 0;
  265. }
  266. static const struct of_device_id usbtll_omap_dt_ids[] = {
  267. { .compatible = "ti,usbhs-tll" },
  268. { }
  269. };
  270. MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids);
  271. static struct platform_driver usbtll_omap_driver = {
  272. .driver = {
  273. .name = (char *)usbtll_driver_name,
  274. .of_match_table = usbtll_omap_dt_ids,
  275. },
  276. .probe = usbtll_omap_probe,
  277. .remove = usbtll_omap_remove,
  278. };
  279. int omap_tll_init(struct usbhs_omap_platform_data *pdata)
  280. {
  281. int i;
  282. bool needs_tll;
  283. unsigned reg;
  284. struct usbtll_omap *tll;
  285. if (!tll_dev)
  286. return -ENODEV;
  287. pm_runtime_get_sync(tll_dev);
  288. spin_lock(&tll_lock);
  289. tll = dev_get_drvdata(tll_dev);
  290. needs_tll = false;
  291. for (i = 0; i < tll->nch; i++)
  292. needs_tll |= omap_usb_mode_needs_tll(pdata->port_mode[i]);
  293. if (needs_tll) {
  294. void __iomem *base = tll->base;
  295. /* Program Common TLL register */
  296. reg = usbtll_read(base, OMAP_TLL_SHARED_CONF);
  297. reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
  298. | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
  299. reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
  300. reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
  301. usbtll_write(base, OMAP_TLL_SHARED_CONF, reg);
  302. /* Enable channels now */
  303. for (i = 0; i < tll->nch; i++) {
  304. reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i));
  305. if (is_ohci_port(pdata->port_mode[i])) {
  306. reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
  307. << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
  308. reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
  309. } else if (pdata->port_mode[i] ==
  310. OMAP_EHCI_PORT_MODE_TLL) {
  311. /*
  312. * Disable AutoIdle, BitStuffing
  313. * and use SDR Mode
  314. */
  315. reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
  316. | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
  317. reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
  318. } else if (pdata->port_mode[i] ==
  319. OMAP_EHCI_PORT_MODE_HSIC) {
  320. /*
  321. * HSIC Mode requires UTMI port configurations
  322. */
  323. reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS
  324. | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
  325. | OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
  326. | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
  327. } else {
  328. continue;
  329. }
  330. reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
  331. usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg);
  332. usbtll_writeb(base,
  333. OMAP_TLL_ULPI_SCRATCH_REGISTER(i),
  334. 0xbe);
  335. }
  336. }
  337. spin_unlock(&tll_lock);
  338. pm_runtime_put_sync(tll_dev);
  339. return 0;
  340. }
  341. EXPORT_SYMBOL_GPL(omap_tll_init);
  342. int omap_tll_enable(struct usbhs_omap_platform_data *pdata)
  343. {
  344. int i;
  345. struct usbtll_omap *tll;
  346. if (!tll_dev)
  347. return -ENODEV;
  348. pm_runtime_get_sync(tll_dev);
  349. spin_lock(&tll_lock);
  350. tll = dev_get_drvdata(tll_dev);
  351. for (i = 0; i < tll->nch; i++) {
  352. if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
  353. int r;
  354. if (IS_ERR(tll->ch_clk[i]))
  355. continue;
  356. r = clk_enable(tll->ch_clk[i]);
  357. if (r) {
  358. dev_err(tll_dev,
  359. "Error enabling ch %d clock: %d\n", i, r);
  360. }
  361. }
  362. }
  363. spin_unlock(&tll_lock);
  364. return 0;
  365. }
  366. EXPORT_SYMBOL_GPL(omap_tll_enable);
  367. int omap_tll_disable(struct usbhs_omap_platform_data *pdata)
  368. {
  369. int i;
  370. struct usbtll_omap *tll;
  371. if (!tll_dev)
  372. return -ENODEV;
  373. spin_lock(&tll_lock);
  374. tll = dev_get_drvdata(tll_dev);
  375. for (i = 0; i < tll->nch; i++) {
  376. if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
  377. if (!IS_ERR(tll->ch_clk[i]))
  378. clk_disable(tll->ch_clk[i]);
  379. }
  380. }
  381. spin_unlock(&tll_lock);
  382. pm_runtime_put_sync(tll_dev);
  383. return 0;
  384. }
  385. EXPORT_SYMBOL_GPL(omap_tll_disable);
  386. MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
  387. MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
  388. MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
  389. MODULE_LICENSE("GPL v2");
  390. MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");
  391. static int __init omap_usbtll_drvinit(void)
  392. {
  393. return platform_driver_register(&usbtll_omap_driver);
  394. }
  395. /*
  396. * init before usbhs core driver;
  397. * The usbtll driver should be initialized before
  398. * the usbhs core driver probe function is called.
  399. */
  400. fs_initcall(omap_usbtll_drvinit);
  401. static void __exit omap_usbtll_drvexit(void)
  402. {
  403. platform_driver_unregister(&usbtll_omap_driver);
  404. }
  405. module_exit(omap_usbtll_drvexit);