max8925-core.c 23 KB

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  1. /*
  2. * Base driver for Maxim MAX8925
  3. *
  4. * Copyright (C) 2009-2010 Marvell International Ltd.
  5. * Haojian Zhuang <haojian.zhuang@marvell.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/i2c.h>
  14. #include <linux/irq.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/regulator/machine.h>
  19. #include <linux/mfd/core.h>
  20. #include <linux/mfd/max8925.h>
  21. #include <linux/of.h>
  22. #include <linux/of_platform.h>
  23. static struct resource bk_resources[] = {
  24. { 0x84, 0x84, "mode control", IORESOURCE_REG, },
  25. { 0x85, 0x85, "control", IORESOURCE_REG, },
  26. };
  27. static struct mfd_cell bk_devs[] = {
  28. {
  29. .name = "max8925-backlight",
  30. .num_resources = ARRAY_SIZE(bk_resources),
  31. .resources = &bk_resources[0],
  32. .id = -1,
  33. },
  34. };
  35. static struct resource touch_resources[] = {
  36. {
  37. .name = "max8925-tsc",
  38. .start = MAX8925_TSC_IRQ,
  39. .end = MAX8925_ADC_RES_END,
  40. .flags = IORESOURCE_REG,
  41. },
  42. };
  43. static const struct mfd_cell touch_devs[] = {
  44. {
  45. .name = "max8925-touch",
  46. .num_resources = 1,
  47. .resources = &touch_resources[0],
  48. .id = -1,
  49. },
  50. };
  51. static struct resource power_supply_resources[] = {
  52. {
  53. .name = "max8925-power",
  54. .start = MAX8925_CHG_IRQ1,
  55. .end = MAX8925_CHG_IRQ1_MASK,
  56. .flags = IORESOURCE_REG,
  57. },
  58. };
  59. static const struct mfd_cell power_devs[] = {
  60. {
  61. .name = "max8925-power",
  62. .num_resources = 1,
  63. .resources = &power_supply_resources[0],
  64. .id = -1,
  65. },
  66. };
  67. static struct resource rtc_resources[] = {
  68. {
  69. .name = "max8925-rtc",
  70. .start = MAX8925_IRQ_RTC_ALARM0,
  71. .end = MAX8925_IRQ_RTC_ALARM0,
  72. .flags = IORESOURCE_IRQ,
  73. },
  74. };
  75. static const struct mfd_cell rtc_devs[] = {
  76. {
  77. .name = "max8925-rtc",
  78. .num_resources = 1,
  79. .resources = &rtc_resources[0],
  80. .id = -1,
  81. },
  82. };
  83. static struct resource onkey_resources[] = {
  84. {
  85. .name = "max8925-onkey",
  86. .start = MAX8925_IRQ_GPM_SW_R,
  87. .end = MAX8925_IRQ_GPM_SW_R,
  88. .flags = IORESOURCE_IRQ,
  89. }, {
  90. .name = "max8925-onkey",
  91. .start = MAX8925_IRQ_GPM_SW_F,
  92. .end = MAX8925_IRQ_GPM_SW_F,
  93. .flags = IORESOURCE_IRQ,
  94. },
  95. };
  96. static const struct mfd_cell onkey_devs[] = {
  97. {
  98. .name = "max8925-onkey",
  99. .num_resources = 2,
  100. .resources = &onkey_resources[0],
  101. .id = -1,
  102. },
  103. };
  104. static struct resource sd1_resources[] = {
  105. {0x06, 0x06, "sdv", IORESOURCE_REG, },
  106. };
  107. static struct resource sd2_resources[] = {
  108. {0x09, 0x09, "sdv", IORESOURCE_REG, },
  109. };
  110. static struct resource sd3_resources[] = {
  111. {0x0c, 0x0c, "sdv", IORESOURCE_REG, },
  112. };
  113. static struct resource ldo1_resources[] = {
  114. {0x1a, 0x1a, "ldov", IORESOURCE_REG, },
  115. };
  116. static struct resource ldo2_resources[] = {
  117. {0x1e, 0x1e, "ldov", IORESOURCE_REG, },
  118. };
  119. static struct resource ldo3_resources[] = {
  120. {0x22, 0x22, "ldov", IORESOURCE_REG, },
  121. };
  122. static struct resource ldo4_resources[] = {
  123. {0x26, 0x26, "ldov", IORESOURCE_REG, },
  124. };
  125. static struct resource ldo5_resources[] = {
  126. {0x2a, 0x2a, "ldov", IORESOURCE_REG, },
  127. };
  128. static struct resource ldo6_resources[] = {
  129. {0x2e, 0x2e, "ldov", IORESOURCE_REG, },
  130. };
  131. static struct resource ldo7_resources[] = {
  132. {0x32, 0x32, "ldov", IORESOURCE_REG, },
  133. };
  134. static struct resource ldo8_resources[] = {
  135. {0x36, 0x36, "ldov", IORESOURCE_REG, },
  136. };
  137. static struct resource ldo9_resources[] = {
  138. {0x3a, 0x3a, "ldov", IORESOURCE_REG, },
  139. };
  140. static struct resource ldo10_resources[] = {
  141. {0x3e, 0x3e, "ldov", IORESOURCE_REG, },
  142. };
  143. static struct resource ldo11_resources[] = {
  144. {0x42, 0x42, "ldov", IORESOURCE_REG, },
  145. };
  146. static struct resource ldo12_resources[] = {
  147. {0x46, 0x46, "ldov", IORESOURCE_REG, },
  148. };
  149. static struct resource ldo13_resources[] = {
  150. {0x4a, 0x4a, "ldov", IORESOURCE_REG, },
  151. };
  152. static struct resource ldo14_resources[] = {
  153. {0x4e, 0x4e, "ldov", IORESOURCE_REG, },
  154. };
  155. static struct resource ldo15_resources[] = {
  156. {0x52, 0x52, "ldov", IORESOURCE_REG, },
  157. };
  158. static struct resource ldo16_resources[] = {
  159. {0x12, 0x12, "ldov", IORESOURCE_REG, },
  160. };
  161. static struct resource ldo17_resources[] = {
  162. {0x16, 0x16, "ldov", IORESOURCE_REG, },
  163. };
  164. static struct resource ldo18_resources[] = {
  165. {0x74, 0x74, "ldov", IORESOURCE_REG, },
  166. };
  167. static struct resource ldo19_resources[] = {
  168. {0x5e, 0x5e, "ldov", IORESOURCE_REG, },
  169. };
  170. static struct resource ldo20_resources[] = {
  171. {0x9e, 0x9e, "ldov", IORESOURCE_REG, },
  172. };
  173. static struct mfd_cell reg_devs[] = {
  174. {
  175. .name = "max8925-regulator",
  176. .id = 0,
  177. .num_resources = ARRAY_SIZE(sd1_resources),
  178. .resources = sd1_resources,
  179. }, {
  180. .name = "max8925-regulator",
  181. .id = 1,
  182. .num_resources = ARRAY_SIZE(sd2_resources),
  183. .resources = sd2_resources,
  184. }, {
  185. .name = "max8925-regulator",
  186. .id = 2,
  187. .num_resources = ARRAY_SIZE(sd3_resources),
  188. .resources = sd3_resources,
  189. }, {
  190. .name = "max8925-regulator",
  191. .id = 3,
  192. .num_resources = ARRAY_SIZE(ldo1_resources),
  193. .resources = ldo1_resources,
  194. }, {
  195. .name = "max8925-regulator",
  196. .id = 4,
  197. .num_resources = ARRAY_SIZE(ldo2_resources),
  198. .resources = ldo2_resources,
  199. }, {
  200. .name = "max8925-regulator",
  201. .id = 5,
  202. .num_resources = ARRAY_SIZE(ldo3_resources),
  203. .resources = ldo3_resources,
  204. }, {
  205. .name = "max8925-regulator",
  206. .id = 6,
  207. .num_resources = ARRAY_SIZE(ldo4_resources),
  208. .resources = ldo4_resources,
  209. }, {
  210. .name = "max8925-regulator",
  211. .id = 7,
  212. .num_resources = ARRAY_SIZE(ldo5_resources),
  213. .resources = ldo5_resources,
  214. }, {
  215. .name = "max8925-regulator",
  216. .id = 8,
  217. .num_resources = ARRAY_SIZE(ldo6_resources),
  218. .resources = ldo6_resources,
  219. }, {
  220. .name = "max8925-regulator",
  221. .id = 9,
  222. .num_resources = ARRAY_SIZE(ldo7_resources),
  223. .resources = ldo7_resources,
  224. }, {
  225. .name = "max8925-regulator",
  226. .id = 10,
  227. .num_resources = ARRAY_SIZE(ldo8_resources),
  228. .resources = ldo8_resources,
  229. }, {
  230. .name = "max8925-regulator",
  231. .id = 11,
  232. .num_resources = ARRAY_SIZE(ldo9_resources),
  233. .resources = ldo9_resources,
  234. }, {
  235. .name = "max8925-regulator",
  236. .id = 12,
  237. .num_resources = ARRAY_SIZE(ldo10_resources),
  238. .resources = ldo10_resources,
  239. }, {
  240. .name = "max8925-regulator",
  241. .id = 13,
  242. .num_resources = ARRAY_SIZE(ldo11_resources),
  243. .resources = ldo11_resources,
  244. }, {
  245. .name = "max8925-regulator",
  246. .id = 14,
  247. .num_resources = ARRAY_SIZE(ldo12_resources),
  248. .resources = ldo12_resources,
  249. }, {
  250. .name = "max8925-regulator",
  251. .id = 15,
  252. .num_resources = ARRAY_SIZE(ldo13_resources),
  253. .resources = ldo13_resources,
  254. }, {
  255. .name = "max8925-regulator",
  256. .id = 16,
  257. .num_resources = ARRAY_SIZE(ldo14_resources),
  258. .resources = ldo14_resources,
  259. }, {
  260. .name = "max8925-regulator",
  261. .id = 17,
  262. .num_resources = ARRAY_SIZE(ldo15_resources),
  263. .resources = ldo15_resources,
  264. }, {
  265. .name = "max8925-regulator",
  266. .id = 18,
  267. .num_resources = ARRAY_SIZE(ldo16_resources),
  268. .resources = ldo16_resources,
  269. }, {
  270. .name = "max8925-regulator",
  271. .id = 19,
  272. .num_resources = ARRAY_SIZE(ldo17_resources),
  273. .resources = ldo17_resources,
  274. }, {
  275. .name = "max8925-regulator",
  276. .id = 20,
  277. .num_resources = ARRAY_SIZE(ldo18_resources),
  278. .resources = ldo18_resources,
  279. }, {
  280. .name = "max8925-regulator",
  281. .id = 21,
  282. .num_resources = ARRAY_SIZE(ldo19_resources),
  283. .resources = ldo19_resources,
  284. }, {
  285. .name = "max8925-regulator",
  286. .id = 22,
  287. .num_resources = ARRAY_SIZE(ldo20_resources),
  288. .resources = ldo20_resources,
  289. },
  290. };
  291. enum {
  292. FLAGS_ADC = 1, /* register in ADC component */
  293. FLAGS_RTC, /* register in RTC component */
  294. };
  295. struct max8925_irq_data {
  296. int reg;
  297. int mask_reg;
  298. int enable; /* enable or not */
  299. int offs; /* bit offset in mask register */
  300. int flags;
  301. int tsc_irq;
  302. };
  303. static struct max8925_irq_data max8925_irqs[] = {
  304. [MAX8925_IRQ_VCHG_DC_OVP] = {
  305. .reg = MAX8925_CHG_IRQ1,
  306. .mask_reg = MAX8925_CHG_IRQ1_MASK,
  307. .offs = 1 << 0,
  308. },
  309. [MAX8925_IRQ_VCHG_DC_F] = {
  310. .reg = MAX8925_CHG_IRQ1,
  311. .mask_reg = MAX8925_CHG_IRQ1_MASK,
  312. .offs = 1 << 1,
  313. },
  314. [MAX8925_IRQ_VCHG_DC_R] = {
  315. .reg = MAX8925_CHG_IRQ1,
  316. .mask_reg = MAX8925_CHG_IRQ1_MASK,
  317. .offs = 1 << 2,
  318. },
  319. [MAX8925_IRQ_VCHG_THM_OK_R] = {
  320. .reg = MAX8925_CHG_IRQ2,
  321. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  322. .offs = 1 << 0,
  323. },
  324. [MAX8925_IRQ_VCHG_THM_OK_F] = {
  325. .reg = MAX8925_CHG_IRQ2,
  326. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  327. .offs = 1 << 1,
  328. },
  329. [MAX8925_IRQ_VCHG_SYSLOW_F] = {
  330. .reg = MAX8925_CHG_IRQ2,
  331. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  332. .offs = 1 << 2,
  333. },
  334. [MAX8925_IRQ_VCHG_SYSLOW_R] = {
  335. .reg = MAX8925_CHG_IRQ2,
  336. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  337. .offs = 1 << 3,
  338. },
  339. [MAX8925_IRQ_VCHG_RST] = {
  340. .reg = MAX8925_CHG_IRQ2,
  341. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  342. .offs = 1 << 4,
  343. },
  344. [MAX8925_IRQ_VCHG_DONE] = {
  345. .reg = MAX8925_CHG_IRQ2,
  346. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  347. .offs = 1 << 5,
  348. },
  349. [MAX8925_IRQ_VCHG_TOPOFF] = {
  350. .reg = MAX8925_CHG_IRQ2,
  351. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  352. .offs = 1 << 6,
  353. },
  354. [MAX8925_IRQ_VCHG_TMR_FAULT] = {
  355. .reg = MAX8925_CHG_IRQ2,
  356. .mask_reg = MAX8925_CHG_IRQ2_MASK,
  357. .offs = 1 << 7,
  358. },
  359. [MAX8925_IRQ_GPM_RSTIN] = {
  360. .reg = MAX8925_ON_OFF_IRQ1,
  361. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  362. .offs = 1 << 0,
  363. },
  364. [MAX8925_IRQ_GPM_MPL] = {
  365. .reg = MAX8925_ON_OFF_IRQ1,
  366. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  367. .offs = 1 << 1,
  368. },
  369. [MAX8925_IRQ_GPM_SW_3SEC] = {
  370. .reg = MAX8925_ON_OFF_IRQ1,
  371. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  372. .offs = 1 << 2,
  373. },
  374. [MAX8925_IRQ_GPM_EXTON_F] = {
  375. .reg = MAX8925_ON_OFF_IRQ1,
  376. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  377. .offs = 1 << 3,
  378. },
  379. [MAX8925_IRQ_GPM_EXTON_R] = {
  380. .reg = MAX8925_ON_OFF_IRQ1,
  381. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  382. .offs = 1 << 4,
  383. },
  384. [MAX8925_IRQ_GPM_SW_1SEC] = {
  385. .reg = MAX8925_ON_OFF_IRQ1,
  386. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  387. .offs = 1 << 5,
  388. },
  389. [MAX8925_IRQ_GPM_SW_F] = {
  390. .reg = MAX8925_ON_OFF_IRQ1,
  391. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  392. .offs = 1 << 6,
  393. },
  394. [MAX8925_IRQ_GPM_SW_R] = {
  395. .reg = MAX8925_ON_OFF_IRQ1,
  396. .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
  397. .offs = 1 << 7,
  398. },
  399. [MAX8925_IRQ_GPM_SYSCKEN_F] = {
  400. .reg = MAX8925_ON_OFF_IRQ2,
  401. .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
  402. .offs = 1 << 0,
  403. },
  404. [MAX8925_IRQ_GPM_SYSCKEN_R] = {
  405. .reg = MAX8925_ON_OFF_IRQ2,
  406. .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
  407. .offs = 1 << 1,
  408. },
  409. [MAX8925_IRQ_RTC_ALARM1] = {
  410. .reg = MAX8925_RTC_IRQ,
  411. .mask_reg = MAX8925_RTC_IRQ_MASK,
  412. .offs = 1 << 2,
  413. .flags = FLAGS_RTC,
  414. },
  415. [MAX8925_IRQ_RTC_ALARM0] = {
  416. .reg = MAX8925_RTC_IRQ,
  417. .mask_reg = MAX8925_RTC_IRQ_MASK,
  418. .offs = 1 << 3,
  419. .flags = FLAGS_RTC,
  420. },
  421. [MAX8925_IRQ_TSC_STICK] = {
  422. .reg = MAX8925_TSC_IRQ,
  423. .mask_reg = MAX8925_TSC_IRQ_MASK,
  424. .offs = 1 << 0,
  425. .flags = FLAGS_ADC,
  426. .tsc_irq = 1,
  427. },
  428. [MAX8925_IRQ_TSC_NSTICK] = {
  429. .reg = MAX8925_TSC_IRQ,
  430. .mask_reg = MAX8925_TSC_IRQ_MASK,
  431. .offs = 1 << 1,
  432. .flags = FLAGS_ADC,
  433. .tsc_irq = 1,
  434. },
  435. };
  436. static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip,
  437. int irq)
  438. {
  439. return &max8925_irqs[irq - chip->irq_base];
  440. }
  441. static irqreturn_t max8925_irq(int irq, void *data)
  442. {
  443. struct max8925_chip *chip = data;
  444. struct max8925_irq_data *irq_data;
  445. struct i2c_client *i2c;
  446. int read_reg = -1, value = 0;
  447. int i;
  448. for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
  449. irq_data = &max8925_irqs[i];
  450. /* TSC IRQ should be serviced in max8925_tsc_irq() */
  451. if (irq_data->tsc_irq)
  452. continue;
  453. if (irq_data->flags == FLAGS_RTC)
  454. i2c = chip->rtc;
  455. else if (irq_data->flags == FLAGS_ADC)
  456. i2c = chip->adc;
  457. else
  458. i2c = chip->i2c;
  459. if (read_reg != irq_data->reg) {
  460. read_reg = irq_data->reg;
  461. value = max8925_reg_read(i2c, irq_data->reg);
  462. }
  463. if (value & irq_data->enable)
  464. handle_nested_irq(chip->irq_base + i);
  465. }
  466. return IRQ_HANDLED;
  467. }
  468. static irqreturn_t max8925_tsc_irq(int irq, void *data)
  469. {
  470. struct max8925_chip *chip = data;
  471. struct max8925_irq_data *irq_data;
  472. struct i2c_client *i2c;
  473. int read_reg = -1, value = 0;
  474. int i;
  475. for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
  476. irq_data = &max8925_irqs[i];
  477. /* non TSC IRQ should be serviced in max8925_irq() */
  478. if (!irq_data->tsc_irq)
  479. continue;
  480. if (irq_data->flags == FLAGS_RTC)
  481. i2c = chip->rtc;
  482. else if (irq_data->flags == FLAGS_ADC)
  483. i2c = chip->adc;
  484. else
  485. i2c = chip->i2c;
  486. if (read_reg != irq_data->reg) {
  487. read_reg = irq_data->reg;
  488. value = max8925_reg_read(i2c, irq_data->reg);
  489. }
  490. if (value & irq_data->enable)
  491. handle_nested_irq(chip->irq_base + i);
  492. }
  493. return IRQ_HANDLED;
  494. }
  495. static void max8925_irq_lock(struct irq_data *data)
  496. {
  497. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  498. mutex_lock(&chip->irq_lock);
  499. }
  500. static void max8925_irq_sync_unlock(struct irq_data *data)
  501. {
  502. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  503. struct max8925_irq_data *irq_data;
  504. static unsigned char cache_chg[2] = {0xff, 0xff};
  505. static unsigned char cache_on[2] = {0xff, 0xff};
  506. static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
  507. unsigned char irq_chg[2], irq_on[2];
  508. unsigned char irq_rtc, irq_tsc;
  509. int i;
  510. /* Load cached value. In initial, all IRQs are masked */
  511. irq_chg[0] = cache_chg[0];
  512. irq_chg[1] = cache_chg[1];
  513. irq_on[0] = cache_on[0];
  514. irq_on[1] = cache_on[1];
  515. irq_rtc = cache_rtc;
  516. irq_tsc = cache_tsc;
  517. for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
  518. irq_data = &max8925_irqs[i];
  519. /* 1 -- disable, 0 -- enable */
  520. switch (irq_data->mask_reg) {
  521. case MAX8925_CHG_IRQ1_MASK:
  522. irq_chg[0] &= ~irq_data->enable;
  523. break;
  524. case MAX8925_CHG_IRQ2_MASK:
  525. irq_chg[1] &= ~irq_data->enable;
  526. break;
  527. case MAX8925_ON_OFF_IRQ1_MASK:
  528. irq_on[0] &= ~irq_data->enable;
  529. break;
  530. case MAX8925_ON_OFF_IRQ2_MASK:
  531. irq_on[1] &= ~irq_data->enable;
  532. break;
  533. case MAX8925_RTC_IRQ_MASK:
  534. irq_rtc &= ~irq_data->enable;
  535. break;
  536. case MAX8925_TSC_IRQ_MASK:
  537. irq_tsc &= ~irq_data->enable;
  538. break;
  539. default:
  540. dev_err(chip->dev, "wrong IRQ\n");
  541. break;
  542. }
  543. }
  544. /* update mask into registers */
  545. if (cache_chg[0] != irq_chg[0]) {
  546. cache_chg[0] = irq_chg[0];
  547. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
  548. irq_chg[0]);
  549. }
  550. if (cache_chg[1] != irq_chg[1]) {
  551. cache_chg[1] = irq_chg[1];
  552. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
  553. irq_chg[1]);
  554. }
  555. if (cache_on[0] != irq_on[0]) {
  556. cache_on[0] = irq_on[0];
  557. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
  558. irq_on[0]);
  559. }
  560. if (cache_on[1] != irq_on[1]) {
  561. cache_on[1] = irq_on[1];
  562. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
  563. irq_on[1]);
  564. }
  565. if (cache_rtc != irq_rtc) {
  566. cache_rtc = irq_rtc;
  567. max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
  568. }
  569. if (cache_tsc != irq_tsc) {
  570. cache_tsc = irq_tsc;
  571. max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
  572. }
  573. mutex_unlock(&chip->irq_lock);
  574. }
  575. static void max8925_irq_enable(struct irq_data *data)
  576. {
  577. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  578. max8925_irqs[data->irq - chip->irq_base].enable
  579. = max8925_irqs[data->irq - chip->irq_base].offs;
  580. }
  581. static void max8925_irq_disable(struct irq_data *data)
  582. {
  583. struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
  584. max8925_irqs[data->irq - chip->irq_base].enable = 0;
  585. }
  586. static struct irq_chip max8925_irq_chip = {
  587. .name = "max8925",
  588. .irq_bus_lock = max8925_irq_lock,
  589. .irq_bus_sync_unlock = max8925_irq_sync_unlock,
  590. .irq_enable = max8925_irq_enable,
  591. .irq_disable = max8925_irq_disable,
  592. };
  593. static int max8925_irq_domain_map(struct irq_domain *d, unsigned int virq,
  594. irq_hw_number_t hw)
  595. {
  596. irq_set_chip_data(virq, d->host_data);
  597. irq_set_chip_and_handler(virq, &max8925_irq_chip, handle_edge_irq);
  598. irq_set_nested_thread(virq, 1);
  599. irq_set_noprobe(virq);
  600. return 0;
  601. }
  602. static const struct irq_domain_ops max8925_irq_domain_ops = {
  603. .map = max8925_irq_domain_map,
  604. .xlate = irq_domain_xlate_onetwocell,
  605. };
  606. static int max8925_irq_init(struct max8925_chip *chip, int irq,
  607. struct max8925_platform_data *pdata)
  608. {
  609. unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
  610. int ret;
  611. struct device_node *node = chip->dev->of_node;
  612. /* clear all interrupts */
  613. max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
  614. max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
  615. max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
  616. max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
  617. max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
  618. max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
  619. /* mask all interrupts except for TSC */
  620. max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
  621. max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
  622. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
  623. max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
  624. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
  625. max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
  626. max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
  627. mutex_init(&chip->irq_lock);
  628. chip->irq_base = irq_alloc_descs(-1, 0, MAX8925_NR_IRQS, 0);
  629. if (chip->irq_base < 0) {
  630. dev_err(chip->dev, "Failed to allocate interrupts, ret:%d\n",
  631. chip->irq_base);
  632. return -EBUSY;
  633. }
  634. irq_domain_add_legacy(node, MAX8925_NR_IRQS, chip->irq_base, 0,
  635. &max8925_irq_domain_ops, chip);
  636. /* request irq handler for pmic main irq*/
  637. chip->core_irq = irq;
  638. if (!chip->core_irq)
  639. return -EBUSY;
  640. ret = request_threaded_irq(irq, NULL, max8925_irq, flags | IRQF_ONESHOT,
  641. "max8925", chip);
  642. if (ret) {
  643. dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
  644. chip->core_irq = 0;
  645. return -EBUSY;
  646. }
  647. /* request irq handler for pmic tsc irq*/
  648. /* mask TSC interrupt */
  649. max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
  650. if (!pdata->tsc_irq) {
  651. dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
  652. return 0;
  653. }
  654. chip->tsc_irq = pdata->tsc_irq;
  655. ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
  656. flags | IRQF_ONESHOT, "max8925-tsc", chip);
  657. if (ret) {
  658. dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
  659. chip->tsc_irq = 0;
  660. }
  661. return 0;
  662. }
  663. static void init_regulator(struct max8925_chip *chip,
  664. struct max8925_platform_data *pdata)
  665. {
  666. int ret;
  667. if (!pdata)
  668. return;
  669. if (pdata->sd1) {
  670. reg_devs[0].platform_data = pdata->sd1;
  671. reg_devs[0].pdata_size = sizeof(struct regulator_init_data);
  672. }
  673. if (pdata->sd2) {
  674. reg_devs[1].platform_data = pdata->sd2;
  675. reg_devs[1].pdata_size = sizeof(struct regulator_init_data);
  676. }
  677. if (pdata->sd3) {
  678. reg_devs[2].platform_data = pdata->sd3;
  679. reg_devs[2].pdata_size = sizeof(struct regulator_init_data);
  680. }
  681. if (pdata->ldo1) {
  682. reg_devs[3].platform_data = pdata->ldo1;
  683. reg_devs[3].pdata_size = sizeof(struct regulator_init_data);
  684. }
  685. if (pdata->ldo2) {
  686. reg_devs[4].platform_data = pdata->ldo2;
  687. reg_devs[4].pdata_size = sizeof(struct regulator_init_data);
  688. }
  689. if (pdata->ldo3) {
  690. reg_devs[5].platform_data = pdata->ldo3;
  691. reg_devs[5].pdata_size = sizeof(struct regulator_init_data);
  692. }
  693. if (pdata->ldo4) {
  694. reg_devs[6].platform_data = pdata->ldo4;
  695. reg_devs[6].pdata_size = sizeof(struct regulator_init_data);
  696. }
  697. if (pdata->ldo5) {
  698. reg_devs[7].platform_data = pdata->ldo5;
  699. reg_devs[7].pdata_size = sizeof(struct regulator_init_data);
  700. }
  701. if (pdata->ldo6) {
  702. reg_devs[8].platform_data = pdata->ldo6;
  703. reg_devs[8].pdata_size = sizeof(struct regulator_init_data);
  704. }
  705. if (pdata->ldo7) {
  706. reg_devs[9].platform_data = pdata->ldo7;
  707. reg_devs[9].pdata_size = sizeof(struct regulator_init_data);
  708. }
  709. if (pdata->ldo8) {
  710. reg_devs[10].platform_data = pdata->ldo8;
  711. reg_devs[10].pdata_size = sizeof(struct regulator_init_data);
  712. }
  713. if (pdata->ldo9) {
  714. reg_devs[11].platform_data = pdata->ldo9;
  715. reg_devs[11].pdata_size = sizeof(struct regulator_init_data);
  716. }
  717. if (pdata->ldo10) {
  718. reg_devs[12].platform_data = pdata->ldo10;
  719. reg_devs[12].pdata_size = sizeof(struct regulator_init_data);
  720. }
  721. if (pdata->ldo11) {
  722. reg_devs[13].platform_data = pdata->ldo11;
  723. reg_devs[13].pdata_size = sizeof(struct regulator_init_data);
  724. }
  725. if (pdata->ldo12) {
  726. reg_devs[14].platform_data = pdata->ldo12;
  727. reg_devs[14].pdata_size = sizeof(struct regulator_init_data);
  728. }
  729. if (pdata->ldo13) {
  730. reg_devs[15].platform_data = pdata->ldo13;
  731. reg_devs[15].pdata_size = sizeof(struct regulator_init_data);
  732. }
  733. if (pdata->ldo14) {
  734. reg_devs[16].platform_data = pdata->ldo14;
  735. reg_devs[16].pdata_size = sizeof(struct regulator_init_data);
  736. }
  737. if (pdata->ldo15) {
  738. reg_devs[17].platform_data = pdata->ldo15;
  739. reg_devs[17].pdata_size = sizeof(struct regulator_init_data);
  740. }
  741. if (pdata->ldo16) {
  742. reg_devs[18].platform_data = pdata->ldo16;
  743. reg_devs[18].pdata_size = sizeof(struct regulator_init_data);
  744. }
  745. if (pdata->ldo17) {
  746. reg_devs[19].platform_data = pdata->ldo17;
  747. reg_devs[19].pdata_size = sizeof(struct regulator_init_data);
  748. }
  749. if (pdata->ldo18) {
  750. reg_devs[20].platform_data = pdata->ldo18;
  751. reg_devs[20].pdata_size = sizeof(struct regulator_init_data);
  752. }
  753. if (pdata->ldo19) {
  754. reg_devs[21].platform_data = pdata->ldo19;
  755. reg_devs[21].pdata_size = sizeof(struct regulator_init_data);
  756. }
  757. if (pdata->ldo20) {
  758. reg_devs[22].platform_data = pdata->ldo20;
  759. reg_devs[22].pdata_size = sizeof(struct regulator_init_data);
  760. }
  761. ret = mfd_add_devices(chip->dev, 0, reg_devs, ARRAY_SIZE(reg_devs),
  762. NULL, 0, NULL);
  763. if (ret < 0) {
  764. dev_err(chip->dev, "Failed to add regulator subdev\n");
  765. return;
  766. }
  767. }
  768. int max8925_device_init(struct max8925_chip *chip,
  769. struct max8925_platform_data *pdata)
  770. {
  771. int ret;
  772. max8925_irq_init(chip, chip->i2c->irq, pdata);
  773. if (pdata && (pdata->power || pdata->touch)) {
  774. /* enable ADC to control internal reference */
  775. max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
  776. /* enable internal reference for ADC */
  777. max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
  778. /* check for internal reference IRQ */
  779. do {
  780. ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
  781. } while (ret & MAX8925_NREF_OK);
  782. /* enaable ADC scheduler, interval is 1 second */
  783. max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
  784. }
  785. /* enable Momentary Power Loss */
  786. max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
  787. ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
  788. ARRAY_SIZE(rtc_devs),
  789. NULL, chip->irq_base, NULL);
  790. if (ret < 0) {
  791. dev_err(chip->dev, "Failed to add rtc subdev\n");
  792. goto out;
  793. }
  794. ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
  795. ARRAY_SIZE(onkey_devs),
  796. NULL, chip->irq_base, NULL);
  797. if (ret < 0) {
  798. dev_err(chip->dev, "Failed to add onkey subdev\n");
  799. goto out_dev;
  800. }
  801. init_regulator(chip, pdata);
  802. if (pdata && pdata->backlight) {
  803. bk_devs[0].platform_data = &pdata->backlight;
  804. bk_devs[0].pdata_size = sizeof(struct max8925_backlight_pdata);
  805. }
  806. ret = mfd_add_devices(chip->dev, 0, bk_devs, ARRAY_SIZE(bk_devs),
  807. NULL, 0, NULL);
  808. if (ret < 0) {
  809. dev_err(chip->dev, "Failed to add backlight subdev\n");
  810. goto out_dev;
  811. }
  812. ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
  813. ARRAY_SIZE(power_devs),
  814. NULL, 0, NULL);
  815. if (ret < 0) {
  816. dev_err(chip->dev,
  817. "Failed to add power supply subdev, err = %d\n", ret);
  818. goto out_dev;
  819. }
  820. if (pdata && pdata->touch) {
  821. ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
  822. ARRAY_SIZE(touch_devs),
  823. NULL, chip->tsc_irq, NULL);
  824. if (ret < 0) {
  825. dev_err(chip->dev, "Failed to add touch subdev\n");
  826. goto out_dev;
  827. }
  828. }
  829. return 0;
  830. out_dev:
  831. mfd_remove_devices(chip->dev);
  832. out:
  833. return ret;
  834. }
  835. void max8925_device_exit(struct max8925_chip *chip)
  836. {
  837. if (chip->core_irq)
  838. free_irq(chip->core_irq, chip);
  839. if (chip->tsc_irq)
  840. free_irq(chip->tsc_irq, chip);
  841. mfd_remove_devices(chip->dev);
  842. }
  843. MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925");
  844. MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com");
  845. MODULE_LICENSE("GPL");