tw5864-video.c 47 KB

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  1. /*
  2. * TW5864 driver - video encoding functions
  3. *
  4. * Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/module.h>
  17. #include <media/v4l2-common.h>
  18. #include <media/v4l2-event.h>
  19. #include <media/videobuf2-dma-contig.h>
  20. #include "tw5864.h"
  21. #include "tw5864-reg.h"
  22. #define QUANTIZATION_TABLE_LEN 96
  23. #define VLC_LOOKUP_TABLE_LEN 1024
  24. static const u16 forward_quantization_table[QUANTIZATION_TABLE_LEN] = {
  25. 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
  26. 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
  27. 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
  28. 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
  29. 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
  30. 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
  31. 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
  32. 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
  33. 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
  34. 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
  35. 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d,
  36. 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d
  37. };
  38. static const u16 inverse_quantization_table[QUANTIZATION_TABLE_LEN] = {
  39. 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
  40. 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
  41. 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
  42. 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
  43. 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
  44. 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
  45. 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
  46. 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
  47. 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
  48. 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
  49. 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d,
  50. 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d
  51. };
  52. static const u16 encoder_vlc_lookup_table[VLC_LOOKUP_TABLE_LEN] = {
  53. 0x011, 0x000, 0x000, 0x000, 0x065, 0x021, 0x000, 0x000, 0x087, 0x064,
  54. 0x031, 0x000, 0x097, 0x086, 0x075, 0x053, 0x0a7, 0x096, 0x085, 0x063,
  55. 0x0b7, 0x0a6, 0x095, 0x074, 0x0df, 0x0b6, 0x0a5, 0x084, 0x0db, 0x0de,
  56. 0x0b5, 0x094, 0x0d8, 0x0da, 0x0dd, 0x0a4, 0x0ef, 0x0ee, 0x0d9, 0x0b4,
  57. 0x0eb, 0x0ea, 0x0ed, 0x0dc, 0x0ff, 0x0fe, 0x0e9, 0x0ec, 0x0fb, 0x0fa,
  58. 0x0fd, 0x0e8, 0x10f, 0x0f1, 0x0f9, 0x0fc, 0x10b, 0x10e, 0x10d, 0x0f8,
  59. 0x107, 0x10a, 0x109, 0x10c, 0x104, 0x106, 0x105, 0x108, 0x023, 0x000,
  60. 0x000, 0x000, 0x06b, 0x022, 0x000, 0x000, 0x067, 0x057, 0x033, 0x000,
  61. 0x077, 0x06a, 0x069, 0x045, 0x087, 0x066, 0x065, 0x044, 0x084, 0x076,
  62. 0x075, 0x056, 0x097, 0x086, 0x085, 0x068, 0x0bf, 0x096, 0x095, 0x064,
  63. 0x0bb, 0x0be, 0x0bd, 0x074, 0x0cf, 0x0ba, 0x0b9, 0x094, 0x0cb, 0x0ce,
  64. 0x0cd, 0x0bc, 0x0c8, 0x0ca, 0x0c9, 0x0b8, 0x0df, 0x0de, 0x0dd, 0x0cc,
  65. 0x0db, 0x0da, 0x0d9, 0x0dc, 0x0d7, 0x0eb, 0x0d6, 0x0d8, 0x0e9, 0x0e8,
  66. 0x0ea, 0x0d1, 0x0e7, 0x0e6, 0x0e5, 0x0e4, 0x04f, 0x000, 0x000, 0x000,
  67. 0x06f, 0x04e, 0x000, 0x000, 0x06b, 0x05f, 0x04d, 0x000, 0x068, 0x05c,
  68. 0x05e, 0x04c, 0x07f, 0x05a, 0x05b, 0x04b, 0x07b, 0x058, 0x059, 0x04a,
  69. 0x079, 0x06e, 0x06d, 0x049, 0x078, 0x06a, 0x069, 0x048, 0x08f, 0x07e,
  70. 0x07d, 0x05d, 0x08b, 0x08e, 0x07a, 0x06c, 0x09f, 0x08a, 0x08d, 0x07c,
  71. 0x09b, 0x09e, 0x089, 0x08c, 0x098, 0x09a, 0x09d, 0x088, 0x0ad, 0x097,
  72. 0x099, 0x09c, 0x0a9, 0x0ac, 0x0ab, 0x0aa, 0x0a5, 0x0a8, 0x0a7, 0x0a6,
  73. 0x0a1, 0x0a4, 0x0a3, 0x0a2, 0x021, 0x000, 0x000, 0x000, 0x067, 0x011,
  74. 0x000, 0x000, 0x064, 0x066, 0x031, 0x000, 0x063, 0x073, 0x072, 0x065,
  75. 0x062, 0x083, 0x082, 0x070, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  76. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  77. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  78. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  79. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  80. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  81. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  82. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  83. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  84. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  85. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  86. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  87. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  88. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  89. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  90. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  91. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  92. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  93. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  94. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  95. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  96. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  97. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  98. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  99. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  100. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  101. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  102. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  103. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  104. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  105. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x011, 0x010,
  106. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  107. 0x000, 0x000, 0x000, 0x000, 0x011, 0x021, 0x020, 0x000, 0x000, 0x000,
  108. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  109. 0x023, 0x022, 0x021, 0x020, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  110. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x022, 0x021, 0x031,
  111. 0x030, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  112. 0x000, 0x000, 0x023, 0x022, 0x033, 0x032, 0x031, 0x030, 0x000, 0x000,
  113. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x030,
  114. 0x031, 0x033, 0x032, 0x035, 0x034, 0x000, 0x000, 0x000, 0x000, 0x000,
  115. 0x000, 0x000, 0x000, 0x000, 0x037, 0x036, 0x035, 0x034, 0x033, 0x032,
  116. 0x031, 0x041, 0x051, 0x061, 0x071, 0x081, 0x091, 0x0a1, 0x0b1, 0x000,
  117. 0x002, 0x000, 0x0e4, 0x011, 0x0f4, 0x002, 0x024, 0x003, 0x005, 0x012,
  118. 0x034, 0x013, 0x065, 0x024, 0x013, 0x063, 0x015, 0x022, 0x075, 0x034,
  119. 0x044, 0x023, 0x023, 0x073, 0x054, 0x033, 0x033, 0x004, 0x043, 0x014,
  120. 0x011, 0x043, 0x014, 0x001, 0x025, 0x015, 0x035, 0x025, 0x064, 0x055,
  121. 0x045, 0x035, 0x074, 0x065, 0x085, 0x0d5, 0x012, 0x095, 0x055, 0x045,
  122. 0x095, 0x0e5, 0x084, 0x075, 0x022, 0x0a5, 0x094, 0x085, 0x032, 0x0b5,
  123. 0x003, 0x0c5, 0x001, 0x044, 0x0a5, 0x032, 0x0b5, 0x094, 0x0c5, 0x0a4,
  124. 0x0a4, 0x054, 0x0d5, 0x0b4, 0x0b4, 0x064, 0x0f5, 0x0f5, 0x053, 0x0d4,
  125. 0x0e5, 0x0c4, 0x105, 0x105, 0x0c4, 0x074, 0x063, 0x0e4, 0x0d4, 0x084,
  126. 0x073, 0x0f4, 0x004, 0x005, 0x000, 0x053, 0x000, 0x000, 0x000, 0x000,
  127. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  128. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  129. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  130. 0x000, 0x000, 0x011, 0x021, 0x031, 0x030, 0x011, 0x021, 0x020, 0x000,
  131. 0x011, 0x010, 0x000, 0x000, 0x011, 0x033, 0x032, 0x043, 0x042, 0x053,
  132. 0x052, 0x063, 0x062, 0x073, 0x072, 0x083, 0x082, 0x093, 0x092, 0x091,
  133. 0x037, 0x036, 0x035, 0x034, 0x033, 0x045, 0x044, 0x043, 0x042, 0x053,
  134. 0x052, 0x063, 0x062, 0x061, 0x060, 0x000, 0x045, 0x037, 0x036, 0x035,
  135. 0x044, 0x043, 0x034, 0x033, 0x042, 0x053, 0x052, 0x061, 0x051, 0x060,
  136. 0x000, 0x000, 0x053, 0x037, 0x045, 0x044, 0x036, 0x035, 0x034, 0x043,
  137. 0x033, 0x042, 0x052, 0x051, 0x050, 0x000, 0x000, 0x000, 0x045, 0x044,
  138. 0x043, 0x037, 0x036, 0x035, 0x034, 0x033, 0x042, 0x051, 0x041, 0x050,
  139. 0x000, 0x000, 0x000, 0x000, 0x061, 0x051, 0x037, 0x036, 0x035, 0x034,
  140. 0x033, 0x032, 0x041, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
  141. 0x061, 0x051, 0x035, 0x034, 0x033, 0x023, 0x032, 0x041, 0x031, 0x060,
  142. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x061, 0x041, 0x051, 0x033,
  143. 0x023, 0x022, 0x032, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
  144. 0x000, 0x000, 0x061, 0x060, 0x041, 0x023, 0x022, 0x031, 0x021, 0x051,
  145. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x051, 0x050,
  146. 0x031, 0x023, 0x022, 0x021, 0x041, 0x000, 0x000, 0x000, 0x000, 0x000,
  147. 0x000, 0x000, 0x000, 0x000, 0x040, 0x041, 0x031, 0x032, 0x011, 0x033,
  148. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  149. 0x040, 0x041, 0x021, 0x011, 0x031, 0x000, 0x000, 0x000, 0x000, 0x000,
  150. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x030, 0x031, 0x011, 0x021,
  151. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  152. 0x000, 0x000, 0x020, 0x021, 0x011, 0x000, 0x000, 0x000, 0x000, 0x000,
  153. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x010, 0x011,
  154. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  155. 0x000, 0x000, 0x000, 0x000
  156. };
  157. static const unsigned int lambda_lookup_table[] = {
  158. 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
  159. 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
  160. 0x0040, 0x0040, 0x0040, 0x0040, 0x0060, 0x0060, 0x0060, 0x0080,
  161. 0x0080, 0x0080, 0x00a0, 0x00c0, 0x00c0, 0x00e0, 0x0100, 0x0120,
  162. 0x0140, 0x0160, 0x01a0, 0x01c0, 0x0200, 0x0240, 0x0280, 0x02e0,
  163. 0x0320, 0x03a0, 0x0400, 0x0480, 0x0500, 0x05a0, 0x0660, 0x0720,
  164. 0x0800, 0x0900, 0x0a20, 0x0b60
  165. };
  166. static const unsigned int intra4x4_lambda3[] = {
  167. 1, 1, 1, 1, 1, 1, 1, 1,
  168. 1, 1, 1, 1, 1, 1, 1, 1,
  169. 2, 2, 2, 2, 3, 3, 3, 4,
  170. 4, 4, 5, 6, 6, 7, 8, 9,
  171. 10, 11, 13, 14, 16, 18, 20, 23,
  172. 25, 29, 32, 36, 40, 45, 51, 57,
  173. 64, 72, 81, 91
  174. };
  175. static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std);
  176. static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std);
  177. static void tw5864_handle_frame_task(unsigned long data);
  178. static void tw5864_handle_frame(struct tw5864_h264_frame *frame);
  179. static void tw5864_frame_interval_set(struct tw5864_input *input);
  180. static int tw5864_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
  181. unsigned int *num_planes, unsigned int sizes[],
  182. struct device *alloc_ctxs[])
  183. {
  184. if (*num_planes)
  185. return sizes[0] < H264_VLC_BUF_SIZE ? -EINVAL : 0;
  186. sizes[0] = H264_VLC_BUF_SIZE;
  187. *num_planes = 1;
  188. return 0;
  189. }
  190. static void tw5864_buf_queue(struct vb2_buffer *vb)
  191. {
  192. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  193. struct vb2_queue *vq = vb->vb2_queue;
  194. struct tw5864_input *dev = vb2_get_drv_priv(vq);
  195. struct tw5864_buf *buf = container_of(vbuf, struct tw5864_buf, vb);
  196. unsigned long flags;
  197. spin_lock_irqsave(&dev->slock, flags);
  198. list_add_tail(&buf->list, &dev->active);
  199. spin_unlock_irqrestore(&dev->slock, flags);
  200. }
  201. static int tw5864_input_std_get(struct tw5864_input *input,
  202. enum tw5864_vid_std *std)
  203. {
  204. struct tw5864_dev *dev = input->root;
  205. u8 std_reg = tw_indir_readb(TW5864_INDIR_VIN_E(input->nr));
  206. *std = (std_reg & 0x70) >> 4;
  207. if (std_reg & 0x80) {
  208. dev_dbg(&dev->pci->dev,
  209. "Video format detection is in progress, please wait\n");
  210. return -EAGAIN;
  211. }
  212. return 0;
  213. }
  214. static int tw5864_enable_input(struct tw5864_input *input)
  215. {
  216. struct tw5864_dev *dev = input->root;
  217. int nr = input->nr;
  218. unsigned long flags;
  219. int d1_width = 720;
  220. int d1_height;
  221. int frame_width_bus_value = 0;
  222. int frame_height_bus_value = 0;
  223. int reg_frame_bus = 0x1c;
  224. int fmt_reg_value = 0;
  225. int downscale_enabled = 0;
  226. dev_dbg(&dev->pci->dev, "Enabling channel %d\n", nr);
  227. input->frame_seqno = 0;
  228. input->frame_gop_seqno = 0;
  229. input->h264_idr_pic_id = 0;
  230. input->reg_dsp_qp = input->qp;
  231. input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
  232. input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
  233. input->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST
  234. | TW5864_EMU_EN_SEN | TW5864_EMU_EN_ME | TW5864_EMU_EN_DDR;
  235. input->reg_dsp = nr /* channel id */
  236. | TW5864_DSP_CHROM_SW
  237. | ((0xa << 8) & TW5864_DSP_MB_DELAY)
  238. ;
  239. input->resolution = D1;
  240. d1_height = (input->std == STD_NTSC) ? 480 : 576;
  241. input->width = d1_width;
  242. input->height = d1_height;
  243. input->reg_interlacing = 0x4;
  244. switch (input->resolution) {
  245. case D1:
  246. frame_width_bus_value = 0x2cf;
  247. frame_height_bus_value = input->height - 1;
  248. reg_frame_bus = 0x1c;
  249. fmt_reg_value = 0;
  250. downscale_enabled = 0;
  251. input->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD;
  252. input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
  253. input->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST;
  254. tw_setl(TW5864_FULL_HALF_FLAG, 1 << nr);
  255. break;
  256. case HD1:
  257. input->height /= 2;
  258. input->width /= 2;
  259. frame_width_bus_value = 0x2cf;
  260. frame_height_bus_value = input->height * 2 - 1;
  261. reg_frame_bus = 0x1c;
  262. fmt_reg_value = 0;
  263. downscale_enabled = 0;
  264. input->reg_dsp_codec |= TW5864_HD1_MAP_MD;
  265. input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
  266. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  267. break;
  268. case CIF:
  269. input->height /= 4;
  270. input->width /= 2;
  271. frame_width_bus_value = 0x15f;
  272. frame_height_bus_value = input->height * 2 - 1;
  273. reg_frame_bus = 0x07;
  274. fmt_reg_value = 1;
  275. downscale_enabled = 1;
  276. input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
  277. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  278. break;
  279. case QCIF:
  280. input->height /= 4;
  281. input->width /= 4;
  282. frame_width_bus_value = 0x15f;
  283. frame_height_bus_value = input->height * 2 - 1;
  284. reg_frame_bus = 0x07;
  285. fmt_reg_value = 1;
  286. downscale_enabled = 1;
  287. input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
  288. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  289. break;
  290. }
  291. /* analog input width / 4 */
  292. tw_indir_writeb(TW5864_INDIR_IN_PIC_WIDTH(nr), d1_width / 4);
  293. tw_indir_writeb(TW5864_INDIR_IN_PIC_HEIGHT(nr), d1_height / 4);
  294. /* output width / 4 */
  295. tw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4);
  296. tw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4);
  297. tw_writel(TW5864_DSP_PIC_MAX_MB,
  298. ((input->width / 16) << 8) | (input->height / 16));
  299. tw_writel(TW5864_FRAME_WIDTH_BUS_A(nr),
  300. frame_width_bus_value);
  301. tw_writel(TW5864_FRAME_WIDTH_BUS_B(nr),
  302. frame_width_bus_value);
  303. tw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr),
  304. frame_height_bus_value);
  305. tw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr),
  306. (frame_height_bus_value + 1) / 2 - 1);
  307. tw5864_frame_interval_set(input);
  308. if (downscale_enabled)
  309. tw_setl(TW5864_H264EN_CH_DNS, 1 << nr);
  310. tw_mask_shift_writel(TW5864_H264EN_CH_FMT_REG1, 0x3, 2 * nr,
  311. fmt_reg_value);
  312. tw_mask_shift_writel((nr < 2
  313. ? TW5864_H264EN_RATE_MAX_LINE_REG1
  314. : TW5864_H264EN_RATE_MAX_LINE_REG2),
  315. 0x1f, 5 * (nr % 2),
  316. input->std == STD_NTSC ? 29 : 24);
  317. tw_mask_shift_writel((nr < 2) ? TW5864_FRAME_BUS1 :
  318. TW5864_FRAME_BUS2, 0xff, (nr % 2) * 8,
  319. reg_frame_bus);
  320. spin_lock_irqsave(&dev->slock, flags);
  321. input->enabled = 1;
  322. spin_unlock_irqrestore(&dev->slock, flags);
  323. return 0;
  324. }
  325. void tw5864_request_encoded_frame(struct tw5864_input *input)
  326. {
  327. struct tw5864_dev *dev = input->root;
  328. u32 enc_buf_id_new;
  329. tw_setl(TW5864_DSP_CODEC, TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD);
  330. tw_writel(TW5864_EMU, input->reg_emu);
  331. tw_writel(TW5864_INTERLACING, input->reg_interlacing);
  332. tw_writel(TW5864_DSP, input->reg_dsp);
  333. tw_writel(TW5864_DSP_QP, input->reg_dsp_qp);
  334. tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda);
  335. tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight);
  336. tw_mask_shift_writel(TW5864_DSP_INTRA_MODE, TW5864_DSP_INTRA_MODE_MASK,
  337. TW5864_DSP_INTRA_MODE_SHIFT,
  338. TW5864_DSP_INTRA_MODE_16x16);
  339. if (input->frame_gop_seqno == 0) {
  340. /* Produce I-frame */
  341. tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN);
  342. input->h264_idr_pic_id++;
  343. input->h264_idr_pic_id &= TW5864_DSP_REF_FRM;
  344. } else {
  345. /* Produce P-frame */
  346. tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN |
  347. TW5864_ME_EN | BIT(5) /* SRCH_OPT default */);
  348. }
  349. tw5864_prepare_frame_headers(input);
  350. tw_writel(TW5864_VLC,
  351. TW5864_VLC_PCI_SEL |
  352. ((input->tail_nb_bits + 24) << TW5864_VLC_BIT_ALIGN_SHIFT) |
  353. input->reg_dsp_qp);
  354. enc_buf_id_new = tw_mask_shift_readl(TW5864_ENC_BUF_PTR_REC1, 0x3,
  355. 2 * input->nr);
  356. tw_writel(TW5864_DSP_ENC_ORG_PTR_REG,
  357. enc_buf_id_new << TW5864_DSP_ENC_ORG_PTR_SHIFT);
  358. tw_writel(TW5864_DSP_ENC_REC,
  359. enc_buf_id_new << 12 | ((enc_buf_id_new + 3) & 3));
  360. tw_writel(TW5864_SLICE, TW5864_START_NSLICE);
  361. tw_writel(TW5864_SLICE, 0);
  362. }
  363. static int tw5864_disable_input(struct tw5864_input *input)
  364. {
  365. struct tw5864_dev *dev = input->root;
  366. unsigned long flags;
  367. dev_dbg(&dev->pci->dev, "Disabling channel %d\n", input->nr);
  368. spin_lock_irqsave(&dev->slock, flags);
  369. input->enabled = 0;
  370. spin_unlock_irqrestore(&dev->slock, flags);
  371. return 0;
  372. }
  373. static int tw5864_start_streaming(struct vb2_queue *q, unsigned int count)
  374. {
  375. struct tw5864_input *input = vb2_get_drv_priv(q);
  376. int ret;
  377. ret = tw5864_enable_input(input);
  378. if (!ret)
  379. return 0;
  380. while (!list_empty(&input->active)) {
  381. struct tw5864_buf *buf = list_entry(input->active.next,
  382. struct tw5864_buf, list);
  383. list_del(&buf->list);
  384. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
  385. }
  386. return ret;
  387. }
  388. static void tw5864_stop_streaming(struct vb2_queue *q)
  389. {
  390. unsigned long flags;
  391. struct tw5864_input *input = vb2_get_drv_priv(q);
  392. tw5864_disable_input(input);
  393. spin_lock_irqsave(&input->slock, flags);
  394. if (input->vb) {
  395. vb2_buffer_done(&input->vb->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  396. input->vb = NULL;
  397. }
  398. while (!list_empty(&input->active)) {
  399. struct tw5864_buf *buf = list_entry(input->active.next,
  400. struct tw5864_buf, list);
  401. list_del(&buf->list);
  402. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  403. }
  404. spin_unlock_irqrestore(&input->slock, flags);
  405. }
  406. static const struct vb2_ops tw5864_video_qops = {
  407. .queue_setup = tw5864_queue_setup,
  408. .buf_queue = tw5864_buf_queue,
  409. .start_streaming = tw5864_start_streaming,
  410. .stop_streaming = tw5864_stop_streaming,
  411. .wait_prepare = vb2_ops_wait_prepare,
  412. .wait_finish = vb2_ops_wait_finish,
  413. };
  414. static int tw5864_s_ctrl(struct v4l2_ctrl *ctrl)
  415. {
  416. struct tw5864_input *input =
  417. container_of(ctrl->handler, struct tw5864_input, hdl);
  418. struct tw5864_dev *dev = input->root;
  419. unsigned long flags;
  420. switch (ctrl->id) {
  421. case V4L2_CID_BRIGHTNESS:
  422. tw_indir_writeb(TW5864_INDIR_VIN_A_BRIGHT(input->nr),
  423. (u8)ctrl->val);
  424. break;
  425. case V4L2_CID_HUE:
  426. tw_indir_writeb(TW5864_INDIR_VIN_7_HUE(input->nr),
  427. (u8)ctrl->val);
  428. break;
  429. case V4L2_CID_CONTRAST:
  430. tw_indir_writeb(TW5864_INDIR_VIN_9_CNTRST(input->nr),
  431. (u8)ctrl->val);
  432. break;
  433. case V4L2_CID_SATURATION:
  434. tw_indir_writeb(TW5864_INDIR_VIN_B_SAT_U(input->nr),
  435. (u8)ctrl->val);
  436. tw_indir_writeb(TW5864_INDIR_VIN_C_SAT_V(input->nr),
  437. (u8)ctrl->val);
  438. break;
  439. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  440. input->gop = ctrl->val;
  441. return 0;
  442. case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
  443. spin_lock_irqsave(&input->slock, flags);
  444. input->qp = ctrl->val;
  445. input->reg_dsp_qp = input->qp;
  446. input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
  447. input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
  448. spin_unlock_irqrestore(&input->slock, flags);
  449. return 0;
  450. case V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD:
  451. memset(input->md_threshold_grid_values, ctrl->val,
  452. sizeof(input->md_threshold_grid_values));
  453. return 0;
  454. case V4L2_CID_DETECT_MD_MODE:
  455. return 0;
  456. case V4L2_CID_DETECT_MD_THRESHOLD_GRID:
  457. /* input->md_threshold_grid_ctrl->p_new.p_u16 contains data */
  458. memcpy(input->md_threshold_grid_values,
  459. input->md_threshold_grid_ctrl->p_new.p_u16,
  460. sizeof(input->md_threshold_grid_values));
  461. return 0;
  462. }
  463. return 0;
  464. }
  465. static int tw5864_fmt_vid_cap(struct file *file, void *priv,
  466. struct v4l2_format *f)
  467. {
  468. struct tw5864_input *input = video_drvdata(file);
  469. f->fmt.pix.width = 720;
  470. switch (input->std) {
  471. default:
  472. WARN_ON_ONCE(1);
  473. case STD_NTSC:
  474. f->fmt.pix.height = 480;
  475. break;
  476. case STD_PAL:
  477. case STD_SECAM:
  478. f->fmt.pix.height = 576;
  479. break;
  480. }
  481. f->fmt.pix.field = V4L2_FIELD_INTERLACED;
  482. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  483. f->fmt.pix.sizeimage = H264_VLC_BUF_SIZE;
  484. f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
  485. return 0;
  486. }
  487. static int tw5864_enum_input(struct file *file, void *priv,
  488. struct v4l2_input *i)
  489. {
  490. struct tw5864_input *input = video_drvdata(file);
  491. struct tw5864_dev *dev = input->root;
  492. u8 indir_0x000 = tw_indir_readb(TW5864_INDIR_VIN_0(input->nr));
  493. u8 indir_0x00d = tw_indir_readb(TW5864_INDIR_VIN_D(input->nr));
  494. u8 v1 = indir_0x000;
  495. u8 v2 = indir_0x00d;
  496. if (i->index)
  497. return -EINVAL;
  498. i->type = V4L2_INPUT_TYPE_CAMERA;
  499. snprintf(i->name, sizeof(i->name), "Encoder %d", input->nr);
  500. i->std = TW5864_NORMS;
  501. if (v1 & (1 << 7))
  502. i->status |= V4L2_IN_ST_NO_SYNC;
  503. if (!(v1 & (1 << 6)))
  504. i->status |= V4L2_IN_ST_NO_H_LOCK;
  505. if (v1 & (1 << 2))
  506. i->status |= V4L2_IN_ST_NO_SIGNAL;
  507. if (v1 & (1 << 1))
  508. i->status |= V4L2_IN_ST_NO_COLOR;
  509. if (v2 & (1 << 2))
  510. i->status |= V4L2_IN_ST_MACROVISION;
  511. return 0;
  512. }
  513. static int tw5864_g_input(struct file *file, void *priv, unsigned int *i)
  514. {
  515. *i = 0;
  516. return 0;
  517. }
  518. static int tw5864_s_input(struct file *file, void *priv, unsigned int i)
  519. {
  520. if (i)
  521. return -EINVAL;
  522. return 0;
  523. }
  524. static int tw5864_querycap(struct file *file, void *priv,
  525. struct v4l2_capability *cap)
  526. {
  527. struct tw5864_input *input = video_drvdata(file);
  528. strcpy(cap->driver, "tw5864");
  529. snprintf(cap->card, sizeof(cap->card), "TW5864 Encoder %d",
  530. input->nr);
  531. sprintf(cap->bus_info, "PCI:%s", pci_name(input->root->pci));
  532. return 0;
  533. }
  534. static int tw5864_querystd(struct file *file, void *priv, v4l2_std_id *std)
  535. {
  536. struct tw5864_input *input = video_drvdata(file);
  537. enum tw5864_vid_std tw_std;
  538. int ret;
  539. ret = tw5864_input_std_get(input, &tw_std);
  540. if (ret)
  541. return ret;
  542. *std = tw5864_get_v4l2_std(tw_std);
  543. return 0;
  544. }
  545. static int tw5864_g_std(struct file *file, void *priv, v4l2_std_id *std)
  546. {
  547. struct tw5864_input *input = video_drvdata(file);
  548. *std = input->v4l2_std;
  549. return 0;
  550. }
  551. static int tw5864_s_std(struct file *file, void *priv, v4l2_std_id std)
  552. {
  553. struct tw5864_input *input = video_drvdata(file);
  554. struct tw5864_dev *dev = input->root;
  555. input->v4l2_std = std;
  556. input->std = tw5864_from_v4l2_std(std);
  557. tw_indir_writeb(TW5864_INDIR_VIN_E(input->nr), input->std);
  558. return 0;
  559. }
  560. static int tw5864_enum_fmt_vid_cap(struct file *file, void *priv,
  561. struct v4l2_fmtdesc *f)
  562. {
  563. if (f->index)
  564. return -EINVAL;
  565. f->pixelformat = V4L2_PIX_FMT_H264;
  566. return 0;
  567. }
  568. static int tw5864_subscribe_event(struct v4l2_fh *fh,
  569. const struct v4l2_event_subscription *sub)
  570. {
  571. switch (sub->type) {
  572. case V4L2_EVENT_CTRL:
  573. return v4l2_ctrl_subscribe_event(fh, sub);
  574. case V4L2_EVENT_MOTION_DET:
  575. /*
  576. * Allow for up to 30 events (1 second for NTSC) to be stored.
  577. */
  578. return v4l2_event_subscribe(fh, sub, 30, NULL);
  579. }
  580. return -EINVAL;
  581. }
  582. static void tw5864_frame_interval_set(struct tw5864_input *input)
  583. {
  584. /*
  585. * This register value seems to follow such approach: In each second
  586. * interval, when processing Nth frame, it checks Nth bit of register
  587. * value and, if the bit is 1, it processes the frame, otherwise the
  588. * frame is discarded.
  589. * So unary representation would work, but more or less equal gaps
  590. * between the frames should be preserved.
  591. *
  592. * For 1 FPS - 0x00000001
  593. * 00000000 00000000 00000000 00000001
  594. *
  595. * For max FPS - set all 25/30 lower bits:
  596. * 00111111 11111111 11111111 11111111 (NTSC)
  597. * 00000001 11111111 11111111 11111111 (PAL)
  598. *
  599. * For half of max FPS - use such pattern:
  600. * 00010101 01010101 01010101 01010101 (NTSC)
  601. * 00000001 01010101 01010101 01010101 (PAL)
  602. *
  603. * Et cetera.
  604. *
  605. * The value supplied to hardware is capped by mask of 25/30 lower bits.
  606. */
  607. struct tw5864_dev *dev = input->root;
  608. u32 unary_framerate = 0;
  609. int shift = 0;
  610. int std_max_fps = input->std == STD_NTSC ? 30 : 25;
  611. for (shift = 0; shift < std_max_fps; shift += input->frame_interval)
  612. unary_framerate |= 0x00000001 << shift;
  613. tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),
  614. unary_framerate >> 16);
  615. tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),
  616. unary_framerate & 0xffff);
  617. }
  618. static int tw5864_frameinterval_get(struct tw5864_input *input,
  619. struct v4l2_fract *frameinterval)
  620. {
  621. struct tw5864_dev *dev = input->root;
  622. switch (input->std) {
  623. case STD_NTSC:
  624. frameinterval->numerator = 1001;
  625. frameinterval->denominator = 30000;
  626. break;
  627. case STD_PAL:
  628. case STD_SECAM:
  629. frameinterval->numerator = 1;
  630. frameinterval->denominator = 25;
  631. break;
  632. default:
  633. dev_warn(&dev->pci->dev, "tw5864_frameinterval_get requested for unknown std %d\n",
  634. input->std);
  635. return -EINVAL;
  636. }
  637. return 0;
  638. }
  639. static int tw5864_enum_framesizes(struct file *file, void *priv,
  640. struct v4l2_frmsizeenum *fsize)
  641. {
  642. struct tw5864_input *input = video_drvdata(file);
  643. if (fsize->index > 0)
  644. return -EINVAL;
  645. if (fsize->pixel_format != V4L2_PIX_FMT_H264)
  646. return -EINVAL;
  647. fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
  648. fsize->discrete.width = 720;
  649. fsize->discrete.height = input->std == STD_NTSC ? 480 : 576;
  650. return 0;
  651. }
  652. static int tw5864_enum_frameintervals(struct file *file, void *priv,
  653. struct v4l2_frmivalenum *fintv)
  654. {
  655. struct tw5864_input *input = video_drvdata(file);
  656. struct v4l2_fract frameinterval;
  657. int std_max_fps = input->std == STD_NTSC ? 30 : 25;
  658. struct v4l2_frmsizeenum fsize = { .index = fintv->index,
  659. .pixel_format = fintv->pixel_format };
  660. int ret;
  661. ret = tw5864_enum_framesizes(file, priv, &fsize);
  662. if (ret)
  663. return ret;
  664. if (fintv->width != fsize.discrete.width ||
  665. fintv->height != fsize.discrete.height)
  666. return -EINVAL;
  667. fintv->type = V4L2_FRMIVAL_TYPE_STEPWISE;
  668. ret = tw5864_frameinterval_get(input, &frameinterval);
  669. fintv->stepwise.step = frameinterval;
  670. fintv->stepwise.min = frameinterval;
  671. fintv->stepwise.max = frameinterval;
  672. fintv->stepwise.max.numerator *= std_max_fps;
  673. return ret;
  674. }
  675. static int tw5864_g_parm(struct file *file, void *priv,
  676. struct v4l2_streamparm *sp)
  677. {
  678. struct tw5864_input *input = video_drvdata(file);
  679. struct v4l2_captureparm *cp = &sp->parm.capture;
  680. int ret;
  681. cp->capability = V4L2_CAP_TIMEPERFRAME;
  682. ret = tw5864_frameinterval_get(input, &cp->timeperframe);
  683. cp->timeperframe.numerator *= input->frame_interval;
  684. cp->capturemode = 0;
  685. cp->readbuffers = 2;
  686. return ret;
  687. }
  688. static int tw5864_s_parm(struct file *file, void *priv,
  689. struct v4l2_streamparm *sp)
  690. {
  691. struct tw5864_input *input = video_drvdata(file);
  692. struct v4l2_fract *t = &sp->parm.capture.timeperframe;
  693. struct v4l2_fract time_base;
  694. int ret;
  695. ret = tw5864_frameinterval_get(input, &time_base);
  696. if (ret)
  697. return ret;
  698. if (!t->numerator || !t->denominator) {
  699. t->numerator = time_base.numerator * input->frame_interval;
  700. t->denominator = time_base.denominator;
  701. } else if (t->denominator != time_base.denominator) {
  702. t->numerator = t->numerator * time_base.denominator /
  703. t->denominator;
  704. t->denominator = time_base.denominator;
  705. }
  706. input->frame_interval = t->numerator / time_base.numerator;
  707. if (input->frame_interval < 1)
  708. input->frame_interval = 1;
  709. tw5864_frame_interval_set(input);
  710. return tw5864_g_parm(file, priv, sp);
  711. }
  712. static const struct v4l2_ctrl_ops tw5864_ctrl_ops = {
  713. .s_ctrl = tw5864_s_ctrl,
  714. };
  715. static const struct v4l2_file_operations video_fops = {
  716. .owner = THIS_MODULE,
  717. .open = v4l2_fh_open,
  718. .release = vb2_fop_release,
  719. .read = vb2_fop_read,
  720. .poll = vb2_fop_poll,
  721. .mmap = vb2_fop_mmap,
  722. .unlocked_ioctl = video_ioctl2,
  723. };
  724. #ifdef CONFIG_VIDEO_ADV_DEBUG
  725. #define INDIR_SPACE_MAP_SHIFT 0x100000
  726. static int tw5864_g_reg(struct file *file, void *fh,
  727. struct v4l2_dbg_register *reg)
  728. {
  729. struct tw5864_input *input = video_drvdata(file);
  730. struct tw5864_dev *dev = input->root;
  731. if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
  732. if (reg->reg > 0x87fff)
  733. return -EINVAL;
  734. reg->size = 4;
  735. reg->val = tw_readl(reg->reg);
  736. } else {
  737. __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
  738. if (indir_addr > 0xefe)
  739. return -EINVAL;
  740. reg->size = 1;
  741. reg->val = tw_indir_readb(reg->reg);
  742. }
  743. return 0;
  744. }
  745. static int tw5864_s_reg(struct file *file, void *fh,
  746. const struct v4l2_dbg_register *reg)
  747. {
  748. struct tw5864_input *input = video_drvdata(file);
  749. struct tw5864_dev *dev = input->root;
  750. if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
  751. if (reg->reg > 0x87fff)
  752. return -EINVAL;
  753. tw_writel(reg->reg, reg->val);
  754. } else {
  755. __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
  756. if (indir_addr > 0xefe)
  757. return -EINVAL;
  758. tw_indir_writeb(reg->reg, reg->val);
  759. }
  760. return 0;
  761. }
  762. #endif
  763. static const struct v4l2_ioctl_ops video_ioctl_ops = {
  764. .vidioc_querycap = tw5864_querycap,
  765. .vidioc_enum_fmt_vid_cap = tw5864_enum_fmt_vid_cap,
  766. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  767. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  768. .vidioc_querybuf = vb2_ioctl_querybuf,
  769. .vidioc_qbuf = vb2_ioctl_qbuf,
  770. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  771. .vidioc_expbuf = vb2_ioctl_expbuf,
  772. .vidioc_querystd = tw5864_querystd,
  773. .vidioc_s_std = tw5864_s_std,
  774. .vidioc_g_std = tw5864_g_std,
  775. .vidioc_enum_input = tw5864_enum_input,
  776. .vidioc_g_input = tw5864_g_input,
  777. .vidioc_s_input = tw5864_s_input,
  778. .vidioc_streamon = vb2_ioctl_streamon,
  779. .vidioc_streamoff = vb2_ioctl_streamoff,
  780. .vidioc_try_fmt_vid_cap = tw5864_fmt_vid_cap,
  781. .vidioc_s_fmt_vid_cap = tw5864_fmt_vid_cap,
  782. .vidioc_g_fmt_vid_cap = tw5864_fmt_vid_cap,
  783. .vidioc_log_status = v4l2_ctrl_log_status,
  784. .vidioc_subscribe_event = tw5864_subscribe_event,
  785. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  786. .vidioc_enum_framesizes = tw5864_enum_framesizes,
  787. .vidioc_enum_frameintervals = tw5864_enum_frameintervals,
  788. .vidioc_s_parm = tw5864_s_parm,
  789. .vidioc_g_parm = tw5864_g_parm,
  790. #ifdef CONFIG_VIDEO_ADV_DEBUG
  791. .vidioc_g_register = tw5864_g_reg,
  792. .vidioc_s_register = tw5864_s_reg,
  793. #endif
  794. };
  795. static const struct video_device tw5864_video_template = {
  796. .name = "tw5864_video",
  797. .fops = &video_fops,
  798. .ioctl_ops = &video_ioctl_ops,
  799. .release = video_device_release_empty,
  800. .tvnorms = TW5864_NORMS,
  801. .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
  802. V4L2_CAP_STREAMING,
  803. };
  804. /* Motion Detection Threshold matrix */
  805. static const struct v4l2_ctrl_config tw5864_md_thresholds = {
  806. .ops = &tw5864_ctrl_ops,
  807. .id = V4L2_CID_DETECT_MD_THRESHOLD_GRID,
  808. .dims = {MD_CELLS_HOR, MD_CELLS_VERT},
  809. .def = 14,
  810. /* See tw5864_md_metric_from_mvd() */
  811. .max = 2 * 0x0f,
  812. .step = 1,
  813. };
  814. static int tw5864_video_input_init(struct tw5864_input *dev, int video_nr);
  815. static void tw5864_video_input_fini(struct tw5864_input *dev);
  816. static void tw5864_encoder_tables_upload(struct tw5864_dev *dev);
  817. int tw5864_video_init(struct tw5864_dev *dev, int *video_nr)
  818. {
  819. int i;
  820. int ret;
  821. unsigned long flags;
  822. int last_dma_allocated = -1;
  823. int last_input_nr_registered = -1;
  824. for (i = 0; i < H264_BUF_CNT; i++) {
  825. struct tw5864_h264_frame *frame = &dev->h264_buf[i];
  826. frame->vlc.addr = dma_alloc_coherent(&dev->pci->dev,
  827. H264_VLC_BUF_SIZE,
  828. &frame->vlc.dma_addr,
  829. GFP_KERNEL | GFP_DMA32);
  830. if (!frame->vlc.addr) {
  831. dev_err(&dev->pci->dev, "dma alloc fail\n");
  832. ret = -ENOMEM;
  833. goto free_dma;
  834. }
  835. frame->mv.addr = dma_alloc_coherent(&dev->pci->dev,
  836. H264_MV_BUF_SIZE,
  837. &frame->mv.dma_addr,
  838. GFP_KERNEL | GFP_DMA32);
  839. if (!frame->mv.addr) {
  840. dev_err(&dev->pci->dev, "dma alloc fail\n");
  841. ret = -ENOMEM;
  842. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  843. frame->vlc.addr, frame->vlc.dma_addr);
  844. goto free_dma;
  845. }
  846. last_dma_allocated = i;
  847. }
  848. tw5864_encoder_tables_upload(dev);
  849. /* Picture is distorted without this block */
  850. /* use falling edge to sample 54M to 108M */
  851. tw_indir_writeb(TW5864_INDIR_VD_108_POL, TW5864_INDIR_VD_108_POL_BOTH);
  852. tw_indir_writeb(TW5864_INDIR_CLK0_SEL, 0x00);
  853. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL0, 0x02);
  854. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL1, 0x02);
  855. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_CLK90_SEL, 0x02);
  856. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL0, 0x02);
  857. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL1, 0x02);
  858. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_CLK90_SEL, 0x02);
  859. /* video input reset */
  860. tw_indir_writeb(TW5864_INDIR_RESET, 0);
  861. tw_indir_writeb(TW5864_INDIR_RESET, TW5864_INDIR_RESET_VD |
  862. TW5864_INDIR_RESET_DLL | TW5864_INDIR_RESET_MUX_CORE);
  863. msleep(20);
  864. /*
  865. * Select Part A mode for all channels.
  866. * tw_setl instead of tw_clearl for Part B mode.
  867. *
  868. * I guess "Part B" is primarily for downscaled version of same channel
  869. * which goes in Part A of same bus
  870. */
  871. tw_writel(TW5864_FULL_HALF_MODE_SEL, 0);
  872. tw_indir_writeb(TW5864_INDIR_PV_VD_CK_POL,
  873. TW5864_INDIR_PV_VD_CK_POL_VD(0) |
  874. TW5864_INDIR_PV_VD_CK_POL_VD(1) |
  875. TW5864_INDIR_PV_VD_CK_POL_VD(2) |
  876. TW5864_INDIR_PV_VD_CK_POL_VD(3));
  877. spin_lock_irqsave(&dev->slock, flags);
  878. dev->encoder_busy = 0;
  879. dev->h264_buf_r_index = 0;
  880. dev->h264_buf_w_index = 0;
  881. tw_writel(TW5864_VLC_STREAM_BASE_ADDR,
  882. dev->h264_buf[dev->h264_buf_w_index].vlc.dma_addr);
  883. tw_writel(TW5864_MV_STREAM_BASE_ADDR,
  884. dev->h264_buf[dev->h264_buf_w_index].mv.dma_addr);
  885. spin_unlock_irqrestore(&dev->slock, flags);
  886. tw_writel(TW5864_SEN_EN_CH, 0x000f);
  887. tw_writel(TW5864_H264EN_CH_EN, 0x000f);
  888. tw_writel(TW5864_H264EN_BUS0_MAP, 0x00000000);
  889. tw_writel(TW5864_H264EN_BUS1_MAP, 0x00001111);
  890. tw_writel(TW5864_H264EN_BUS2_MAP, 0x00002222);
  891. tw_writel(TW5864_H264EN_BUS3_MAP, 0x00003333);
  892. /*
  893. * Quote from Intersil (manufacturer):
  894. * 0x0038 is managed by HW, and by default it won't pass the pointer set
  895. * at 0x0010. So if you don't do encoding, 0x0038 should stay at '3'
  896. * (with 4 frames in buffer). If you encode one frame and then move
  897. * 0x0010 to '1' for example, HW will take one more frame and set it to
  898. * buffer #0, and then you should see 0x0038 is set to '0'. There is
  899. * only one HW encoder engine, so 4 channels cannot get encoded
  900. * simultaneously. But each channel does have its own buffer (for
  901. * original frames and reconstructed frames). So there is no problem to
  902. * manage encoding for 4 channels at same time and no need to force
  903. * I-frames in switching channels.
  904. * End of quote.
  905. *
  906. * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0 (for any channel), we
  907. * have no "rolling" (until we change this value).
  908. * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0x3, it starts to roll
  909. * continuously together with 0x0038.
  910. */
  911. tw_writel(TW5864_ENC_BUF_PTR_REC1, 0x00ff);
  912. tw_writel(TW5864_PCI_INTTM_SCALE, 0);
  913. tw_writel(TW5864_INTERLACING, TW5864_DI_EN);
  914. tw_writel(TW5864_MASTER_ENB_REG, TW5864_PCI_VLC_INTR_ENB);
  915. tw_writel(TW5864_PCI_INTR_CTL,
  916. TW5864_TIMER_INTR_ENB | TW5864_PCI_MAST_ENB |
  917. TW5864_MVD_VLC_MAST_ENB);
  918. dev->irqmask |= TW5864_INTR_VLC_DONE | TW5864_INTR_TIMER;
  919. tw5864_irqmask_apply(dev);
  920. tasklet_init(&dev->tasklet, tw5864_handle_frame_task,
  921. (unsigned long)dev);
  922. for (i = 0; i < TW5864_INPUTS; i++) {
  923. dev->inputs[i].root = dev;
  924. dev->inputs[i].nr = i;
  925. ret = tw5864_video_input_init(&dev->inputs[i], video_nr[i]);
  926. if (ret)
  927. goto fini_video_inputs;
  928. last_input_nr_registered = i;
  929. }
  930. return 0;
  931. fini_video_inputs:
  932. for (i = last_input_nr_registered; i >= 0; i--)
  933. tw5864_video_input_fini(&dev->inputs[i]);
  934. tasklet_kill(&dev->tasklet);
  935. free_dma:
  936. for (i = last_dma_allocated; i >= 0; i--) {
  937. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  938. dev->h264_buf[i].vlc.addr,
  939. dev->h264_buf[i].vlc.dma_addr);
  940. dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
  941. dev->h264_buf[i].mv.addr,
  942. dev->h264_buf[i].mv.dma_addr);
  943. }
  944. return ret;
  945. }
  946. static int tw5864_video_input_init(struct tw5864_input *input, int video_nr)
  947. {
  948. struct tw5864_dev *dev = input->root;
  949. int ret;
  950. struct v4l2_ctrl_handler *hdl = &input->hdl;
  951. mutex_init(&input->lock);
  952. spin_lock_init(&input->slock);
  953. /* setup video buffers queue */
  954. INIT_LIST_HEAD(&input->active);
  955. input->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  956. input->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  957. input->vidq.io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
  958. input->vidq.ops = &tw5864_video_qops;
  959. input->vidq.mem_ops = &vb2_dma_contig_memops;
  960. input->vidq.drv_priv = input;
  961. input->vidq.gfp_flags = 0;
  962. input->vidq.buf_struct_size = sizeof(struct tw5864_buf);
  963. input->vidq.lock = &input->lock;
  964. input->vidq.min_buffers_needed = 2;
  965. input->vidq.dev = &input->root->pci->dev;
  966. ret = vb2_queue_init(&input->vidq);
  967. if (ret)
  968. goto free_mutex;
  969. input->vdev = tw5864_video_template;
  970. input->vdev.v4l2_dev = &input->root->v4l2_dev;
  971. input->vdev.lock = &input->lock;
  972. input->vdev.queue = &input->vidq;
  973. video_set_drvdata(&input->vdev, input);
  974. /* Initialize the device control structures */
  975. v4l2_ctrl_handler_init(hdl, 6);
  976. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  977. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  978. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  979. V4L2_CID_CONTRAST, 0, 255, 1, 100);
  980. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  981. V4L2_CID_SATURATION, 0, 255, 1, 128);
  982. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_HUE, -128, 127, 1, 0);
  983. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE,
  984. 1, MAX_GOP_SIZE, 1, GOP_SIZE);
  985. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  986. V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 28, 51, 1, QP_VALUE);
  987. v4l2_ctrl_new_std_menu(hdl, &tw5864_ctrl_ops,
  988. V4L2_CID_DETECT_MD_MODE,
  989. V4L2_DETECT_MD_MODE_THRESHOLD_GRID, 0,
  990. V4L2_DETECT_MD_MODE_DISABLED);
  991. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  992. V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD,
  993. tw5864_md_thresholds.min, tw5864_md_thresholds.max,
  994. tw5864_md_thresholds.step, tw5864_md_thresholds.def);
  995. input->md_threshold_grid_ctrl =
  996. v4l2_ctrl_new_custom(hdl, &tw5864_md_thresholds, NULL);
  997. if (hdl->error) {
  998. ret = hdl->error;
  999. goto free_v4l2_hdl;
  1000. }
  1001. input->vdev.ctrl_handler = hdl;
  1002. v4l2_ctrl_handler_setup(hdl);
  1003. input->qp = QP_VALUE;
  1004. input->gop = GOP_SIZE;
  1005. input->frame_interval = 1;
  1006. ret = video_register_device(&input->vdev, VFL_TYPE_GRABBER, video_nr);
  1007. if (ret)
  1008. goto free_v4l2_hdl;
  1009. dev_info(&input->root->pci->dev, "Registered video device %s\n",
  1010. video_device_node_name(&input->vdev));
  1011. /*
  1012. * Set default video standard. Doesn't matter which, the detected value
  1013. * will be found out by VIDIOC_QUERYSTD handler.
  1014. */
  1015. input->v4l2_std = V4L2_STD_NTSC_M;
  1016. input->std = STD_NTSC;
  1017. tw_indir_writeb(TW5864_INDIR_VIN_E(video_nr), 0x07);
  1018. /* to initiate auto format recognition */
  1019. tw_indir_writeb(TW5864_INDIR_VIN_F(video_nr), 0xff);
  1020. return 0;
  1021. free_v4l2_hdl:
  1022. v4l2_ctrl_handler_free(hdl);
  1023. vb2_queue_release(&input->vidq);
  1024. free_mutex:
  1025. mutex_destroy(&input->lock);
  1026. return ret;
  1027. }
  1028. static void tw5864_video_input_fini(struct tw5864_input *dev)
  1029. {
  1030. video_unregister_device(&dev->vdev);
  1031. v4l2_ctrl_handler_free(&dev->hdl);
  1032. vb2_queue_release(&dev->vidq);
  1033. }
  1034. void tw5864_video_fini(struct tw5864_dev *dev)
  1035. {
  1036. int i;
  1037. tasklet_kill(&dev->tasklet);
  1038. for (i = 0; i < TW5864_INPUTS; i++)
  1039. tw5864_video_input_fini(&dev->inputs[i]);
  1040. for (i = 0; i < H264_BUF_CNT; i++) {
  1041. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  1042. dev->h264_buf[i].vlc.addr,
  1043. dev->h264_buf[i].vlc.dma_addr);
  1044. dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
  1045. dev->h264_buf[i].mv.addr,
  1046. dev->h264_buf[i].mv.dma_addr);
  1047. }
  1048. }
  1049. void tw5864_prepare_frame_headers(struct tw5864_input *input)
  1050. {
  1051. struct tw5864_buf *vb = input->vb;
  1052. u8 *dst;
  1053. size_t dst_space;
  1054. unsigned long flags;
  1055. if (!vb) {
  1056. spin_lock_irqsave(&input->slock, flags);
  1057. if (list_empty(&input->active)) {
  1058. spin_unlock_irqrestore(&input->slock, flags);
  1059. input->vb = NULL;
  1060. return;
  1061. }
  1062. vb = list_first_entry(&input->active, struct tw5864_buf, list);
  1063. list_del(&vb->list);
  1064. spin_unlock_irqrestore(&input->slock, flags);
  1065. }
  1066. dst = vb2_plane_vaddr(&vb->vb.vb2_buf, 0);
  1067. dst_space = vb2_plane_size(&vb->vb.vb2_buf, 0);
  1068. /*
  1069. * Low-level bitstream writing functions don't have a fine way to say
  1070. * correctly that supplied buffer is too small. So we just check there
  1071. * and warn, and don't care at lower level.
  1072. * Currently all headers take below 32 bytes.
  1073. * The buffer is supposed to have plenty of free space at this point,
  1074. * anyway.
  1075. */
  1076. if (WARN_ON_ONCE(dst_space < 128))
  1077. return;
  1078. /*
  1079. * Generate H264 headers:
  1080. * If this is first frame, put SPS and PPS
  1081. */
  1082. if (input->frame_gop_seqno == 0)
  1083. tw5864_h264_put_stream_header(&dst, &dst_space, input->qp,
  1084. input->width, input->height);
  1085. /* Put slice header */
  1086. tw5864_h264_put_slice_header(&dst, &dst_space, input->h264_idr_pic_id,
  1087. input->frame_gop_seqno,
  1088. &input->tail_nb_bits, &input->tail);
  1089. input->vb = vb;
  1090. input->buf_cur_ptr = dst;
  1091. input->buf_cur_space_left = dst_space;
  1092. }
  1093. /*
  1094. * Returns heuristic motion detection metric value from known components of
  1095. * hardware-provided Motion Vector Data.
  1096. */
  1097. static unsigned int tw5864_md_metric_from_mvd(u32 mvd)
  1098. {
  1099. /*
  1100. * Format of motion vector data exposed by tw5864, according to
  1101. * manufacturer:
  1102. * mv_x 10 bits
  1103. * mv_y 10 bits
  1104. * non_zero_members 8 bits
  1105. * mb_type 3 bits
  1106. * reserved 1 bit
  1107. *
  1108. * non_zero_members: number of non-zero residuals in each macro block
  1109. * after quantization
  1110. *
  1111. * unsigned int reserved = mvd >> 31;
  1112. * unsigned int mb_type = (mvd >> 28) & 0x7;
  1113. * unsigned int non_zero_members = (mvd >> 20) & 0xff;
  1114. */
  1115. unsigned int mv_y = (mvd >> 10) & 0x3ff;
  1116. unsigned int mv_x = mvd & 0x3ff;
  1117. /* heuristic: */
  1118. mv_x &= 0x0f;
  1119. mv_y &= 0x0f;
  1120. return mv_y + mv_x;
  1121. }
  1122. static int tw5864_is_motion_triggered(struct tw5864_h264_frame *frame)
  1123. {
  1124. struct tw5864_input *input = frame->input;
  1125. u32 *mv = (u32 *)frame->mv.addr;
  1126. int i;
  1127. int detected = 0;
  1128. for (i = 0; i < MD_CELLS; i++) {
  1129. const u16 thresh = input->md_threshold_grid_values[i];
  1130. const unsigned int metric = tw5864_md_metric_from_mvd(mv[i]);
  1131. if (metric > thresh)
  1132. detected = 1;
  1133. if (detected)
  1134. break;
  1135. }
  1136. return detected;
  1137. }
  1138. static void tw5864_handle_frame_task(unsigned long data)
  1139. {
  1140. struct tw5864_dev *dev = (struct tw5864_dev *)data;
  1141. unsigned long flags;
  1142. int batch_size = H264_BUF_CNT;
  1143. spin_lock_irqsave(&dev->slock, flags);
  1144. while (dev->h264_buf_r_index != dev->h264_buf_w_index && batch_size--) {
  1145. struct tw5864_h264_frame *frame =
  1146. &dev->h264_buf[dev->h264_buf_r_index];
  1147. spin_unlock_irqrestore(&dev->slock, flags);
  1148. dma_sync_single_for_cpu(&dev->pci->dev, frame->vlc.dma_addr,
  1149. H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
  1150. dma_sync_single_for_cpu(&dev->pci->dev, frame->mv.dma_addr,
  1151. H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
  1152. tw5864_handle_frame(frame);
  1153. dma_sync_single_for_device(&dev->pci->dev, frame->vlc.dma_addr,
  1154. H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
  1155. dma_sync_single_for_device(&dev->pci->dev, frame->mv.dma_addr,
  1156. H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
  1157. spin_lock_irqsave(&dev->slock, flags);
  1158. dev->h264_buf_r_index++;
  1159. dev->h264_buf_r_index %= H264_BUF_CNT;
  1160. }
  1161. spin_unlock_irqrestore(&dev->slock, flags);
  1162. }
  1163. #ifdef DEBUG
  1164. static u32 tw5864_vlc_checksum(u32 *data, int len)
  1165. {
  1166. u32 val, count_len = len;
  1167. val = *data++;
  1168. while (((count_len >> 2) - 1) > 0) {
  1169. val ^= *data++;
  1170. count_len -= 4;
  1171. }
  1172. val ^= htonl((len >> 2));
  1173. return val;
  1174. }
  1175. #endif
  1176. static void tw5864_handle_frame(struct tw5864_h264_frame *frame)
  1177. {
  1178. #define SKIP_VLCBUF_BYTES 3
  1179. struct tw5864_input *input = frame->input;
  1180. struct tw5864_dev *dev = input->root;
  1181. struct tw5864_buf *vb;
  1182. struct vb2_v4l2_buffer *v4l2_buf;
  1183. int frame_len = frame->vlc_len - SKIP_VLCBUF_BYTES;
  1184. u8 *dst = input->buf_cur_ptr;
  1185. u8 tail_mask, vlc_mask = 0;
  1186. int i;
  1187. u8 vlc_first_byte = ((u8 *)(frame->vlc.addr + SKIP_VLCBUF_BYTES))[0];
  1188. unsigned long flags;
  1189. int zero_run;
  1190. u8 *src;
  1191. u8 *src_end;
  1192. #ifdef DEBUG
  1193. if (frame->checksum !=
  1194. tw5864_vlc_checksum((u32 *)frame->vlc.addr, frame_len))
  1195. dev_err(&dev->pci->dev,
  1196. "Checksum of encoded frame doesn't match!\n");
  1197. #endif
  1198. spin_lock_irqsave(&input->slock, flags);
  1199. vb = input->vb;
  1200. input->vb = NULL;
  1201. spin_unlock_irqrestore(&input->slock, flags);
  1202. v4l2_buf = to_vb2_v4l2_buffer(&vb->vb.vb2_buf);
  1203. if (!vb) { /* Gone because of disabling */
  1204. dev_dbg(&dev->pci->dev, "vb is empty, dropping frame\n");
  1205. return;
  1206. }
  1207. /*
  1208. * Check for space.
  1209. * Mind the overhead of startcode emulation prevention.
  1210. */
  1211. if (input->buf_cur_space_left < frame_len * 5 / 4) {
  1212. dev_err_once(&dev->pci->dev,
  1213. "Left space in vb2 buffer, %d bytes, is less than considered safely enough to put frame of length %d. Dropping this frame.\n",
  1214. input->buf_cur_space_left, frame_len);
  1215. return;
  1216. }
  1217. for (i = 0; i < 8 - input->tail_nb_bits; i++)
  1218. vlc_mask |= 1 << i;
  1219. tail_mask = (~vlc_mask) & 0xff;
  1220. dst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask);
  1221. frame_len--;
  1222. dst++;
  1223. /* H.264 startcode emulation prevention */
  1224. src = frame->vlc.addr + SKIP_VLCBUF_BYTES + 1;
  1225. src_end = src + frame_len;
  1226. zero_run = 0;
  1227. for (; src < src_end; src++) {
  1228. if (zero_run < 2) {
  1229. if (*src == 0)
  1230. ++zero_run;
  1231. else
  1232. zero_run = 0;
  1233. } else {
  1234. if ((*src & ~0x03) == 0)
  1235. *dst++ = 0x03;
  1236. zero_run = *src == 0;
  1237. }
  1238. *dst++ = *src;
  1239. }
  1240. vb2_set_plane_payload(&vb->vb.vb2_buf, 0,
  1241. dst - (u8 *)vb2_plane_vaddr(&vb->vb.vb2_buf, 0));
  1242. vb->vb.vb2_buf.timestamp = frame->timestamp;
  1243. v4l2_buf->field = V4L2_FIELD_INTERLACED;
  1244. v4l2_buf->sequence = frame->seqno;
  1245. /* Check for motion flags */
  1246. if (frame->gop_seqno /* P-frame */ &&
  1247. tw5864_is_motion_triggered(frame)) {
  1248. struct v4l2_event ev = {
  1249. .type = V4L2_EVENT_MOTION_DET,
  1250. .u.motion_det = {
  1251. .flags = V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ,
  1252. .frame_sequence = v4l2_buf->sequence,
  1253. },
  1254. };
  1255. v4l2_event_queue(&input->vdev, &ev);
  1256. }
  1257. vb2_buffer_done(&vb->vb.vb2_buf, VB2_BUF_STATE_DONE);
  1258. }
  1259. static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std)
  1260. {
  1261. switch (std) {
  1262. case STD_NTSC: return V4L2_STD_NTSC_M;
  1263. case STD_PAL: return V4L2_STD_PAL_B;
  1264. case STD_SECAM: return V4L2_STD_SECAM_B;
  1265. case STD_NTSC443: return V4L2_STD_NTSC_443;
  1266. case STD_PAL_M: return V4L2_STD_PAL_M;
  1267. case STD_PAL_CN: return V4L2_STD_PAL_Nc;
  1268. case STD_PAL_60: return V4L2_STD_PAL_60;
  1269. case STD_INVALID: return V4L2_STD_UNKNOWN;
  1270. }
  1271. return 0;
  1272. }
  1273. static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std)
  1274. {
  1275. if (v4l2_std & V4L2_STD_NTSC_M)
  1276. return STD_NTSC;
  1277. if (v4l2_std & V4L2_STD_PAL_B)
  1278. return STD_PAL;
  1279. if (v4l2_std & V4L2_STD_SECAM_B)
  1280. return STD_SECAM;
  1281. if (v4l2_std & V4L2_STD_NTSC_443)
  1282. return STD_NTSC443;
  1283. if (v4l2_std & V4L2_STD_PAL_M)
  1284. return STD_PAL_M;
  1285. if (v4l2_std & V4L2_STD_PAL_Nc)
  1286. return STD_PAL_CN;
  1287. if (v4l2_std & V4L2_STD_PAL_60)
  1288. return STD_PAL_60;
  1289. return STD_INVALID;
  1290. }
  1291. static void tw5864_encoder_tables_upload(struct tw5864_dev *dev)
  1292. {
  1293. int i;
  1294. tw_writel(TW5864_VLC_RD, 0x1);
  1295. for (i = 0; i < VLC_LOOKUP_TABLE_LEN; i++) {
  1296. tw_writel((TW5864_VLC_STREAM_MEM_START + i * 4),
  1297. encoder_vlc_lookup_table[i]);
  1298. }
  1299. tw_writel(TW5864_VLC_RD, 0x0);
  1300. for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
  1301. tw_writel((TW5864_QUAN_TAB + i * 4),
  1302. forward_quantization_table[i]);
  1303. }
  1304. for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
  1305. tw_writel((TW5864_QUAN_TAB + i * 4),
  1306. inverse_quantization_table[i]);
  1307. }
  1308. }