ddbridge-core.c 43 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758
  1. /*
  2. * ddbridge.c: Digital Devices PCIe bridge driver
  3. *
  4. * Copyright (C) 2010-2011 Digital Devices GmbH
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 only, as published by the Free Software Foundation.
  9. *
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20. * 02110-1301, USA
  21. * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include <linux/poll.h>
  29. #include <linux/io.h>
  30. #include <linux/pci.h>
  31. #include <linux/pci_ids.h>
  32. #include <linux/timer.h>
  33. #include <linux/i2c.h>
  34. #include <linux/swab.h>
  35. #include <linux/vmalloc.h>
  36. #include "ddbridge.h"
  37. #include "ddbridge-regs.h"
  38. #include "tda18271c2dd.h"
  39. #include "stv6110x.h"
  40. #include "stv090x.h"
  41. #include "lnbh24.h"
  42. #include "drxk.h"
  43. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  44. /* MSI had problems with lost interrupts, fixed but needs testing */
  45. #undef CONFIG_PCI_MSI
  46. /******************************************************************************/
  47. static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val)
  48. {
  49. struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
  50. .buf = val, .len = 1 } };
  51. return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
  52. }
  53. static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val)
  54. {
  55. struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
  56. .buf = &reg, .len = 1 },
  57. {.addr = adr, .flags = I2C_M_RD,
  58. .buf = val, .len = 1 } };
  59. return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
  60. }
  61. static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr,
  62. u16 reg, u8 *val)
  63. {
  64. u8 msg[2] = {reg>>8, reg&0xff};
  65. struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
  66. .buf = msg, .len = 2},
  67. {.addr = adr, .flags = I2C_M_RD,
  68. .buf = val, .len = 1} };
  69. return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1;
  70. }
  71. static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
  72. {
  73. struct ddb *dev = i2c->dev;
  74. long stat;
  75. u32 val;
  76. i2c->done = 0;
  77. ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND);
  78. stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ);
  79. if (stat == 0) {
  80. printk(KERN_ERR "I2C timeout\n");
  81. { /* MSI debugging*/
  82. u32 istat = ddbreadl(INTERRUPT_STATUS);
  83. printk(KERN_ERR "IRS %08x\n", istat);
  84. ddbwritel(istat, INTERRUPT_ACK);
  85. }
  86. return -EIO;
  87. }
  88. val = ddbreadl(i2c->regs+I2C_COMMAND);
  89. if (val & 0x70000)
  90. return -EIO;
  91. return 0;
  92. }
  93. static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
  94. struct i2c_msg msg[], int num)
  95. {
  96. struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter);
  97. struct ddb *dev = i2c->dev;
  98. u8 addr = 0;
  99. if (num)
  100. addr = msg[0].addr;
  101. if (num == 2 && msg[1].flags & I2C_M_RD &&
  102. !(msg[0].flags & I2C_M_RD)) {
  103. memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf,
  104. msg[0].buf, msg[0].len);
  105. ddbwritel(msg[0].len|(msg[1].len << 16),
  106. i2c->regs+I2C_TASKLENGTH);
  107. if (!ddb_i2c_cmd(i2c, addr, 1)) {
  108. memcpy_fromio(msg[1].buf,
  109. dev->regs + I2C_TASKMEM_BASE + i2c->rbuf,
  110. msg[1].len);
  111. return num;
  112. }
  113. }
  114. if (num == 1 && !(msg[0].flags & I2C_M_RD)) {
  115. ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len);
  116. ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH);
  117. if (!ddb_i2c_cmd(i2c, addr, 2))
  118. return num;
  119. }
  120. if (num == 1 && (msg[0].flags & I2C_M_RD)) {
  121. ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH);
  122. if (!ddb_i2c_cmd(i2c, addr, 3)) {
  123. ddbcpyfrom(msg[0].buf,
  124. I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len);
  125. return num;
  126. }
  127. }
  128. return -EIO;
  129. }
  130. static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
  131. {
  132. return I2C_FUNC_SMBUS_EMUL;
  133. }
  134. static struct i2c_algorithm ddb_i2c_algo = {
  135. .master_xfer = ddb_i2c_master_xfer,
  136. .functionality = ddb_i2c_functionality,
  137. };
  138. static void ddb_i2c_release(struct ddb *dev)
  139. {
  140. int i;
  141. struct ddb_i2c *i2c;
  142. struct i2c_adapter *adap;
  143. for (i = 0; i < dev->info->port_num; i++) {
  144. i2c = &dev->i2c[i];
  145. adap = &i2c->adap;
  146. i2c_del_adapter(adap);
  147. }
  148. }
  149. static int ddb_i2c_init(struct ddb *dev)
  150. {
  151. int i, j, stat = 0;
  152. struct ddb_i2c *i2c;
  153. struct i2c_adapter *adap;
  154. for (i = 0; i < dev->info->port_num; i++) {
  155. i2c = &dev->i2c[i];
  156. i2c->dev = dev;
  157. i2c->nr = i;
  158. i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4);
  159. i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8);
  160. i2c->regs = 0x80 + i * 0x20;
  161. ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING);
  162. ddbwritel((i2c->rbuf << 16) | i2c->wbuf,
  163. i2c->regs + I2C_TASKADDRESS);
  164. init_waitqueue_head(&i2c->wq);
  165. adap = &i2c->adap;
  166. i2c_set_adapdata(adap, i2c);
  167. #ifdef I2C_ADAP_CLASS_TV_DIGITAL
  168. adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
  169. #else
  170. #ifdef I2C_CLASS_TV_ANALOG
  171. adap->class = I2C_CLASS_TV_ANALOG;
  172. #endif
  173. #endif
  174. strcpy(adap->name, "ddbridge");
  175. adap->algo = &ddb_i2c_algo;
  176. adap->algo_data = (void *)i2c;
  177. adap->dev.parent = &dev->pdev->dev;
  178. stat = i2c_add_adapter(adap);
  179. if (stat)
  180. break;
  181. }
  182. if (stat)
  183. for (j = 0; j < i; j++) {
  184. i2c = &dev->i2c[j];
  185. adap = &i2c->adap;
  186. i2c_del_adapter(adap);
  187. }
  188. return stat;
  189. }
  190. /******************************************************************************/
  191. /******************************************************************************/
  192. /******************************************************************************/
  193. #if 0
  194. static void set_table(struct ddb *dev, u32 off,
  195. dma_addr_t *pbuf, u32 num)
  196. {
  197. u32 i, base;
  198. u64 mem;
  199. base = DMA_BASE_ADDRESS_TABLE + off;
  200. for (i = 0; i < num; i++) {
  201. mem = pbuf[i];
  202. ddbwritel(mem & 0xffffffff, base + i * 8);
  203. ddbwritel(mem >> 32, base + i * 8 + 4);
  204. }
  205. }
  206. #endif
  207. static void ddb_address_table(struct ddb *dev)
  208. {
  209. u32 i, j, base;
  210. u64 mem;
  211. dma_addr_t *pbuf;
  212. for (i = 0; i < dev->info->port_num * 2; i++) {
  213. base = DMA_BASE_ADDRESS_TABLE + i * 0x100;
  214. pbuf = dev->input[i].pbuf;
  215. for (j = 0; j < dev->input[i].dma_buf_num; j++) {
  216. mem = pbuf[j];
  217. ddbwritel(mem & 0xffffffff, base + j * 8);
  218. ddbwritel(mem >> 32, base + j * 8 + 4);
  219. }
  220. }
  221. for (i = 0; i < dev->info->port_num; i++) {
  222. base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100;
  223. pbuf = dev->output[i].pbuf;
  224. for (j = 0; j < dev->output[i].dma_buf_num; j++) {
  225. mem = pbuf[j];
  226. ddbwritel(mem & 0xffffffff, base + j * 8);
  227. ddbwritel(mem >> 32, base + j * 8 + 4);
  228. }
  229. }
  230. }
  231. static void io_free(struct pci_dev *pdev, u8 **vbuf,
  232. dma_addr_t *pbuf, u32 size, int num)
  233. {
  234. int i;
  235. for (i = 0; i < num; i++) {
  236. if (vbuf[i]) {
  237. pci_free_consistent(pdev, size, vbuf[i], pbuf[i]);
  238. vbuf[i] = NULL;
  239. }
  240. }
  241. }
  242. static int io_alloc(struct pci_dev *pdev, u8 **vbuf,
  243. dma_addr_t *pbuf, u32 size, int num)
  244. {
  245. int i;
  246. for (i = 0; i < num; i++) {
  247. vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]);
  248. if (!vbuf[i])
  249. return -ENOMEM;
  250. }
  251. return 0;
  252. }
  253. static int ddb_buffers_alloc(struct ddb *dev)
  254. {
  255. int i;
  256. struct ddb_port *port;
  257. for (i = 0; i < dev->info->port_num; i++) {
  258. port = &dev->port[i];
  259. switch (port->class) {
  260. case DDB_PORT_TUNER:
  261. if (io_alloc(dev->pdev, port->input[0]->vbuf,
  262. port->input[0]->pbuf,
  263. port->input[0]->dma_buf_size,
  264. port->input[0]->dma_buf_num) < 0)
  265. return -1;
  266. if (io_alloc(dev->pdev, port->input[1]->vbuf,
  267. port->input[1]->pbuf,
  268. port->input[1]->dma_buf_size,
  269. port->input[1]->dma_buf_num) < 0)
  270. return -1;
  271. break;
  272. case DDB_PORT_CI:
  273. if (io_alloc(dev->pdev, port->input[0]->vbuf,
  274. port->input[0]->pbuf,
  275. port->input[0]->dma_buf_size,
  276. port->input[0]->dma_buf_num) < 0)
  277. return -1;
  278. if (io_alloc(dev->pdev, port->output->vbuf,
  279. port->output->pbuf,
  280. port->output->dma_buf_size,
  281. port->output->dma_buf_num) < 0)
  282. return -1;
  283. break;
  284. default:
  285. break;
  286. }
  287. }
  288. ddb_address_table(dev);
  289. return 0;
  290. }
  291. static void ddb_buffers_free(struct ddb *dev)
  292. {
  293. int i;
  294. struct ddb_port *port;
  295. for (i = 0; i < dev->info->port_num; i++) {
  296. port = &dev->port[i];
  297. io_free(dev->pdev, port->input[0]->vbuf,
  298. port->input[0]->pbuf,
  299. port->input[0]->dma_buf_size,
  300. port->input[0]->dma_buf_num);
  301. io_free(dev->pdev, port->input[1]->vbuf,
  302. port->input[1]->pbuf,
  303. port->input[1]->dma_buf_size,
  304. port->input[1]->dma_buf_num);
  305. io_free(dev->pdev, port->output->vbuf,
  306. port->output->pbuf,
  307. port->output->dma_buf_size,
  308. port->output->dma_buf_num);
  309. }
  310. }
  311. static void ddb_input_start(struct ddb_input *input)
  312. {
  313. struct ddb *dev = input->port->dev;
  314. spin_lock_irq(&input->lock);
  315. input->cbuf = 0;
  316. input->coff = 0;
  317. /* reset */
  318. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  319. ddbwritel(2, TS_INPUT_CONTROL(input->nr));
  320. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  321. ddbwritel((1 << 16) |
  322. (input->dma_buf_num << 11) |
  323. (input->dma_buf_size >> 7),
  324. DMA_BUFFER_SIZE(input->nr));
  325. ddbwritel(0, DMA_BUFFER_ACK(input->nr));
  326. ddbwritel(1, DMA_BASE_WRITE);
  327. ddbwritel(3, DMA_BUFFER_CONTROL(input->nr));
  328. ddbwritel(9, TS_INPUT_CONTROL(input->nr));
  329. input->running = 1;
  330. spin_unlock_irq(&input->lock);
  331. }
  332. static void ddb_input_stop(struct ddb_input *input)
  333. {
  334. struct ddb *dev = input->port->dev;
  335. spin_lock_irq(&input->lock);
  336. ddbwritel(0, TS_INPUT_CONTROL(input->nr));
  337. ddbwritel(0, DMA_BUFFER_CONTROL(input->nr));
  338. input->running = 0;
  339. spin_unlock_irq(&input->lock);
  340. }
  341. static void ddb_output_start(struct ddb_output *output)
  342. {
  343. struct ddb *dev = output->port->dev;
  344. spin_lock_irq(&output->lock);
  345. output->cbuf = 0;
  346. output->coff = 0;
  347. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  348. ddbwritel(2, TS_OUTPUT_CONTROL(output->nr));
  349. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  350. ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr));
  351. ddbwritel((1 << 16) |
  352. (output->dma_buf_num << 11) |
  353. (output->dma_buf_size >> 7),
  354. DMA_BUFFER_SIZE(output->nr + 8));
  355. ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8));
  356. ddbwritel(1, DMA_BASE_READ);
  357. ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8));
  358. /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */
  359. ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr));
  360. output->running = 1;
  361. spin_unlock_irq(&output->lock);
  362. }
  363. static void ddb_output_stop(struct ddb_output *output)
  364. {
  365. struct ddb *dev = output->port->dev;
  366. spin_lock_irq(&output->lock);
  367. ddbwritel(0, TS_OUTPUT_CONTROL(output->nr));
  368. ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8));
  369. output->running = 0;
  370. spin_unlock_irq(&output->lock);
  371. }
  372. static u32 ddb_output_free(struct ddb_output *output)
  373. {
  374. u32 idx, off, stat = output->stat;
  375. s32 diff;
  376. idx = (stat >> 11) & 0x1f;
  377. off = (stat & 0x7ff) << 7;
  378. if (output->cbuf != idx) {
  379. if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
  380. (output->dma_buf_size - output->coff <= 188))
  381. return 0;
  382. return 188;
  383. }
  384. diff = off - output->coff;
  385. if (diff <= 0 || diff > 188)
  386. return 188;
  387. return 0;
  388. }
  389. static ssize_t ddb_output_write(struct ddb_output *output,
  390. const __user u8 *buf, size_t count)
  391. {
  392. struct ddb *dev = output->port->dev;
  393. u32 idx, off, stat = output->stat;
  394. u32 left = count, len;
  395. idx = (stat >> 11) & 0x1f;
  396. off = (stat & 0x7ff) << 7;
  397. while (left) {
  398. len = output->dma_buf_size - output->coff;
  399. if ((((output->cbuf + 1) % output->dma_buf_num) == idx) &&
  400. (off == 0)) {
  401. if (len <= 188)
  402. break;
  403. len -= 188;
  404. }
  405. if (output->cbuf == idx) {
  406. if (off > output->coff) {
  407. #if 1
  408. len = off - output->coff;
  409. len -= (len % 188);
  410. if (len <= 188)
  411. #endif
  412. break;
  413. len -= 188;
  414. }
  415. }
  416. if (len > left)
  417. len = left;
  418. if (copy_from_user(output->vbuf[output->cbuf] + output->coff,
  419. buf, len))
  420. return -EIO;
  421. left -= len;
  422. buf += len;
  423. output->coff += len;
  424. if (output->coff == output->dma_buf_size) {
  425. output->coff = 0;
  426. output->cbuf = ((output->cbuf + 1) % output->dma_buf_num);
  427. }
  428. ddbwritel((output->cbuf << 11) | (output->coff >> 7),
  429. DMA_BUFFER_ACK(output->nr + 8));
  430. }
  431. return count - left;
  432. }
  433. static u32 ddb_input_avail(struct ddb_input *input)
  434. {
  435. struct ddb *dev = input->port->dev;
  436. u32 idx, off, stat = input->stat;
  437. u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr));
  438. idx = (stat >> 11) & 0x1f;
  439. off = (stat & 0x7ff) << 7;
  440. if (ctrl & 4) {
  441. printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl);
  442. ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr));
  443. return 0;
  444. }
  445. if (input->cbuf != idx)
  446. return 188;
  447. return 0;
  448. }
  449. static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count)
  450. {
  451. struct ddb *dev = input->port->dev;
  452. u32 left = count;
  453. u32 idx, free, stat = input->stat;
  454. int ret;
  455. idx = (stat >> 11) & 0x1f;
  456. while (left) {
  457. if (input->cbuf == idx)
  458. return count - left;
  459. free = input->dma_buf_size - input->coff;
  460. if (free > left)
  461. free = left;
  462. ret = copy_to_user(buf, input->vbuf[input->cbuf] +
  463. input->coff, free);
  464. if (ret)
  465. return -EFAULT;
  466. input->coff += free;
  467. if (input->coff == input->dma_buf_size) {
  468. input->coff = 0;
  469. input->cbuf = (input->cbuf+1) % input->dma_buf_num;
  470. }
  471. left -= free;
  472. ddbwritel((input->cbuf << 11) | (input->coff >> 7),
  473. DMA_BUFFER_ACK(input->nr));
  474. }
  475. return count;
  476. }
  477. /******************************************************************************/
  478. /******************************************************************************/
  479. /******************************************************************************/
  480. #if 0
  481. static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe)
  482. {
  483. int i;
  484. for (i = 0; i < dev->info->port_num * 2; i++) {
  485. if (dev->input[i].fe == fe)
  486. return &dev->input[i];
  487. }
  488. return NULL;
  489. }
  490. #endif
  491. static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
  492. {
  493. struct ddb_input *input = fe->sec_priv;
  494. struct ddb_port *port = input->port;
  495. int status;
  496. if (enable) {
  497. mutex_lock(&port->i2c_gate_lock);
  498. status = input->gate_ctrl(fe, 1);
  499. } else {
  500. status = input->gate_ctrl(fe, 0);
  501. mutex_unlock(&port->i2c_gate_lock);
  502. }
  503. return status;
  504. }
  505. static int demod_attach_drxk(struct ddb_input *input)
  506. {
  507. struct i2c_adapter *i2c = &input->port->i2c->adap;
  508. struct dvb_frontend *fe;
  509. struct drxk_config config;
  510. memset(&config, 0, sizeof(config));
  511. config.microcode_name = "drxk_a3.mc";
  512. config.qam_demod_parameter_count = 4;
  513. config.adr = 0x29 + (input->nr & 1);
  514. fe = input->fe = dvb_attach(drxk_attach, &config, i2c);
  515. if (!input->fe) {
  516. printk(KERN_ERR "No DRXK found!\n");
  517. return -ENODEV;
  518. }
  519. fe->sec_priv = input;
  520. input->gate_ctrl = fe->ops.i2c_gate_ctrl;
  521. fe->ops.i2c_gate_ctrl = drxk_gate_ctrl;
  522. return 0;
  523. }
  524. static int tuner_attach_tda18271(struct ddb_input *input)
  525. {
  526. struct i2c_adapter *i2c = &input->port->i2c->adap;
  527. struct dvb_frontend *fe;
  528. if (input->fe->ops.i2c_gate_ctrl)
  529. input->fe->ops.i2c_gate_ctrl(input->fe, 1);
  530. fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60);
  531. if (!fe) {
  532. printk(KERN_ERR "No TDA18271 found!\n");
  533. return -ENODEV;
  534. }
  535. if (input->fe->ops.i2c_gate_ctrl)
  536. input->fe->ops.i2c_gate_ctrl(input->fe, 0);
  537. return 0;
  538. }
  539. /******************************************************************************/
  540. /******************************************************************************/
  541. /******************************************************************************/
  542. static struct stv090x_config stv0900 = {
  543. .device = STV0900,
  544. .demod_mode = STV090x_DUAL,
  545. .clk_mode = STV090x_CLK_EXT,
  546. .xtal = 27000000,
  547. .address = 0x69,
  548. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  549. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  550. .repeater_level = STV090x_RPTLEVEL_16,
  551. .adc1_range = STV090x_ADC_1Vpp,
  552. .adc2_range = STV090x_ADC_1Vpp,
  553. .diseqc_envelope_mode = true,
  554. };
  555. static struct stv090x_config stv0900_aa = {
  556. .device = STV0900,
  557. .demod_mode = STV090x_DUAL,
  558. .clk_mode = STV090x_CLK_EXT,
  559. .xtal = 27000000,
  560. .address = 0x68,
  561. .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  562. .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED,
  563. .repeater_level = STV090x_RPTLEVEL_16,
  564. .adc1_range = STV090x_ADC_1Vpp,
  565. .adc2_range = STV090x_ADC_1Vpp,
  566. .diseqc_envelope_mode = true,
  567. };
  568. static struct stv6110x_config stv6110a = {
  569. .addr = 0x60,
  570. .refclk = 27000000,
  571. .clk_div = 1,
  572. };
  573. static struct stv6110x_config stv6110b = {
  574. .addr = 0x63,
  575. .refclk = 27000000,
  576. .clk_div = 1,
  577. };
  578. static int demod_attach_stv0900(struct ddb_input *input, int type)
  579. {
  580. struct i2c_adapter *i2c = &input->port->i2c->adap;
  581. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  582. input->fe = dvb_attach(stv090x_attach, feconf, i2c,
  583. (input->nr & 1) ? STV090x_DEMODULATOR_1
  584. : STV090x_DEMODULATOR_0);
  585. if (!input->fe) {
  586. printk(KERN_ERR "No STV0900 found!\n");
  587. return -ENODEV;
  588. }
  589. if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0,
  590. 0, (input->nr & 1) ?
  591. (0x09 - type) : (0x0b - type))) {
  592. printk(KERN_ERR "No LNBH24 found!\n");
  593. return -ENODEV;
  594. }
  595. return 0;
  596. }
  597. static int tuner_attach_stv6110(struct ddb_input *input, int type)
  598. {
  599. struct i2c_adapter *i2c = &input->port->i2c->adap;
  600. struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900;
  601. struct stv6110x_config *tunerconf = (input->nr & 1) ?
  602. &stv6110b : &stv6110a;
  603. const struct stv6110x_devctl *ctl;
  604. ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c);
  605. if (!ctl) {
  606. printk(KERN_ERR "No STV6110X found!\n");
  607. return -ENODEV;
  608. }
  609. printk(KERN_INFO "attach tuner input %d adr %02x\n",
  610. input->nr, tunerconf->addr);
  611. feconf->tuner_init = ctl->tuner_init;
  612. feconf->tuner_sleep = ctl->tuner_sleep;
  613. feconf->tuner_set_mode = ctl->tuner_set_mode;
  614. feconf->tuner_set_frequency = ctl->tuner_set_frequency;
  615. feconf->tuner_get_frequency = ctl->tuner_get_frequency;
  616. feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth;
  617. feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth;
  618. feconf->tuner_set_bbgain = ctl->tuner_set_bbgain;
  619. feconf->tuner_get_bbgain = ctl->tuner_get_bbgain;
  620. feconf->tuner_set_refclk = ctl->tuner_set_refclk;
  621. feconf->tuner_get_status = ctl->tuner_get_status;
  622. return 0;
  623. }
  624. static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
  625. int (*start_feed)(struct dvb_demux_feed *),
  626. int (*stop_feed)(struct dvb_demux_feed *),
  627. void *priv)
  628. {
  629. dvbdemux->priv = priv;
  630. dvbdemux->filternum = 256;
  631. dvbdemux->feednum = 256;
  632. dvbdemux->start_feed = start_feed;
  633. dvbdemux->stop_feed = stop_feed;
  634. dvbdemux->write_to_decoder = NULL;
  635. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  636. DMX_SECTION_FILTERING |
  637. DMX_MEMORY_BASED_FILTERING);
  638. return dvb_dmx_init(dvbdemux);
  639. }
  640. static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
  641. struct dvb_demux *dvbdemux,
  642. struct dmx_frontend *hw_frontend,
  643. struct dmx_frontend *mem_frontend,
  644. struct dvb_adapter *dvb_adapter)
  645. {
  646. int ret;
  647. dmxdev->filternum = 256;
  648. dmxdev->demux = &dvbdemux->dmx;
  649. dmxdev->capabilities = 0;
  650. ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
  651. if (ret < 0)
  652. return ret;
  653. hw_frontend->source = DMX_FRONTEND_0;
  654. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
  655. mem_frontend->source = DMX_MEMORY_FE;
  656. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
  657. return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
  658. }
  659. static int start_feed(struct dvb_demux_feed *dvbdmxfeed)
  660. {
  661. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  662. struct ddb_input *input = dvbdmx->priv;
  663. if (!input->users)
  664. ddb_input_start(input);
  665. return ++input->users;
  666. }
  667. static int stop_feed(struct dvb_demux_feed *dvbdmxfeed)
  668. {
  669. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  670. struct ddb_input *input = dvbdmx->priv;
  671. if (--input->users)
  672. return input->users;
  673. ddb_input_stop(input);
  674. return 0;
  675. }
  676. static void dvb_input_detach(struct ddb_input *input)
  677. {
  678. struct dvb_adapter *adap = &input->adap;
  679. struct dvb_demux *dvbdemux = &input->demux;
  680. switch (input->attached) {
  681. case 5:
  682. if (input->fe2)
  683. dvb_unregister_frontend(input->fe2);
  684. if (input->fe) {
  685. dvb_unregister_frontend(input->fe);
  686. dvb_frontend_detach(input->fe);
  687. input->fe = NULL;
  688. }
  689. case 4:
  690. dvb_net_release(&input->dvbnet);
  691. case 3:
  692. dvbdemux->dmx.close(&dvbdemux->dmx);
  693. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  694. &input->hw_frontend);
  695. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
  696. &input->mem_frontend);
  697. dvb_dmxdev_release(&input->dmxdev);
  698. case 2:
  699. dvb_dmx_release(&input->demux);
  700. case 1:
  701. dvb_unregister_adapter(adap);
  702. }
  703. input->attached = 0;
  704. }
  705. static int dvb_input_attach(struct ddb_input *input)
  706. {
  707. int ret;
  708. struct ddb_port *port = input->port;
  709. struct dvb_adapter *adap = &input->adap;
  710. struct dvb_demux *dvbdemux = &input->demux;
  711. ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE,
  712. &input->port->dev->pdev->dev,
  713. adapter_nr);
  714. if (ret < 0) {
  715. printk(KERN_ERR "ddbridge: Could not register adapter."
  716. "Check if you enabled enough adapters in dvb-core!\n");
  717. return ret;
  718. }
  719. input->attached = 1;
  720. ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
  721. start_feed,
  722. stop_feed, input);
  723. if (ret < 0)
  724. return ret;
  725. input->attached = 2;
  726. ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux,
  727. &input->hw_frontend,
  728. &input->mem_frontend, adap);
  729. if (ret < 0)
  730. return ret;
  731. input->attached = 3;
  732. ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux);
  733. if (ret < 0)
  734. return ret;
  735. input->attached = 4;
  736. input->fe = NULL;
  737. switch (port->type) {
  738. case DDB_TUNER_DVBS_ST:
  739. if (demod_attach_stv0900(input, 0) < 0)
  740. return -ENODEV;
  741. if (tuner_attach_stv6110(input, 0) < 0)
  742. return -ENODEV;
  743. if (input->fe) {
  744. if (dvb_register_frontend(adap, input->fe) < 0)
  745. return -ENODEV;
  746. }
  747. break;
  748. case DDB_TUNER_DVBS_ST_AA:
  749. if (demod_attach_stv0900(input, 1) < 0)
  750. return -ENODEV;
  751. if (tuner_attach_stv6110(input, 1) < 0)
  752. return -ENODEV;
  753. if (input->fe) {
  754. if (dvb_register_frontend(adap, input->fe) < 0)
  755. return -ENODEV;
  756. }
  757. break;
  758. case DDB_TUNER_DVBCT_TR:
  759. if (demod_attach_drxk(input) < 0)
  760. return -ENODEV;
  761. if (tuner_attach_tda18271(input) < 0)
  762. return -ENODEV;
  763. if (dvb_register_frontend(adap, input->fe) < 0)
  764. return -ENODEV;
  765. if (input->fe2) {
  766. if (dvb_register_frontend(adap, input->fe2) < 0)
  767. return -ENODEV;
  768. input->fe2->tuner_priv = input->fe->tuner_priv;
  769. memcpy(&input->fe2->ops.tuner_ops,
  770. &input->fe->ops.tuner_ops,
  771. sizeof(struct dvb_tuner_ops));
  772. }
  773. break;
  774. }
  775. input->attached = 5;
  776. return 0;
  777. }
  778. /****************************************************************************/
  779. /****************************************************************************/
  780. static ssize_t ts_write(struct file *file, const __user char *buf,
  781. size_t count, loff_t *ppos)
  782. {
  783. struct dvb_device *dvbdev = file->private_data;
  784. struct ddb_output *output = dvbdev->priv;
  785. size_t left = count;
  786. int stat;
  787. while (left) {
  788. if (ddb_output_free(output) < 188) {
  789. if (file->f_flags & O_NONBLOCK)
  790. break;
  791. if (wait_event_interruptible(
  792. output->wq, ddb_output_free(output) >= 188) < 0)
  793. break;
  794. }
  795. stat = ddb_output_write(output, buf, left);
  796. if (stat < 0)
  797. break;
  798. buf += stat;
  799. left -= stat;
  800. }
  801. return (left == count) ? -EAGAIN : (count - left);
  802. }
  803. static ssize_t ts_read(struct file *file, __user char *buf,
  804. size_t count, loff_t *ppos)
  805. {
  806. struct dvb_device *dvbdev = file->private_data;
  807. struct ddb_output *output = dvbdev->priv;
  808. struct ddb_input *input = output->port->input[0];
  809. int left, read;
  810. count -= count % 188;
  811. left = count;
  812. while (left) {
  813. if (ddb_input_avail(input) < 188) {
  814. if (file->f_flags & O_NONBLOCK)
  815. break;
  816. if (wait_event_interruptible(
  817. input->wq, ddb_input_avail(input) >= 188) < 0)
  818. break;
  819. }
  820. read = ddb_input_read(input, buf, left);
  821. if (read < 0)
  822. return read;
  823. left -= read;
  824. buf += read;
  825. }
  826. return (left == count) ? -EAGAIN : (count - left);
  827. }
  828. static unsigned int ts_poll(struct file *file, poll_table *wait)
  829. {
  830. /*
  831. struct dvb_device *dvbdev = file->private_data;
  832. struct ddb_output *output = dvbdev->priv;
  833. struct ddb_input *input = output->port->input[0];
  834. */
  835. unsigned int mask = 0;
  836. #if 0
  837. if (data_avail_to_read)
  838. mask |= POLLIN | POLLRDNORM;
  839. if (data_avail_to_write)
  840. mask |= POLLOUT | POLLWRNORM;
  841. poll_wait(file, &read_queue, wait);
  842. poll_wait(file, &write_queue, wait);
  843. #endif
  844. return mask;
  845. }
  846. static const struct file_operations ci_fops = {
  847. .owner = THIS_MODULE,
  848. .read = ts_read,
  849. .write = ts_write,
  850. .open = dvb_generic_open,
  851. .release = dvb_generic_release,
  852. .poll = ts_poll,
  853. };
  854. static struct dvb_device dvbdev_ci = {
  855. .readers = -1,
  856. .writers = -1,
  857. .users = -1,
  858. .fops = &ci_fops,
  859. };
  860. /****************************************************************************/
  861. /****************************************************************************/
  862. /****************************************************************************/
  863. static void input_tasklet(unsigned long data)
  864. {
  865. struct ddb_input *input = (struct ddb_input *) data;
  866. struct ddb *dev = input->port->dev;
  867. spin_lock(&input->lock);
  868. if (!input->running) {
  869. spin_unlock(&input->lock);
  870. return;
  871. }
  872. input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
  873. if (input->port->class == DDB_PORT_TUNER) {
  874. if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))
  875. printk(KERN_ERR "Overflow input %d\n", input->nr);
  876. while (input->cbuf != ((input->stat >> 11) & 0x1f)
  877. || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) {
  878. dvb_dmx_swfilter_packets(&input->demux,
  879. input->vbuf[input->cbuf],
  880. input->dma_buf_size / 188);
  881. input->cbuf = (input->cbuf + 1) % input->dma_buf_num;
  882. ddbwritel((input->cbuf << 11),
  883. DMA_BUFFER_ACK(input->nr));
  884. input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr));
  885. }
  886. }
  887. if (input->port->class == DDB_PORT_CI)
  888. wake_up(&input->wq);
  889. spin_unlock(&input->lock);
  890. }
  891. static void output_tasklet(unsigned long data)
  892. {
  893. struct ddb_output *output = (struct ddb_output *) data;
  894. struct ddb *dev = output->port->dev;
  895. spin_lock(&output->lock);
  896. if (!output->running) {
  897. spin_unlock(&output->lock);
  898. return;
  899. }
  900. output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8));
  901. wake_up(&output->wq);
  902. spin_unlock(&output->lock);
  903. }
  904. static struct cxd2099_cfg cxd_cfg = {
  905. .bitrate = 62000,
  906. .adr = 0x40,
  907. .polarity = 1,
  908. .clock_mode = 1,
  909. };
  910. static int ddb_ci_attach(struct ddb_port *port)
  911. {
  912. int ret;
  913. ret = dvb_register_adapter(&port->output->adap,
  914. "DDBridge",
  915. THIS_MODULE,
  916. &port->dev->pdev->dev,
  917. adapter_nr);
  918. if (ret < 0)
  919. return ret;
  920. port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap);
  921. if (!port->en) {
  922. dvb_unregister_adapter(&port->output->adap);
  923. return -ENODEV;
  924. }
  925. ddb_input_start(port->input[0]);
  926. ddb_output_start(port->output);
  927. dvb_ca_en50221_init(&port->output->adap,
  928. port->en, 0, 1);
  929. ret = dvb_register_device(&port->output->adap, &port->output->dev,
  930. &dvbdev_ci, (void *) port->output,
  931. DVB_DEVICE_SEC, 0);
  932. return ret;
  933. }
  934. static int ddb_port_attach(struct ddb_port *port)
  935. {
  936. int ret = 0;
  937. switch (port->class) {
  938. case DDB_PORT_TUNER:
  939. ret = dvb_input_attach(port->input[0]);
  940. if (ret < 0)
  941. break;
  942. ret = dvb_input_attach(port->input[1]);
  943. break;
  944. case DDB_PORT_CI:
  945. ret = ddb_ci_attach(port);
  946. break;
  947. default:
  948. break;
  949. }
  950. if (ret < 0)
  951. printk(KERN_ERR "port_attach on port %d failed\n", port->nr);
  952. return ret;
  953. }
  954. static int ddb_ports_attach(struct ddb *dev)
  955. {
  956. int i, ret = 0;
  957. struct ddb_port *port;
  958. for (i = 0; i < dev->info->port_num; i++) {
  959. port = &dev->port[i];
  960. ret = ddb_port_attach(port);
  961. if (ret < 0)
  962. break;
  963. }
  964. return ret;
  965. }
  966. static void ddb_ports_detach(struct ddb *dev)
  967. {
  968. int i;
  969. struct ddb_port *port;
  970. for (i = 0; i < dev->info->port_num; i++) {
  971. port = &dev->port[i];
  972. switch (port->class) {
  973. case DDB_PORT_TUNER:
  974. dvb_input_detach(port->input[0]);
  975. dvb_input_detach(port->input[1]);
  976. break;
  977. case DDB_PORT_CI:
  978. dvb_unregister_device(port->output->dev);
  979. if (port->en) {
  980. ddb_input_stop(port->input[0]);
  981. ddb_output_stop(port->output);
  982. dvb_ca_en50221_release(port->en);
  983. kfree(port->en);
  984. port->en = NULL;
  985. dvb_unregister_adapter(&port->output->adap);
  986. }
  987. break;
  988. }
  989. }
  990. }
  991. /****************************************************************************/
  992. /****************************************************************************/
  993. static int port_has_ci(struct ddb_port *port)
  994. {
  995. u8 val;
  996. return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1;
  997. }
  998. static int port_has_stv0900(struct ddb_port *port)
  999. {
  1000. u8 val;
  1001. if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0)
  1002. return 0;
  1003. return 1;
  1004. }
  1005. static int port_has_stv0900_aa(struct ddb_port *port)
  1006. {
  1007. u8 val;
  1008. if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0)
  1009. return 0;
  1010. return 1;
  1011. }
  1012. static int port_has_drxks(struct ddb_port *port)
  1013. {
  1014. u8 val;
  1015. if (i2c_read(&port->i2c->adap, 0x29, &val) < 0)
  1016. return 0;
  1017. if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0)
  1018. return 0;
  1019. return 1;
  1020. }
  1021. static void ddb_port_probe(struct ddb_port *port)
  1022. {
  1023. struct ddb *dev = port->dev;
  1024. char *modname = "NO MODULE";
  1025. port->class = DDB_PORT_NONE;
  1026. if (port_has_ci(port)) {
  1027. modname = "CI";
  1028. port->class = DDB_PORT_CI;
  1029. ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1030. } else if (port_has_stv0900(port)) {
  1031. modname = "DUAL DVB-S2";
  1032. port->class = DDB_PORT_TUNER;
  1033. port->type = DDB_TUNER_DVBS_ST;
  1034. ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1035. } else if (port_has_stv0900_aa(port)) {
  1036. modname = "DUAL DVB-S2";
  1037. port->class = DDB_PORT_TUNER;
  1038. port->type = DDB_TUNER_DVBS_ST_AA;
  1039. ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING);
  1040. } else if (port_has_drxks(port)) {
  1041. modname = "DUAL DVB-C/T";
  1042. port->class = DDB_PORT_TUNER;
  1043. port->type = DDB_TUNER_DVBCT_TR;
  1044. ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING);
  1045. }
  1046. printk(KERN_INFO "Port %d (TAB %d): %s\n",
  1047. port->nr, port->nr+1, modname);
  1048. }
  1049. static void ddb_input_init(struct ddb_port *port, int nr)
  1050. {
  1051. struct ddb *dev = port->dev;
  1052. struct ddb_input *input = &dev->input[nr];
  1053. input->nr = nr;
  1054. input->port = port;
  1055. input->dma_buf_num = INPUT_DMA_BUFS;
  1056. input->dma_buf_size = INPUT_DMA_SIZE;
  1057. ddbwritel(0, TS_INPUT_CONTROL(nr));
  1058. ddbwritel(2, TS_INPUT_CONTROL(nr));
  1059. ddbwritel(0, TS_INPUT_CONTROL(nr));
  1060. ddbwritel(0, DMA_BUFFER_ACK(nr));
  1061. tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input);
  1062. spin_lock_init(&input->lock);
  1063. init_waitqueue_head(&input->wq);
  1064. }
  1065. static void ddb_output_init(struct ddb_port *port, int nr)
  1066. {
  1067. struct ddb *dev = port->dev;
  1068. struct ddb_output *output = &dev->output[nr];
  1069. output->nr = nr;
  1070. output->port = port;
  1071. output->dma_buf_num = OUTPUT_DMA_BUFS;
  1072. output->dma_buf_size = OUTPUT_DMA_SIZE;
  1073. ddbwritel(0, TS_OUTPUT_CONTROL(nr));
  1074. ddbwritel(2, TS_OUTPUT_CONTROL(nr));
  1075. ddbwritel(0, TS_OUTPUT_CONTROL(nr));
  1076. tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output);
  1077. init_waitqueue_head(&output->wq);
  1078. }
  1079. static void ddb_ports_init(struct ddb *dev)
  1080. {
  1081. int i;
  1082. struct ddb_port *port;
  1083. for (i = 0; i < dev->info->port_num; i++) {
  1084. port = &dev->port[i];
  1085. port->dev = dev;
  1086. port->nr = i;
  1087. port->i2c = &dev->i2c[i];
  1088. port->input[0] = &dev->input[2 * i];
  1089. port->input[1] = &dev->input[2 * i + 1];
  1090. port->output = &dev->output[i];
  1091. mutex_init(&port->i2c_gate_lock);
  1092. ddb_port_probe(port);
  1093. ddb_input_init(port, 2 * i);
  1094. ddb_input_init(port, 2 * i + 1);
  1095. ddb_output_init(port, i);
  1096. }
  1097. }
  1098. static void ddb_ports_release(struct ddb *dev)
  1099. {
  1100. int i;
  1101. struct ddb_port *port;
  1102. for (i = 0; i < dev->info->port_num; i++) {
  1103. port = &dev->port[i];
  1104. port->dev = dev;
  1105. tasklet_kill(&port->input[0]->tasklet);
  1106. tasklet_kill(&port->input[1]->tasklet);
  1107. tasklet_kill(&port->output->tasklet);
  1108. }
  1109. }
  1110. /****************************************************************************/
  1111. /****************************************************************************/
  1112. /****************************************************************************/
  1113. static void irq_handle_i2c(struct ddb *dev, int n)
  1114. {
  1115. struct ddb_i2c *i2c = &dev->i2c[n];
  1116. i2c->done = 1;
  1117. wake_up(&i2c->wq);
  1118. }
  1119. static irqreturn_t irq_handler(int irq, void *dev_id)
  1120. {
  1121. struct ddb *dev = (struct ddb *) dev_id;
  1122. u32 s = ddbreadl(INTERRUPT_STATUS);
  1123. if (!s)
  1124. return IRQ_NONE;
  1125. do {
  1126. ddbwritel(s, INTERRUPT_ACK);
  1127. if (s & 0x00000001)
  1128. irq_handle_i2c(dev, 0);
  1129. if (s & 0x00000002)
  1130. irq_handle_i2c(dev, 1);
  1131. if (s & 0x00000004)
  1132. irq_handle_i2c(dev, 2);
  1133. if (s & 0x00000008)
  1134. irq_handle_i2c(dev, 3);
  1135. if (s & 0x00000100)
  1136. tasklet_schedule(&dev->input[0].tasklet);
  1137. if (s & 0x00000200)
  1138. tasklet_schedule(&dev->input[1].tasklet);
  1139. if (s & 0x00000400)
  1140. tasklet_schedule(&dev->input[2].tasklet);
  1141. if (s & 0x00000800)
  1142. tasklet_schedule(&dev->input[3].tasklet);
  1143. if (s & 0x00001000)
  1144. tasklet_schedule(&dev->input[4].tasklet);
  1145. if (s & 0x00002000)
  1146. tasklet_schedule(&dev->input[5].tasklet);
  1147. if (s & 0x00004000)
  1148. tasklet_schedule(&dev->input[6].tasklet);
  1149. if (s & 0x00008000)
  1150. tasklet_schedule(&dev->input[7].tasklet);
  1151. if (s & 0x00010000)
  1152. tasklet_schedule(&dev->output[0].tasklet);
  1153. if (s & 0x00020000)
  1154. tasklet_schedule(&dev->output[1].tasklet);
  1155. if (s & 0x00040000)
  1156. tasklet_schedule(&dev->output[2].tasklet);
  1157. if (s & 0x00080000)
  1158. tasklet_schedule(&dev->output[3].tasklet);
  1159. /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */
  1160. } while ((s = ddbreadl(INTERRUPT_STATUS)));
  1161. return IRQ_HANDLED;
  1162. }
  1163. /******************************************************************************/
  1164. /******************************************************************************/
  1165. /******************************************************************************/
  1166. static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen)
  1167. {
  1168. u32 data, shift;
  1169. if (wlen > 4)
  1170. ddbwritel(1, SPI_CONTROL);
  1171. while (wlen > 4) {
  1172. /* FIXME: check for big-endian */
  1173. data = swab32(*(u32 *)wbuf);
  1174. wbuf += 4;
  1175. wlen -= 4;
  1176. ddbwritel(data, SPI_DATA);
  1177. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1178. ;
  1179. }
  1180. if (rlen)
  1181. ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
  1182. else
  1183. ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL);
  1184. data = 0;
  1185. shift = ((4 - wlen) * 8);
  1186. while (wlen) {
  1187. data <<= 8;
  1188. data |= *wbuf;
  1189. wlen--;
  1190. wbuf++;
  1191. }
  1192. if (shift)
  1193. data <<= shift;
  1194. ddbwritel(data, SPI_DATA);
  1195. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1196. ;
  1197. if (!rlen) {
  1198. ddbwritel(0, SPI_CONTROL);
  1199. return 0;
  1200. }
  1201. if (rlen > 4)
  1202. ddbwritel(1, SPI_CONTROL);
  1203. while (rlen > 4) {
  1204. ddbwritel(0xffffffff, SPI_DATA);
  1205. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1206. ;
  1207. data = ddbreadl(SPI_DATA);
  1208. *(u32 *) rbuf = swab32(data);
  1209. rbuf += 4;
  1210. rlen -= 4;
  1211. }
  1212. ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL);
  1213. ddbwritel(0xffffffff, SPI_DATA);
  1214. while (ddbreadl(SPI_CONTROL) & 0x0004)
  1215. ;
  1216. data = ddbreadl(SPI_DATA);
  1217. ddbwritel(0, SPI_CONTROL);
  1218. if (rlen < 4)
  1219. data <<= ((4 - rlen) * 8);
  1220. while (rlen > 0) {
  1221. *rbuf = ((data >> 24) & 0xff);
  1222. data <<= 8;
  1223. rbuf++;
  1224. rlen--;
  1225. }
  1226. return 0;
  1227. }
  1228. #define DDB_MAGIC 'd'
  1229. struct ddb_flashio {
  1230. __user __u8 *write_buf;
  1231. __u32 write_len;
  1232. __user __u8 *read_buf;
  1233. __u32 read_len;
  1234. };
  1235. #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio)
  1236. #define DDB_NAME "ddbridge"
  1237. static u32 ddb_num;
  1238. static struct ddb *ddbs[32];
  1239. static struct class *ddb_class;
  1240. static int ddb_major;
  1241. static int ddb_open(struct inode *inode, struct file *file)
  1242. {
  1243. struct ddb *dev = ddbs[iminor(inode)];
  1244. file->private_data = dev;
  1245. return 0;
  1246. }
  1247. static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  1248. {
  1249. struct ddb *dev = file->private_data;
  1250. __user void *parg = (__user void *)arg;
  1251. int res;
  1252. switch (cmd) {
  1253. case IOCTL_DDB_FLASHIO:
  1254. {
  1255. struct ddb_flashio fio;
  1256. u8 *rbuf, *wbuf;
  1257. if (copy_from_user(&fio, parg, sizeof(fio)))
  1258. return -EFAULT;
  1259. if (fio.write_len > 1028 || fio.read_len > 1028)
  1260. return -EINVAL;
  1261. if (fio.write_len + fio.read_len > 1028)
  1262. return -EINVAL;
  1263. wbuf = &dev->iobuf[0];
  1264. rbuf = wbuf + fio.write_len;
  1265. if (copy_from_user(wbuf, fio.write_buf, fio.write_len))
  1266. return -EFAULT;
  1267. res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len);
  1268. if (res)
  1269. return res;
  1270. if (copy_to_user(fio.read_buf, rbuf, fio.read_len))
  1271. return -EFAULT;
  1272. break;
  1273. }
  1274. default:
  1275. return -ENOTTY;
  1276. }
  1277. return 0;
  1278. }
  1279. static const struct file_operations ddb_fops = {
  1280. .unlocked_ioctl = ddb_ioctl,
  1281. .open = ddb_open,
  1282. };
  1283. static char *ddb_devnode(struct device *device, umode_t *mode)
  1284. {
  1285. struct ddb *dev = dev_get_drvdata(device);
  1286. return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr);
  1287. }
  1288. static int ddb_class_create(void)
  1289. {
  1290. ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops);
  1291. if (ddb_major < 0)
  1292. return ddb_major;
  1293. ddb_class = class_create(THIS_MODULE, DDB_NAME);
  1294. if (IS_ERR(ddb_class)) {
  1295. unregister_chrdev(ddb_major, DDB_NAME);
  1296. return PTR_ERR(ddb_class);
  1297. }
  1298. ddb_class->devnode = ddb_devnode;
  1299. return 0;
  1300. }
  1301. static void ddb_class_destroy(void)
  1302. {
  1303. class_destroy(ddb_class);
  1304. unregister_chrdev(ddb_major, DDB_NAME);
  1305. }
  1306. static int ddb_device_create(struct ddb *dev)
  1307. {
  1308. dev->nr = ddb_num++;
  1309. dev->ddb_dev = device_create(ddb_class, NULL,
  1310. MKDEV(ddb_major, dev->nr),
  1311. dev, "ddbridge%d", dev->nr);
  1312. ddbs[dev->nr] = dev;
  1313. if (IS_ERR(dev->ddb_dev))
  1314. return -1;
  1315. return 0;
  1316. }
  1317. static void ddb_device_destroy(struct ddb *dev)
  1318. {
  1319. ddb_num--;
  1320. if (IS_ERR(dev->ddb_dev))
  1321. return;
  1322. device_destroy(ddb_class, MKDEV(ddb_major, 0));
  1323. }
  1324. /****************************************************************************/
  1325. /****************************************************************************/
  1326. /****************************************************************************/
  1327. static void ddb_unmap(struct ddb *dev)
  1328. {
  1329. if (dev->regs)
  1330. iounmap(dev->regs);
  1331. vfree(dev);
  1332. }
  1333. static void ddb_remove(struct pci_dev *pdev)
  1334. {
  1335. struct ddb *dev = pci_get_drvdata(pdev);
  1336. ddb_ports_detach(dev);
  1337. ddb_i2c_release(dev);
  1338. ddbwritel(0, INTERRUPT_ENABLE);
  1339. free_irq(dev->pdev->irq, dev);
  1340. #ifdef CONFIG_PCI_MSI
  1341. if (dev->msi)
  1342. pci_disable_msi(dev->pdev);
  1343. #endif
  1344. ddb_ports_release(dev);
  1345. ddb_buffers_free(dev);
  1346. ddb_device_destroy(dev);
  1347. ddb_unmap(dev);
  1348. pci_set_drvdata(pdev, NULL);
  1349. pci_disable_device(pdev);
  1350. }
  1351. static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1352. {
  1353. struct ddb *dev;
  1354. int stat = 0;
  1355. int irq_flag = IRQF_SHARED;
  1356. if (pci_enable_device(pdev) < 0)
  1357. return -ENODEV;
  1358. dev = vzalloc(sizeof(struct ddb));
  1359. if (dev == NULL)
  1360. return -ENOMEM;
  1361. dev->pdev = pdev;
  1362. pci_set_drvdata(pdev, dev);
  1363. dev->info = (struct ddb_info *) id->driver_data;
  1364. printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name);
  1365. dev->regs = ioremap(pci_resource_start(dev->pdev, 0),
  1366. pci_resource_len(dev->pdev, 0));
  1367. if (!dev->regs) {
  1368. stat = -ENOMEM;
  1369. goto fail;
  1370. }
  1371. printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4));
  1372. #ifdef CONFIG_PCI_MSI
  1373. if (pci_msi_enabled())
  1374. stat = pci_enable_msi(dev->pdev);
  1375. if (stat) {
  1376. printk(KERN_INFO ": MSI not available.\n");
  1377. } else {
  1378. irq_flag = 0;
  1379. dev->msi = 1;
  1380. }
  1381. #endif
  1382. stat = request_irq(dev->pdev->irq, irq_handler,
  1383. irq_flag, "DDBridge", (void *) dev);
  1384. if (stat < 0)
  1385. goto fail1;
  1386. ddbwritel(0, DMA_BASE_WRITE);
  1387. ddbwritel(0, DMA_BASE_READ);
  1388. ddbwritel(0xffffffff, INTERRUPT_ACK);
  1389. ddbwritel(0xfff0f, INTERRUPT_ENABLE);
  1390. ddbwritel(0, MSI1_ENABLE);
  1391. if (ddb_i2c_init(dev) < 0)
  1392. goto fail1;
  1393. ddb_ports_init(dev);
  1394. if (ddb_buffers_alloc(dev) < 0) {
  1395. printk(KERN_INFO ": Could not allocate buffer memory\n");
  1396. goto fail2;
  1397. }
  1398. if (ddb_ports_attach(dev) < 0)
  1399. goto fail3;
  1400. ddb_device_create(dev);
  1401. return 0;
  1402. fail3:
  1403. ddb_ports_detach(dev);
  1404. printk(KERN_ERR "fail3\n");
  1405. ddb_ports_release(dev);
  1406. fail2:
  1407. printk(KERN_ERR "fail2\n");
  1408. ddb_buffers_free(dev);
  1409. fail1:
  1410. printk(KERN_ERR "fail1\n");
  1411. if (dev->msi)
  1412. pci_disable_msi(dev->pdev);
  1413. if (stat == 0)
  1414. free_irq(dev->pdev->irq, dev);
  1415. fail:
  1416. printk(KERN_ERR "fail\n");
  1417. ddb_unmap(dev);
  1418. pci_set_drvdata(pdev, NULL);
  1419. pci_disable_device(pdev);
  1420. return -1;
  1421. }
  1422. /******************************************************************************/
  1423. /******************************************************************************/
  1424. /******************************************************************************/
  1425. static const struct ddb_info ddb_none = {
  1426. .type = DDB_NONE,
  1427. .name = "Digital Devices PCIe bridge",
  1428. };
  1429. static const struct ddb_info ddb_octopus = {
  1430. .type = DDB_OCTOPUS,
  1431. .name = "Digital Devices Octopus DVB adapter",
  1432. .port_num = 4,
  1433. };
  1434. static const struct ddb_info ddb_octopus_le = {
  1435. .type = DDB_OCTOPUS,
  1436. .name = "Digital Devices Octopus LE DVB adapter",
  1437. .port_num = 2,
  1438. };
  1439. static const struct ddb_info ddb_octopus_mini = {
  1440. .type = DDB_OCTOPUS,
  1441. .name = "Digital Devices Octopus Mini",
  1442. .port_num = 4,
  1443. };
  1444. static const struct ddb_info ddb_v6 = {
  1445. .type = DDB_OCTOPUS,
  1446. .name = "Digital Devices Cine S2 V6 DVB adapter",
  1447. .port_num = 3,
  1448. };
  1449. static const struct ddb_info ddb_v6_5 = {
  1450. .type = DDB_OCTOPUS,
  1451. .name = "Digital Devices Cine S2 V6.5 DVB adapter",
  1452. .port_num = 4,
  1453. };
  1454. static const struct ddb_info ddb_dvbct = {
  1455. .type = DDB_OCTOPUS,
  1456. .name = "Digital Devices DVBCT V6.1 DVB adapter",
  1457. .port_num = 3,
  1458. };
  1459. static const struct ddb_info ddb_satixS2v3 = {
  1460. .type = DDB_OCTOPUS,
  1461. .name = "Mystique SaTiX-S2 V3 DVB adapter",
  1462. .port_num = 3,
  1463. };
  1464. static const struct ddb_info ddb_octopusv3 = {
  1465. .type = DDB_OCTOPUS,
  1466. .name = "Digital Devices Octopus V3 DVB adapter",
  1467. .port_num = 4,
  1468. };
  1469. #define DDVID 0xdd01 /* Digital Devices Vendor ID */
  1470. #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \
  1471. .vendor = _vend, .device = _dev, \
  1472. .subvendor = _subvend, .subdevice = _subdev, \
  1473. .driver_data = (unsigned long)&_driverdata }
  1474. static const struct pci_device_id ddb_id_tbl[] = {
  1475. DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus),
  1476. DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus),
  1477. DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le),
  1478. DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini),
  1479. DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6),
  1480. DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5),
  1481. DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct),
  1482. DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3),
  1483. DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3),
  1484. /* in case sub-ids got deleted in flash */
  1485. DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none),
  1486. {0}
  1487. };
  1488. MODULE_DEVICE_TABLE(pci, ddb_id_tbl);
  1489. static struct pci_driver ddb_pci_driver = {
  1490. .name = "DDBridge",
  1491. .id_table = ddb_id_tbl,
  1492. .probe = ddb_probe,
  1493. .remove = ddb_remove,
  1494. };
  1495. static __init int module_init_ddbridge(void)
  1496. {
  1497. int ret;
  1498. printk(KERN_INFO "Digital Devices PCIE bridge driver, "
  1499. "Copyright (C) 2010-11 Digital Devices GmbH\n");
  1500. ret = ddb_class_create();
  1501. if (ret < 0)
  1502. return ret;
  1503. ret = pci_register_driver(&ddb_pci_driver);
  1504. if (ret < 0)
  1505. ddb_class_destroy();
  1506. return ret;
  1507. }
  1508. static __exit void module_exit_ddbridge(void)
  1509. {
  1510. pci_unregister_driver(&ddb_pci_driver);
  1511. ddb_class_destroy();
  1512. }
  1513. module_init(module_init_ddbridge);
  1514. module_exit(module_exit_ddbridge);
  1515. MODULE_DESCRIPTION("Digital Devices PCIe Bridge");
  1516. MODULE_AUTHOR("Ralph Metzler");
  1517. MODULE_LICENSE("GPL");
  1518. MODULE_VERSION("0.5");