os_4bri.c 28 KB

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  1. /* $Id: os_4bri.c,v 1.28.4.4 2005/02/11 19:40:25 armin Exp $ */
  2. #include "platform.h"
  3. #include "debuglib.h"
  4. #include "cardtype.h"
  5. #include "pc.h"
  6. #include "pr_pc.h"
  7. #include "di_defs.h"
  8. #include "dsp_defs.h"
  9. #include "di.h"
  10. #include "io.h"
  11. #include "xdi_msg.h"
  12. #include "xdi_adapter.h"
  13. #include "os_4bri.h"
  14. #include "diva_pci.h"
  15. #include "mi_pc.h"
  16. #include "dsrv4bri.h"
  17. #include "helpers.h"
  18. static void *diva_xdiLoadFileFile = NULL;
  19. static dword diva_xdiLoadFileLength = 0;
  20. /*
  21. ** IMPORTS
  22. */
  23. extern void prepare_qBri_functions(PISDN_ADAPTER IoAdapter);
  24. extern void prepare_qBri2_functions(PISDN_ADAPTER IoAdapter);
  25. extern void diva_xdi_display_adapter_features(int card);
  26. extern void diva_add_slave_adapter(diva_os_xdi_adapter_t *a);
  27. extern int qBri_FPGA_download(PISDN_ADAPTER IoAdapter);
  28. extern void start_qBri_hardware(PISDN_ADAPTER IoAdapter);
  29. extern int diva_card_read_xlog(diva_os_xdi_adapter_t *a);
  30. /*
  31. ** LOCALS
  32. */
  33. static unsigned long _4bri_bar_length[4] = {
  34. 0x100,
  35. 0x100, /* I/O */
  36. MQ_MEMORY_SIZE,
  37. 0x2000
  38. };
  39. static unsigned long _4bri_v2_bar_length[4] = {
  40. 0x100,
  41. 0x100, /* I/O */
  42. MQ2_MEMORY_SIZE,
  43. 0x10000
  44. };
  45. static unsigned long _4bri_v2_bri_bar_length[4] = {
  46. 0x100,
  47. 0x100, /* I/O */
  48. BRI2_MEMORY_SIZE,
  49. 0x10000
  50. };
  51. static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t *a);
  52. static int _4bri_get_serial_number(diva_os_xdi_adapter_t *a);
  53. static int diva_4bri_cmd_card_proc(struct _diva_os_xdi_adapter *a,
  54. diva_xdi_um_cfg_cmd_t *cmd,
  55. int length);
  56. static int diva_4bri_cleanup_slave_adapters(diva_os_xdi_adapter_t *a);
  57. static int diva_4bri_write_fpga_image(diva_os_xdi_adapter_t *a,
  58. byte *data, dword length);
  59. static int diva_4bri_reset_adapter(PISDN_ADAPTER IoAdapter);
  60. static int diva_4bri_write_sdram_block(PISDN_ADAPTER IoAdapter,
  61. dword address,
  62. const byte *data,
  63. dword length, dword limit);
  64. static int diva_4bri_start_adapter(PISDN_ADAPTER IoAdapter,
  65. dword start_address, dword features);
  66. static int check_qBri_interrupt(PISDN_ADAPTER IoAdapter);
  67. static int diva_4bri_stop_adapter(diva_os_xdi_adapter_t *a);
  68. static int _4bri_is_rev_2_card(int card_ordinal)
  69. {
  70. switch (card_ordinal) {
  71. case CARDTYPE_DIVASRV_Q_8M_V2_PCI:
  72. case CARDTYPE_DIVASRV_VOICE_Q_8M_V2_PCI:
  73. case CARDTYPE_DIVASRV_B_2M_V2_PCI:
  74. case CARDTYPE_DIVASRV_B_2F_PCI:
  75. case CARDTYPE_DIVASRV_VOICE_B_2M_V2_PCI:
  76. return (1);
  77. }
  78. return (0);
  79. }
  80. static int _4bri_is_rev_2_bri_card(int card_ordinal)
  81. {
  82. switch (card_ordinal) {
  83. case CARDTYPE_DIVASRV_B_2M_V2_PCI:
  84. case CARDTYPE_DIVASRV_B_2F_PCI:
  85. case CARDTYPE_DIVASRV_VOICE_B_2M_V2_PCI:
  86. return (1);
  87. }
  88. return (0);
  89. }
  90. static void diva_4bri_set_addresses(diva_os_xdi_adapter_t *a)
  91. {
  92. dword offset = a->resources.pci.qoffset;
  93. dword c_offset = offset * a->xdi_adapter.ControllerNumber;
  94. a->resources.pci.mem_type_id[MEM_TYPE_RAM] = 2;
  95. a->resources.pci.mem_type_id[MEM_TYPE_ADDRESS] = 2;
  96. a->resources.pci.mem_type_id[MEM_TYPE_CONTROL] = 2;
  97. a->resources.pci.mem_type_id[MEM_TYPE_RESET] = 0;
  98. a->resources.pci.mem_type_id[MEM_TYPE_CTLREG] = 3;
  99. a->resources.pci.mem_type_id[MEM_TYPE_PROM] = 0;
  100. /*
  101. Set up hardware related pointers
  102. */
  103. a->xdi_adapter.Address = a->resources.pci.addr[2]; /* BAR2 SDRAM */
  104. a->xdi_adapter.Address += c_offset;
  105. a->xdi_adapter.Control = a->resources.pci.addr[2]; /* BAR2 SDRAM */
  106. a->xdi_adapter.ram = a->resources.pci.addr[2]; /* BAR2 SDRAM */
  107. a->xdi_adapter.ram += c_offset + (offset - MQ_SHARED_RAM_SIZE);
  108. a->xdi_adapter.reset = a->resources.pci.addr[0]; /* BAR0 CONFIG */
  109. /*
  110. ctlReg contains the register address for the MIPS CPU reset control
  111. */
  112. a->xdi_adapter.ctlReg = a->resources.pci.addr[3]; /* BAR3 CNTRL */
  113. /*
  114. prom contains the register address for FPGA and EEPROM programming
  115. */
  116. a->xdi_adapter.prom = &a->xdi_adapter.reset[0x6E];
  117. }
  118. /*
  119. ** BAR0 - MEM - 0x100 - CONFIG MEM
  120. ** BAR1 - I/O - 0x100 - UNUSED
  121. ** BAR2 - MEM - MQ_MEMORY_SIZE (MQ2_MEMORY_SIZE on Rev.2) - SDRAM
  122. ** BAR3 - MEM - 0x2000 (0x10000 on Rev.2) - CNTRL
  123. **
  124. ** Called by master adapter, that will initialize and add slave adapters
  125. */
  126. int diva_4bri_init_card(diva_os_xdi_adapter_t *a)
  127. {
  128. int bar, i;
  129. byte __iomem *p;
  130. PADAPTER_LIST_ENTRY quadro_list;
  131. diva_os_xdi_adapter_t *diva_current;
  132. diva_os_xdi_adapter_t *adapter_list[4];
  133. PISDN_ADAPTER Slave;
  134. unsigned long bar_length[ARRAY_SIZE(_4bri_bar_length)];
  135. int v2 = _4bri_is_rev_2_card(a->CardOrdinal);
  136. int tasks = _4bri_is_rev_2_bri_card(a->CardOrdinal) ? 1 : MQ_INSTANCE_COUNT;
  137. int factor = (tasks == 1) ? 1 : 2;
  138. if (v2) {
  139. if (_4bri_is_rev_2_bri_card(a->CardOrdinal)) {
  140. memcpy(bar_length, _4bri_v2_bri_bar_length,
  141. sizeof(bar_length));
  142. } else {
  143. memcpy(bar_length, _4bri_v2_bar_length,
  144. sizeof(bar_length));
  145. }
  146. } else {
  147. memcpy(bar_length, _4bri_bar_length, sizeof(bar_length));
  148. }
  149. DBG_TRC(("SDRAM_LENGTH=%08x, tasks=%d, factor=%d",
  150. bar_length[2], tasks, factor))
  151. /*
  152. Get Serial Number
  153. The serial number of 4BRI is accessible in accordance with PCI spec
  154. via command register located in configuration space, also we do not
  155. have to map any BAR before we can access it
  156. */
  157. if (!_4bri_get_serial_number(a)) {
  158. DBG_ERR(("A: 4BRI can't get Serial Number"))
  159. diva_4bri_cleanup_adapter(a);
  160. return (-1);
  161. }
  162. /*
  163. Set properties
  164. */
  165. a->xdi_adapter.Properties = CardProperties[a->CardOrdinal];
  166. DBG_LOG(("Load %s, SN:%ld, bus:%02x, func:%02x",
  167. a->xdi_adapter.Properties.Name,
  168. a->xdi_adapter.serialNo,
  169. a->resources.pci.bus, a->resources.pci.func))
  170. /*
  171. First initialization step: get and check hardware resoures.
  172. Do not map resources and do not access card at this step
  173. */
  174. for (bar = 0; bar < 4; bar++) {
  175. a->resources.pci.bar[bar] =
  176. divasa_get_pci_bar(a->resources.pci.bus,
  177. a->resources.pci.func, bar,
  178. a->resources.pci.hdev);
  179. if (!a->resources.pci.bar[bar]
  180. || (a->resources.pci.bar[bar] == 0xFFFFFFF0)) {
  181. DBG_ERR(
  182. ("A: invalid bar[%d]=%08x", bar,
  183. a->resources.pci.bar[bar]))
  184. return (-1);
  185. }
  186. }
  187. a->resources.pci.irq =
  188. (byte) divasa_get_pci_irq(a->resources.pci.bus,
  189. a->resources.pci.func,
  190. a->resources.pci.hdev);
  191. if (!a->resources.pci.irq) {
  192. DBG_ERR(("A: invalid irq"));
  193. return (-1);
  194. }
  195. a->xdi_adapter.sdram_bar = a->resources.pci.bar[2];
  196. /*
  197. Map all MEMORY BAR's
  198. */
  199. for (bar = 0; bar < 4; bar++) {
  200. if (bar != 1) { /* ignore I/O */
  201. a->resources.pci.addr[bar] =
  202. divasa_remap_pci_bar(a, bar, a->resources.pci.bar[bar],
  203. bar_length[bar]);
  204. if (!a->resources.pci.addr[bar]) {
  205. DBG_ERR(("A: 4BRI: can't map bar[%d]", bar))
  206. diva_4bri_cleanup_adapter(a);
  207. return (-1);
  208. }
  209. }
  210. }
  211. /*
  212. Register I/O port
  213. */
  214. sprintf(&a->port_name[0], "DIVA 4BRI %ld", (long) a->xdi_adapter.serialNo);
  215. if (diva_os_register_io_port(a, 1, a->resources.pci.bar[1],
  216. bar_length[1], &a->port_name[0], 1)) {
  217. DBG_ERR(("A: 4BRI: can't register bar[1]"))
  218. diva_4bri_cleanup_adapter(a);
  219. return (-1);
  220. }
  221. a->resources.pci.addr[1] =
  222. (void *) (unsigned long) a->resources.pci.bar[1];
  223. /*
  224. Set cleanup pointer for base adapter only, so slave adapter
  225. will be unable to get cleanup
  226. */
  227. a->interface.cleanup_adapter_proc = diva_4bri_cleanup_adapter;
  228. /*
  229. Create slave adapters
  230. */
  231. if (tasks > 1) {
  232. if (!(a->slave_adapters[0] =
  233. (diva_os_xdi_adapter_t *) diva_os_malloc(0, sizeof(*a))))
  234. {
  235. diva_4bri_cleanup_adapter(a);
  236. return (-1);
  237. }
  238. if (!(a->slave_adapters[1] =
  239. (diva_os_xdi_adapter_t *) diva_os_malloc(0, sizeof(*a))))
  240. {
  241. diva_os_free(0, a->slave_adapters[0]);
  242. a->slave_adapters[0] = NULL;
  243. diva_4bri_cleanup_adapter(a);
  244. return (-1);
  245. }
  246. if (!(a->slave_adapters[2] =
  247. (diva_os_xdi_adapter_t *) diva_os_malloc(0, sizeof(*a))))
  248. {
  249. diva_os_free(0, a->slave_adapters[0]);
  250. diva_os_free(0, a->slave_adapters[1]);
  251. a->slave_adapters[0] = NULL;
  252. a->slave_adapters[1] = NULL;
  253. diva_4bri_cleanup_adapter(a);
  254. return (-1);
  255. }
  256. memset(a->slave_adapters[0], 0x00, sizeof(*a));
  257. memset(a->slave_adapters[1], 0x00, sizeof(*a));
  258. memset(a->slave_adapters[2], 0x00, sizeof(*a));
  259. }
  260. adapter_list[0] = a;
  261. adapter_list[1] = a->slave_adapters[0];
  262. adapter_list[2] = a->slave_adapters[1];
  263. adapter_list[3] = a->slave_adapters[2];
  264. /*
  265. Allocate slave list
  266. */
  267. quadro_list =
  268. (PADAPTER_LIST_ENTRY) diva_os_malloc(0, sizeof(*quadro_list));
  269. if (!(a->slave_list = quadro_list)) {
  270. for (i = 0; i < (tasks - 1); i++) {
  271. diva_os_free(0, a->slave_adapters[i]);
  272. a->slave_adapters[i] = NULL;
  273. }
  274. diva_4bri_cleanup_adapter(a);
  275. return (-1);
  276. }
  277. memset(quadro_list, 0x00, sizeof(*quadro_list));
  278. /*
  279. Set interfaces
  280. */
  281. a->xdi_adapter.QuadroList = quadro_list;
  282. for (i = 0; i < tasks; i++) {
  283. adapter_list[i]->xdi_adapter.ControllerNumber = i;
  284. adapter_list[i]->xdi_adapter.tasks = tasks;
  285. quadro_list->QuadroAdapter[i] =
  286. &adapter_list[i]->xdi_adapter;
  287. }
  288. for (i = 0; i < tasks; i++) {
  289. diva_current = adapter_list[i];
  290. diva_current->dsp_mask = 0x00000003;
  291. diva_current->xdi_adapter.a.io =
  292. &diva_current->xdi_adapter;
  293. diva_current->xdi_adapter.DIRequest = request;
  294. diva_current->interface.cmd_proc = diva_4bri_cmd_card_proc;
  295. diva_current->xdi_adapter.Properties =
  296. CardProperties[a->CardOrdinal];
  297. diva_current->CardOrdinal = a->CardOrdinal;
  298. diva_current->xdi_adapter.Channels =
  299. CardProperties[a->CardOrdinal].Channels;
  300. diva_current->xdi_adapter.e_max =
  301. CardProperties[a->CardOrdinal].E_info;
  302. diva_current->xdi_adapter.e_tbl =
  303. diva_os_malloc(0,
  304. diva_current->xdi_adapter.e_max *
  305. sizeof(E_INFO));
  306. if (!diva_current->xdi_adapter.e_tbl) {
  307. diva_4bri_cleanup_slave_adapters(a);
  308. diva_4bri_cleanup_adapter(a);
  309. for (i = 1; i < (tasks - 1); i++) {
  310. diva_os_free(0, adapter_list[i]);
  311. }
  312. return (-1);
  313. }
  314. memset(diva_current->xdi_adapter.e_tbl, 0x00,
  315. diva_current->xdi_adapter.e_max * sizeof(E_INFO));
  316. if (diva_os_initialize_spin_lock(&diva_current->xdi_adapter.isr_spin_lock, "isr")) {
  317. diva_4bri_cleanup_slave_adapters(a);
  318. diva_4bri_cleanup_adapter(a);
  319. for (i = 1; i < (tasks - 1); i++) {
  320. diva_os_free(0, adapter_list[i]);
  321. }
  322. return (-1);
  323. }
  324. if (diva_os_initialize_spin_lock(&diva_current->xdi_adapter.data_spin_lock, "data")) {
  325. diva_4bri_cleanup_slave_adapters(a);
  326. diva_4bri_cleanup_adapter(a);
  327. for (i = 1; i < (tasks - 1); i++) {
  328. diva_os_free(0, adapter_list[i]);
  329. }
  330. return (-1);
  331. }
  332. strcpy(diva_current->xdi_adapter.req_soft_isr. dpc_thread_name, "kdivas4brid");
  333. if (diva_os_initialize_soft_isr(&diva_current->xdi_adapter.req_soft_isr, DIDpcRoutine,
  334. &diva_current->xdi_adapter)) {
  335. diva_4bri_cleanup_slave_adapters(a);
  336. diva_4bri_cleanup_adapter(a);
  337. for (i = 1; i < (tasks - 1); i++) {
  338. diva_os_free(0, adapter_list[i]);
  339. }
  340. return (-1);
  341. }
  342. /*
  343. Do not initialize second DPC - only one thread will be created
  344. */
  345. diva_current->xdi_adapter.isr_soft_isr.object =
  346. diva_current->xdi_adapter.req_soft_isr.object;
  347. }
  348. if (v2) {
  349. prepare_qBri2_functions(&a->xdi_adapter);
  350. } else {
  351. prepare_qBri_functions(&a->xdi_adapter);
  352. }
  353. for (i = 0; i < tasks; i++) {
  354. diva_current = adapter_list[i];
  355. if (i)
  356. memcpy(&diva_current->resources, &a->resources, sizeof(divas_card_resources_t));
  357. diva_current->resources.pci.qoffset = (a->xdi_adapter.MemorySize >> factor);
  358. }
  359. /*
  360. Set up hardware related pointers
  361. */
  362. a->xdi_adapter.cfg = (void *) (unsigned long) a->resources.pci.bar[0]; /* BAR0 CONFIG */
  363. a->xdi_adapter.port = (void *) (unsigned long) a->resources.pci.bar[1]; /* BAR1 */
  364. a->xdi_adapter.ctlReg = (void *) (unsigned long) a->resources.pci.bar[3]; /* BAR3 CNTRL */
  365. for (i = 0; i < tasks; i++) {
  366. diva_current = adapter_list[i];
  367. diva_4bri_set_addresses(diva_current);
  368. Slave = a->xdi_adapter.QuadroList->QuadroAdapter[i];
  369. Slave->MultiMaster = &a->xdi_adapter;
  370. Slave->sdram_bar = a->xdi_adapter.sdram_bar;
  371. if (i) {
  372. Slave->serialNo = ((dword) (Slave->ControllerNumber << 24)) |
  373. a->xdi_adapter.serialNo;
  374. Slave->cardType = a->xdi_adapter.cardType;
  375. }
  376. }
  377. /*
  378. reset contains the base address for the PLX 9054 register set
  379. */
  380. p = DIVA_OS_MEM_ATTACH_RESET(&a->xdi_adapter);
  381. WRITE_BYTE(&p[PLX9054_INTCSR], 0x00); /* disable PCI interrupts */
  382. DIVA_OS_MEM_DETACH_RESET(&a->xdi_adapter, p);
  383. /*
  384. Set IRQ handler
  385. */
  386. a->xdi_adapter.irq_info.irq_nr = a->resources.pci.irq;
  387. sprintf(a->xdi_adapter.irq_info.irq_name, "DIVA 4BRI %ld",
  388. (long) a->xdi_adapter.serialNo);
  389. if (diva_os_register_irq(a, a->xdi_adapter.irq_info.irq_nr,
  390. a->xdi_adapter.irq_info.irq_name)) {
  391. diva_4bri_cleanup_slave_adapters(a);
  392. diva_4bri_cleanup_adapter(a);
  393. for (i = 1; i < (tasks - 1); i++) {
  394. diva_os_free(0, adapter_list[i]);
  395. }
  396. return (-1);
  397. }
  398. a->xdi_adapter.irq_info.registered = 1;
  399. /*
  400. Add three slave adapters
  401. */
  402. if (tasks > 1) {
  403. diva_add_slave_adapter(adapter_list[1]);
  404. diva_add_slave_adapter(adapter_list[2]);
  405. diva_add_slave_adapter(adapter_list[3]);
  406. }
  407. diva_log_info("%s IRQ:%d SerNo:%d", a->xdi_adapter.Properties.Name,
  408. a->resources.pci.irq, a->xdi_adapter.serialNo);
  409. return (0);
  410. }
  411. /*
  412. ** Cleanup function will be called for master adapter only
  413. ** this is guaranteed by design: cleanup callback is set
  414. ** by master adapter only
  415. */
  416. static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t *a)
  417. {
  418. int bar;
  419. /*
  420. Stop adapter if running
  421. */
  422. if (a->xdi_adapter.Initialized) {
  423. diva_4bri_stop_adapter(a);
  424. }
  425. /*
  426. Remove IRQ handler
  427. */
  428. if (a->xdi_adapter.irq_info.registered) {
  429. diva_os_remove_irq(a, a->xdi_adapter.irq_info.irq_nr);
  430. }
  431. a->xdi_adapter.irq_info.registered = 0;
  432. /*
  433. Free DPC's and spin locks on all adapters
  434. */
  435. diva_4bri_cleanup_slave_adapters(a);
  436. /*
  437. Unmap all BARS
  438. */
  439. for (bar = 0; bar < 4; bar++) {
  440. if (bar != 1) {
  441. if (a->resources.pci.bar[bar]
  442. && a->resources.pci.addr[bar]) {
  443. divasa_unmap_pci_bar(a->resources.pci.addr[bar]);
  444. a->resources.pci.bar[bar] = 0;
  445. a->resources.pci.addr[bar] = NULL;
  446. }
  447. }
  448. }
  449. /*
  450. Unregister I/O
  451. */
  452. if (a->resources.pci.bar[1] && a->resources.pci.addr[1]) {
  453. diva_os_register_io_port(a, 0, a->resources.pci.bar[1],
  454. _4bri_is_rev_2_card(a->
  455. CardOrdinal) ?
  456. _4bri_v2_bar_length[1] :
  457. _4bri_bar_length[1],
  458. &a->port_name[0], 1);
  459. a->resources.pci.bar[1] = 0;
  460. a->resources.pci.addr[1] = NULL;
  461. }
  462. if (a->slave_list) {
  463. diva_os_free(0, a->slave_list);
  464. a->slave_list = NULL;
  465. }
  466. return (0);
  467. }
  468. static int _4bri_get_serial_number(diva_os_xdi_adapter_t *a)
  469. {
  470. dword data[64];
  471. dword serNo;
  472. word addr, status, i, j;
  473. byte Bus, Slot;
  474. void *hdev;
  475. Bus = a->resources.pci.bus;
  476. Slot = a->resources.pci.func;
  477. hdev = a->resources.pci.hdev;
  478. for (i = 0; i < 64; ++i) {
  479. addr = i * 4;
  480. for (j = 0; j < 5; ++j) {
  481. PCIwrite(Bus, Slot, 0x4E, &addr, sizeof(addr),
  482. hdev);
  483. diva_os_wait(1);
  484. PCIread(Bus, Slot, 0x4E, &status, sizeof(status),
  485. hdev);
  486. if (status & 0x8000)
  487. break;
  488. }
  489. if (j >= 5) {
  490. DBG_ERR(("EEPROM[%d] read failed (0x%x)", i * 4, addr))
  491. return (0);
  492. }
  493. PCIread(Bus, Slot, 0x50, &data[i], sizeof(data[i]), hdev);
  494. }
  495. DBG_BLK(((char *) &data[0], sizeof(data)))
  496. serNo = data[32];
  497. if (serNo == 0 || serNo == 0xffffffff)
  498. serNo = data[63];
  499. if (!serNo) {
  500. DBG_LOG(("W: Serial Number == 0, create one serial number"));
  501. serNo = a->resources.pci.bar[1] & 0xffff0000;
  502. serNo |= a->resources.pci.bus << 8;
  503. serNo |= a->resources.pci.func;
  504. }
  505. a->xdi_adapter.serialNo = serNo;
  506. DBG_REG(("Serial No. : %ld", a->xdi_adapter.serialNo))
  507. return (serNo);
  508. }
  509. /*
  510. ** Release resources of slave adapters
  511. */
  512. static int diva_4bri_cleanup_slave_adapters(diva_os_xdi_adapter_t *a)
  513. {
  514. diva_os_xdi_adapter_t *adapter_list[4];
  515. diva_os_xdi_adapter_t *diva_current;
  516. int i;
  517. adapter_list[0] = a;
  518. adapter_list[1] = a->slave_adapters[0];
  519. adapter_list[2] = a->slave_adapters[1];
  520. adapter_list[3] = a->slave_adapters[2];
  521. for (i = 0; i < a->xdi_adapter.tasks; i++) {
  522. diva_current = adapter_list[i];
  523. if (diva_current) {
  524. diva_os_destroy_spin_lock(&diva_current->
  525. xdi_adapter.
  526. isr_spin_lock, "unload");
  527. diva_os_destroy_spin_lock(&diva_current->
  528. xdi_adapter.
  529. data_spin_lock,
  530. "unload");
  531. diva_os_cancel_soft_isr(&diva_current->xdi_adapter.
  532. req_soft_isr);
  533. diva_os_cancel_soft_isr(&diva_current->xdi_adapter.
  534. isr_soft_isr);
  535. diva_os_remove_soft_isr(&diva_current->xdi_adapter.
  536. req_soft_isr);
  537. diva_current->xdi_adapter.isr_soft_isr.object = NULL;
  538. if (diva_current->xdi_adapter.e_tbl) {
  539. diva_os_free(0,
  540. diva_current->xdi_adapter.
  541. e_tbl);
  542. }
  543. diva_current->xdi_adapter.e_tbl = NULL;
  544. diva_current->xdi_adapter.e_max = 0;
  545. diva_current->xdi_adapter.e_count = 0;
  546. }
  547. }
  548. return (0);
  549. }
  550. static int
  551. diva_4bri_cmd_card_proc(struct _diva_os_xdi_adapter *a,
  552. diva_xdi_um_cfg_cmd_t *cmd, int length)
  553. {
  554. int ret = -1;
  555. if (cmd->adapter != a->controller) {
  556. DBG_ERR(("A: 4bri_cmd, invalid controller=%d != %d",
  557. cmd->adapter, a->controller))
  558. return (-1);
  559. }
  560. switch (cmd->command) {
  561. case DIVA_XDI_UM_CMD_GET_CARD_ORDINAL:
  562. a->xdi_mbox.data_length = sizeof(dword);
  563. a->xdi_mbox.data =
  564. diva_os_malloc(0, a->xdi_mbox.data_length);
  565. if (a->xdi_mbox.data) {
  566. *(dword *) a->xdi_mbox.data =
  567. (dword) a->CardOrdinal;
  568. a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
  569. ret = 0;
  570. }
  571. break;
  572. case DIVA_XDI_UM_CMD_GET_SERIAL_NR:
  573. a->xdi_mbox.data_length = sizeof(dword);
  574. a->xdi_mbox.data =
  575. diva_os_malloc(0, a->xdi_mbox.data_length);
  576. if (a->xdi_mbox.data) {
  577. *(dword *) a->xdi_mbox.data =
  578. (dword) a->xdi_adapter.serialNo;
  579. a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
  580. ret = 0;
  581. }
  582. break;
  583. case DIVA_XDI_UM_CMD_GET_PCI_HW_CONFIG:
  584. if (!a->xdi_adapter.ControllerNumber) {
  585. /*
  586. Only master adapter can access hardware config
  587. */
  588. a->xdi_mbox.data_length = sizeof(dword) * 9;
  589. a->xdi_mbox.data =
  590. diva_os_malloc(0, a->xdi_mbox.data_length);
  591. if (a->xdi_mbox.data) {
  592. int i;
  593. dword *data = (dword *) a->xdi_mbox.data;
  594. for (i = 0; i < 8; i++) {
  595. *data++ = a->resources.pci.bar[i];
  596. }
  597. *data++ = (dword) a->resources.pci.irq;
  598. a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
  599. ret = 0;
  600. }
  601. }
  602. break;
  603. case DIVA_XDI_UM_CMD_GET_CARD_STATE:
  604. if (!a->xdi_adapter.ControllerNumber) {
  605. a->xdi_mbox.data_length = sizeof(dword);
  606. a->xdi_mbox.data =
  607. diva_os_malloc(0, a->xdi_mbox.data_length);
  608. if (a->xdi_mbox.data) {
  609. dword *data = (dword *) a->xdi_mbox.data;
  610. if (!a->xdi_adapter.ram
  611. || !a->xdi_adapter.reset
  612. || !a->xdi_adapter.cfg) {
  613. *data = 3;
  614. } else if (a->xdi_adapter.trapped) {
  615. *data = 2;
  616. } else if (a->xdi_adapter.Initialized) {
  617. *data = 1;
  618. } else {
  619. *data = 0;
  620. }
  621. a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
  622. ret = 0;
  623. }
  624. }
  625. break;
  626. case DIVA_XDI_UM_CMD_WRITE_FPGA:
  627. if (!a->xdi_adapter.ControllerNumber) {
  628. ret =
  629. diva_4bri_write_fpga_image(a,
  630. (byte *)&cmd[1],
  631. cmd->command_data.
  632. write_fpga.
  633. image_length);
  634. }
  635. break;
  636. case DIVA_XDI_UM_CMD_RESET_ADAPTER:
  637. if (!a->xdi_adapter.ControllerNumber) {
  638. ret = diva_4bri_reset_adapter(&a->xdi_adapter);
  639. }
  640. break;
  641. case DIVA_XDI_UM_CMD_WRITE_SDRAM_BLOCK:
  642. if (!a->xdi_adapter.ControllerNumber) {
  643. ret = diva_4bri_write_sdram_block(&a->xdi_adapter,
  644. cmd->
  645. command_data.
  646. write_sdram.
  647. offset,
  648. (byte *) &
  649. cmd[1],
  650. cmd->
  651. command_data.
  652. write_sdram.
  653. length,
  654. a->xdi_adapter.
  655. MemorySize);
  656. }
  657. break;
  658. case DIVA_XDI_UM_CMD_START_ADAPTER:
  659. if (!a->xdi_adapter.ControllerNumber) {
  660. ret = diva_4bri_start_adapter(&a->xdi_adapter,
  661. cmd->command_data.
  662. start.offset,
  663. cmd->command_data.
  664. start.features);
  665. }
  666. break;
  667. case DIVA_XDI_UM_CMD_SET_PROTOCOL_FEATURES:
  668. if (!a->xdi_adapter.ControllerNumber) {
  669. a->xdi_adapter.features =
  670. cmd->command_data.features.features;
  671. a->xdi_adapter.a.protocol_capabilities =
  672. a->xdi_adapter.features;
  673. DBG_TRC(("Set raw protocol features (%08x)",
  674. a->xdi_adapter.features))
  675. ret = 0;
  676. }
  677. break;
  678. case DIVA_XDI_UM_CMD_STOP_ADAPTER:
  679. if (!a->xdi_adapter.ControllerNumber) {
  680. ret = diva_4bri_stop_adapter(a);
  681. }
  682. break;
  683. case DIVA_XDI_UM_CMD_READ_XLOG_ENTRY:
  684. ret = diva_card_read_xlog(a);
  685. break;
  686. case DIVA_XDI_UM_CMD_READ_SDRAM:
  687. if (!a->xdi_adapter.ControllerNumber
  688. && a->xdi_adapter.Address) {
  689. if (
  690. (a->xdi_mbox.data_length =
  691. cmd->command_data.read_sdram.length)) {
  692. if (
  693. (a->xdi_mbox.data_length +
  694. cmd->command_data.read_sdram.offset) <
  695. a->xdi_adapter.MemorySize) {
  696. a->xdi_mbox.data =
  697. diva_os_malloc(0,
  698. a->xdi_mbox.
  699. data_length);
  700. if (a->xdi_mbox.data) {
  701. byte __iomem *p = DIVA_OS_MEM_ATTACH_ADDRESS(&a->xdi_adapter);
  702. byte __iomem *src = p;
  703. byte *dst = a->xdi_mbox.data;
  704. dword len = a->xdi_mbox.data_length;
  705. src += cmd->command_data.read_sdram.offset;
  706. while (len--) {
  707. *dst++ = READ_BYTE(src++);
  708. }
  709. DIVA_OS_MEM_DETACH_ADDRESS(&a->xdi_adapter, p);
  710. a->xdi_mbox.status = DIVA_XDI_MBOX_BUSY;
  711. ret = 0;
  712. }
  713. }
  714. }
  715. }
  716. break;
  717. default:
  718. DBG_ERR(("A: A(%d) invalid cmd=%d", a->controller,
  719. cmd->command))
  720. }
  721. return (ret);
  722. }
  723. void *xdiLoadFile(char *FileName, dword *FileLength,
  724. unsigned long lim)
  725. {
  726. void *ret = diva_xdiLoadFileFile;
  727. if (FileLength) {
  728. *FileLength = diva_xdiLoadFileLength;
  729. }
  730. diva_xdiLoadFileFile = NULL;
  731. diva_xdiLoadFileLength = 0;
  732. return (ret);
  733. }
  734. void diva_os_set_qBri_functions(PISDN_ADAPTER IoAdapter)
  735. {
  736. }
  737. void diva_os_set_qBri2_functions(PISDN_ADAPTER IoAdapter)
  738. {
  739. }
  740. static int
  741. diva_4bri_write_fpga_image(diva_os_xdi_adapter_t *a, byte *data,
  742. dword length)
  743. {
  744. int ret;
  745. diva_xdiLoadFileFile = data;
  746. diva_xdiLoadFileLength = length;
  747. ret = qBri_FPGA_download(&a->xdi_adapter);
  748. diva_xdiLoadFileFile = NULL;
  749. diva_xdiLoadFileLength = 0;
  750. return (ret ? 0 : -1);
  751. }
  752. static int diva_4bri_reset_adapter(PISDN_ADAPTER IoAdapter)
  753. {
  754. PISDN_ADAPTER Slave;
  755. int i;
  756. if (!IoAdapter->Address || !IoAdapter->reset) {
  757. return (-1);
  758. }
  759. if (IoAdapter->Initialized) {
  760. DBG_ERR(("A: A(%d) can't reset 4BRI adapter - please stop first",
  761. IoAdapter->ANum))
  762. return (-1);
  763. }
  764. /*
  765. Forget all entities on all adapters
  766. */
  767. for (i = 0; ((i < IoAdapter->tasks) && IoAdapter->QuadroList); i++) {
  768. Slave = IoAdapter->QuadroList->QuadroAdapter[i];
  769. Slave->e_count = 0;
  770. if (Slave->e_tbl) {
  771. memset(Slave->e_tbl, 0x00,
  772. Slave->e_max * sizeof(E_INFO));
  773. }
  774. Slave->head = 0;
  775. Slave->tail = 0;
  776. Slave->assign = 0;
  777. Slave->trapped = 0;
  778. memset(&Slave->a.IdTable[0], 0x00,
  779. sizeof(Slave->a.IdTable));
  780. memset(&Slave->a.IdTypeTable[0], 0x00,
  781. sizeof(Slave->a.IdTypeTable));
  782. memset(&Slave->a.FlowControlIdTable[0], 0x00,
  783. sizeof(Slave->a.FlowControlIdTable));
  784. memset(&Slave->a.FlowControlSkipTable[0], 0x00,
  785. sizeof(Slave->a.FlowControlSkipTable));
  786. memset(&Slave->a.misc_flags_table[0], 0x00,
  787. sizeof(Slave->a.misc_flags_table));
  788. memset(&Slave->a.rx_stream[0], 0x00,
  789. sizeof(Slave->a.rx_stream));
  790. memset(&Slave->a.tx_stream[0], 0x00,
  791. sizeof(Slave->a.tx_stream));
  792. memset(&Slave->a.tx_pos[0], 0x00, sizeof(Slave->a.tx_pos));
  793. memset(&Slave->a.rx_pos[0], 0x00, sizeof(Slave->a.rx_pos));
  794. }
  795. return (0);
  796. }
  797. static int
  798. diva_4bri_write_sdram_block(PISDN_ADAPTER IoAdapter,
  799. dword address,
  800. const byte *data, dword length, dword limit)
  801. {
  802. byte __iomem *p = DIVA_OS_MEM_ATTACH_ADDRESS(IoAdapter);
  803. byte __iomem *mem = p;
  804. if (((address + length) >= limit) || !mem) {
  805. DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, p);
  806. DBG_ERR(("A: A(%d) write 4BRI address=0x%08lx",
  807. IoAdapter->ANum, address + length))
  808. return (-1);
  809. }
  810. mem += address;
  811. while (length--) {
  812. WRITE_BYTE(mem++, *data++);
  813. }
  814. DIVA_OS_MEM_DETACH_ADDRESS(IoAdapter, p);
  815. return (0);
  816. }
  817. static int
  818. diva_4bri_start_adapter(PISDN_ADAPTER IoAdapter,
  819. dword start_address, dword features)
  820. {
  821. volatile word __iomem *signature;
  822. int started = 0;
  823. int i;
  824. byte __iomem *p;
  825. /*
  826. start adapter
  827. */
  828. start_qBri_hardware(IoAdapter);
  829. p = DIVA_OS_MEM_ATTACH_RAM(IoAdapter);
  830. /*
  831. wait for signature in shared memory (max. 3 seconds)
  832. */
  833. signature = (volatile word __iomem *) (&p[0x1E]);
  834. for (i = 0; i < 300; ++i) {
  835. diva_os_wait(10);
  836. if (READ_WORD(&signature[0]) == 0x4447) {
  837. DBG_TRC(("Protocol startup time %d.%02d seconds",
  838. (i / 100), (i % 100)))
  839. started = 1;
  840. break;
  841. }
  842. }
  843. for (i = 1; i < IoAdapter->tasks; i++) {
  844. IoAdapter->QuadroList->QuadroAdapter[i]->features =
  845. IoAdapter->features;
  846. IoAdapter->QuadroList->QuadroAdapter[i]->a.
  847. protocol_capabilities = IoAdapter->features;
  848. }
  849. if (!started) {
  850. DBG_FTL(("%s: Adapter selftest failed, signature=%04x",
  851. IoAdapter->Properties.Name,
  852. READ_WORD(&signature[0])))
  853. DIVA_OS_MEM_DETACH_RAM(IoAdapter, p);
  854. (*(IoAdapter->trapFnc)) (IoAdapter);
  855. IoAdapter->stop(IoAdapter);
  856. return (-1);
  857. }
  858. DIVA_OS_MEM_DETACH_RAM(IoAdapter, p);
  859. for (i = 0; i < IoAdapter->tasks; i++) {
  860. IoAdapter->QuadroList->QuadroAdapter[i]->Initialized = 1;
  861. IoAdapter->QuadroList->QuadroAdapter[i]->IrqCount = 0;
  862. }
  863. if (check_qBri_interrupt(IoAdapter)) {
  864. DBG_ERR(("A: A(%d) interrupt test failed",
  865. IoAdapter->ANum))
  866. for (i = 0; i < IoAdapter->tasks; i++) {
  867. IoAdapter->QuadroList->QuadroAdapter[i]->Initialized = 0;
  868. }
  869. IoAdapter->stop(IoAdapter);
  870. return (-1);
  871. }
  872. IoAdapter->Properties.Features = (word) features;
  873. diva_xdi_display_adapter_features(IoAdapter->ANum);
  874. for (i = 0; i < IoAdapter->tasks; i++) {
  875. DBG_LOG(("A(%d) %s adapter successfully started",
  876. IoAdapter->QuadroList->QuadroAdapter[i]->ANum,
  877. (IoAdapter->tasks == 1) ? "BRI 2.0" : "4BRI"))
  878. diva_xdi_didd_register_adapter(IoAdapter->QuadroList->QuadroAdapter[i]->ANum);
  879. IoAdapter->QuadroList->QuadroAdapter[i]->Properties.Features = (word) features;
  880. }
  881. return (0);
  882. }
  883. static int check_qBri_interrupt(PISDN_ADAPTER IoAdapter)
  884. {
  885. #ifdef SUPPORT_INTERRUPT_TEST_ON_4BRI
  886. int i;
  887. ADAPTER *a = &IoAdapter->a;
  888. byte __iomem *p;
  889. IoAdapter->IrqCount = 0;
  890. if (IoAdapter->ControllerNumber > 0)
  891. return (-1);
  892. p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
  893. WRITE_BYTE(&p[PLX9054_INTCSR], PLX9054_INT_ENABLE);
  894. DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
  895. /*
  896. interrupt test
  897. */
  898. a->ReadyInt = 1;
  899. a->ram_out(a, &PR_RAM->ReadyInt, 1);
  900. for (i = 100; !IoAdapter->IrqCount && (i-- > 0); diva_os_wait(10));
  901. return ((IoAdapter->IrqCount > 0) ? 0 : -1);
  902. #else
  903. dword volatile __iomem *qBriIrq;
  904. byte __iomem *p;
  905. /*
  906. Reset on-board interrupt register
  907. */
  908. IoAdapter->IrqCount = 0;
  909. p = DIVA_OS_MEM_ATTACH_CTLREG(IoAdapter);
  910. qBriIrq = (dword volatile __iomem *) (&p[_4bri_is_rev_2_card
  911. (IoAdapter->
  912. cardType) ? (MQ2_BREG_IRQ_TEST)
  913. : (MQ_BREG_IRQ_TEST)]);
  914. WRITE_DWORD(qBriIrq, MQ_IRQ_REQ_OFF);
  915. DIVA_OS_MEM_DETACH_CTLREG(IoAdapter, p);
  916. p = DIVA_OS_MEM_ATTACH_RESET(IoAdapter);
  917. WRITE_BYTE(&p[PLX9054_INTCSR], PLX9054_INT_ENABLE);
  918. DIVA_OS_MEM_DETACH_RESET(IoAdapter, p);
  919. diva_os_wait(100);
  920. return (0);
  921. #endif /* SUPPORT_INTERRUPT_TEST_ON_4BRI */
  922. }
  923. static void diva_4bri_clear_interrupts(diva_os_xdi_adapter_t *a)
  924. {
  925. PISDN_ADAPTER IoAdapter = &a->xdi_adapter;
  926. /*
  927. clear any pending interrupt
  928. */
  929. IoAdapter->disIrq(IoAdapter);
  930. IoAdapter->tst_irq(&IoAdapter->a);
  931. IoAdapter->clr_irq(&IoAdapter->a);
  932. IoAdapter->tst_irq(&IoAdapter->a);
  933. /*
  934. kill pending dpcs
  935. */
  936. diva_os_cancel_soft_isr(&IoAdapter->req_soft_isr);
  937. diva_os_cancel_soft_isr(&IoAdapter->isr_soft_isr);
  938. }
  939. static int diva_4bri_stop_adapter(diva_os_xdi_adapter_t *a)
  940. {
  941. PISDN_ADAPTER IoAdapter = &a->xdi_adapter;
  942. int i;
  943. if (!IoAdapter->ram) {
  944. return (-1);
  945. }
  946. if (!IoAdapter->Initialized) {
  947. DBG_ERR(("A: A(%d) can't stop PRI adapter - not running",
  948. IoAdapter->ANum))
  949. return (-1); /* nothing to stop */
  950. }
  951. for (i = 0; i < IoAdapter->tasks; i++) {
  952. IoAdapter->QuadroList->QuadroAdapter[i]->Initialized = 0;
  953. }
  954. /*
  955. Disconnect Adapters from DIDD
  956. */
  957. for (i = 0; i < IoAdapter->tasks; i++) {
  958. diva_xdi_didd_remove_adapter(IoAdapter->QuadroList->QuadroAdapter[i]->ANum);
  959. }
  960. i = 100;
  961. /*
  962. Stop interrupts
  963. */
  964. a->clear_interrupts_proc = diva_4bri_clear_interrupts;
  965. IoAdapter->a.ReadyInt = 1;
  966. IoAdapter->a.ram_inc(&IoAdapter->a, &PR_RAM->ReadyInt);
  967. do {
  968. diva_os_sleep(10);
  969. } while (i-- && a->clear_interrupts_proc);
  970. if (a->clear_interrupts_proc) {
  971. diva_4bri_clear_interrupts(a);
  972. a->clear_interrupts_proc = NULL;
  973. DBG_ERR(("A: A(%d) no final interrupt from 4BRI adapter",
  974. IoAdapter->ANum))
  975. }
  976. IoAdapter->a.ReadyInt = 0;
  977. /*
  978. Stop and reset adapter
  979. */
  980. IoAdapter->stop(IoAdapter);
  981. return (0);
  982. }