omap_crtc.c 15 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_crtc.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <drm/drm_atomic.h>
  20. #include <drm/drm_atomic_helper.h>
  21. #include <drm/drm_crtc.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_plane_helper.h>
  25. #include "omap_drv.h"
  26. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  27. struct omap_crtc {
  28. struct drm_crtc base;
  29. const char *name;
  30. enum omap_channel channel;
  31. struct omap_video_timings timings;
  32. struct omap_drm_irq vblank_irq;
  33. struct omap_drm_irq error_irq;
  34. bool ignore_digit_sync_lost;
  35. bool pending;
  36. wait_queue_head_t pending_wait;
  37. };
  38. /* -----------------------------------------------------------------------------
  39. * Helper Functions
  40. */
  41. uint32_t pipe2vbl(struct drm_crtc *crtc)
  42. {
  43. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  44. return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  45. }
  46. struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
  47. {
  48. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  49. return &omap_crtc->timings;
  50. }
  51. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  52. {
  53. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  54. return omap_crtc->channel;
  55. }
  56. int omap_crtc_wait_pending(struct drm_crtc *crtc)
  57. {
  58. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  59. /*
  60. * Timeout is set to a "sufficiently" high value, which should cover
  61. * a single frame refresh even on slower displays.
  62. */
  63. return wait_event_timeout(omap_crtc->pending_wait,
  64. !omap_crtc->pending,
  65. msecs_to_jiffies(250));
  66. }
  67. /* -----------------------------------------------------------------------------
  68. * DSS Manager Functions
  69. */
  70. /*
  71. * Manager-ops, callbacks from output when they need to configure
  72. * the upstream part of the video pipe.
  73. *
  74. * Most of these we can ignore until we add support for command-mode
  75. * panels.. for video-mode the crtc-helpers already do an adequate
  76. * job of sequencing the setup of the video pipe in the proper order
  77. */
  78. /* ovl-mgr-id -> crtc */
  79. static struct omap_crtc *omap_crtcs[8];
  80. static struct omap_dss_device *omap_crtc_output[8];
  81. /* we can probably ignore these until we support command-mode panels: */
  82. static int omap_crtc_dss_connect(enum omap_channel channel,
  83. struct omap_dss_device *dst)
  84. {
  85. if (omap_crtc_output[channel])
  86. return -EINVAL;
  87. if ((dispc_mgr_get_supported_outputs(channel) & dst->id) == 0)
  88. return -EINVAL;
  89. omap_crtc_output[channel] = dst;
  90. dst->dispc_channel_connected = true;
  91. return 0;
  92. }
  93. static void omap_crtc_dss_disconnect(enum omap_channel channel,
  94. struct omap_dss_device *dst)
  95. {
  96. omap_crtc_output[channel] = NULL;
  97. dst->dispc_channel_connected = false;
  98. }
  99. static void omap_crtc_dss_start_update(enum omap_channel channel)
  100. {
  101. }
  102. /* Called only from the encoder enable/disable and suspend/resume handlers. */
  103. static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
  104. {
  105. struct drm_device *dev = crtc->dev;
  106. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  107. enum omap_channel channel = omap_crtc->channel;
  108. struct omap_irq_wait *wait;
  109. u32 framedone_irq, vsync_irq;
  110. int ret;
  111. if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
  112. dispc_mgr_enable(channel, enable);
  113. return;
  114. }
  115. if (dispc_mgr_is_enabled(channel) == enable)
  116. return;
  117. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  118. /*
  119. * Digit output produces some sync lost interrupts during the
  120. * first frame when enabling, so we need to ignore those.
  121. */
  122. omap_crtc->ignore_digit_sync_lost = true;
  123. }
  124. framedone_irq = dispc_mgr_get_framedone_irq(channel);
  125. vsync_irq = dispc_mgr_get_vsync_irq(channel);
  126. if (enable) {
  127. wait = omap_irq_wait_init(dev, vsync_irq, 1);
  128. } else {
  129. /*
  130. * When we disable the digit output, we need to wait for
  131. * FRAMEDONE to know that DISPC has finished with the output.
  132. *
  133. * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
  134. * that case we need to use vsync interrupt, and wait for both
  135. * even and odd frames.
  136. */
  137. if (framedone_irq)
  138. wait = omap_irq_wait_init(dev, framedone_irq, 1);
  139. else
  140. wait = omap_irq_wait_init(dev, vsync_irq, 2);
  141. }
  142. dispc_mgr_enable(channel, enable);
  143. ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  144. if (ret) {
  145. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  146. omap_crtc->name, enable ? "enable" : "disable");
  147. }
  148. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  149. omap_crtc->ignore_digit_sync_lost = false;
  150. /* make sure the irq handler sees the value above */
  151. mb();
  152. }
  153. }
  154. static int omap_crtc_dss_enable(enum omap_channel channel)
  155. {
  156. struct omap_crtc *omap_crtc = omap_crtcs[channel];
  157. struct omap_overlay_manager_info info;
  158. memset(&info, 0, sizeof(info));
  159. info.default_color = 0x00000000;
  160. info.trans_key = 0x00000000;
  161. info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
  162. info.trans_enabled = false;
  163. dispc_mgr_setup(omap_crtc->channel, &info);
  164. dispc_mgr_set_timings(omap_crtc->channel,
  165. &omap_crtc->timings);
  166. omap_crtc_set_enabled(&omap_crtc->base, true);
  167. return 0;
  168. }
  169. static void omap_crtc_dss_disable(enum omap_channel channel)
  170. {
  171. struct omap_crtc *omap_crtc = omap_crtcs[channel];
  172. omap_crtc_set_enabled(&omap_crtc->base, false);
  173. }
  174. static void omap_crtc_dss_set_timings(enum omap_channel channel,
  175. const struct omap_video_timings *timings)
  176. {
  177. struct omap_crtc *omap_crtc = omap_crtcs[channel];
  178. DBG("%s", omap_crtc->name);
  179. omap_crtc->timings = *timings;
  180. }
  181. static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
  182. const struct dss_lcd_mgr_config *config)
  183. {
  184. struct omap_crtc *omap_crtc = omap_crtcs[channel];
  185. DBG("%s", omap_crtc->name);
  186. dispc_mgr_set_lcd_config(omap_crtc->channel, config);
  187. }
  188. static int omap_crtc_dss_register_framedone(
  189. enum omap_channel channel,
  190. void (*handler)(void *), void *data)
  191. {
  192. return 0;
  193. }
  194. static void omap_crtc_dss_unregister_framedone(
  195. enum omap_channel channel,
  196. void (*handler)(void *), void *data)
  197. {
  198. }
  199. static const struct dss_mgr_ops mgr_ops = {
  200. .connect = omap_crtc_dss_connect,
  201. .disconnect = omap_crtc_dss_disconnect,
  202. .start_update = omap_crtc_dss_start_update,
  203. .enable = omap_crtc_dss_enable,
  204. .disable = omap_crtc_dss_disable,
  205. .set_timings = omap_crtc_dss_set_timings,
  206. .set_lcd_config = omap_crtc_dss_set_lcd_config,
  207. .register_framedone_handler = omap_crtc_dss_register_framedone,
  208. .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
  209. };
  210. /* -----------------------------------------------------------------------------
  211. * Setup, Flush and Page Flip
  212. */
  213. static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
  214. {
  215. struct drm_pending_vblank_event *event;
  216. struct drm_device *dev = crtc->dev;
  217. unsigned long flags;
  218. event = crtc->state->event;
  219. if (!event)
  220. return;
  221. spin_lock_irqsave(&dev->event_lock, flags);
  222. drm_crtc_send_vblank_event(crtc, event);
  223. spin_unlock_irqrestore(&dev->event_lock, flags);
  224. }
  225. static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  226. {
  227. struct omap_crtc *omap_crtc =
  228. container_of(irq, struct omap_crtc, error_irq);
  229. if (omap_crtc->ignore_digit_sync_lost) {
  230. irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
  231. if (!irqstatus)
  232. return;
  233. }
  234. DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  235. }
  236. static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  237. {
  238. struct omap_crtc *omap_crtc =
  239. container_of(irq, struct omap_crtc, vblank_irq);
  240. struct drm_device *dev = omap_crtc->base.dev;
  241. if (dispc_mgr_go_busy(omap_crtc->channel))
  242. return;
  243. DBG("%s: apply done", omap_crtc->name);
  244. __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
  245. rmb();
  246. WARN_ON(!omap_crtc->pending);
  247. omap_crtc->pending = false;
  248. wmb();
  249. /* wake up userspace */
  250. omap_crtc_complete_page_flip(&omap_crtc->base);
  251. /* wake up omap_atomic_complete */
  252. wake_up(&omap_crtc->pending_wait);
  253. }
  254. /* -----------------------------------------------------------------------------
  255. * CRTC Functions
  256. */
  257. static void omap_crtc_destroy(struct drm_crtc *crtc)
  258. {
  259. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  260. DBG("%s", omap_crtc->name);
  261. WARN_ON(omap_crtc->vblank_irq.registered);
  262. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  263. drm_crtc_cleanup(crtc);
  264. kfree(omap_crtc);
  265. }
  266. static void omap_crtc_enable(struct drm_crtc *crtc)
  267. {
  268. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  269. DBG("%s", omap_crtc->name);
  270. rmb();
  271. WARN_ON(omap_crtc->pending);
  272. omap_crtc->pending = true;
  273. wmb();
  274. omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
  275. drm_crtc_vblank_on(crtc);
  276. }
  277. static void omap_crtc_disable(struct drm_crtc *crtc)
  278. {
  279. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  280. DBG("%s", omap_crtc->name);
  281. drm_crtc_vblank_off(crtc);
  282. }
  283. static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
  284. {
  285. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  286. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  287. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  288. omap_crtc->name, mode->base.id, mode->name,
  289. mode->vrefresh, mode->clock,
  290. mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
  291. mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
  292. mode->type, mode->flags);
  293. copy_timings_drm_to_omap(&omap_crtc->timings, mode);
  294. }
  295. static int omap_crtc_atomic_check(struct drm_crtc *crtc,
  296. struct drm_crtc_state *state)
  297. {
  298. if (state->color_mgmt_changed && state->gamma_lut) {
  299. uint length = state->gamma_lut->length /
  300. sizeof(struct drm_color_lut);
  301. if (length < 2)
  302. return -EINVAL;
  303. }
  304. return 0;
  305. }
  306. static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
  307. struct drm_crtc_state *old_crtc_state)
  308. {
  309. }
  310. static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
  311. struct drm_crtc_state *old_crtc_state)
  312. {
  313. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  314. WARN_ON(omap_crtc->vblank_irq.registered);
  315. if (crtc->state->color_mgmt_changed) {
  316. struct drm_color_lut *lut = NULL;
  317. uint length = 0;
  318. if (crtc->state->gamma_lut) {
  319. lut = (struct drm_color_lut *)
  320. crtc->state->gamma_lut->data;
  321. length = crtc->state->gamma_lut->length /
  322. sizeof(*lut);
  323. }
  324. dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
  325. }
  326. if (crtc->state->color_mgmt_changed) {
  327. struct drm_color_lut *lut = NULL;
  328. uint length = 0;
  329. if (crtc->state->gamma_lut) {
  330. lut = (struct drm_color_lut *)
  331. crtc->state->gamma_lut->data;
  332. length = crtc->state->gamma_lut->length /
  333. sizeof(*lut);
  334. }
  335. dispc_mgr_set_gamma(omap_crtc->channel, lut, length);
  336. }
  337. if (dispc_mgr_is_enabled(omap_crtc->channel)) {
  338. DBG("%s: GO", omap_crtc->name);
  339. rmb();
  340. WARN_ON(omap_crtc->pending);
  341. omap_crtc->pending = true;
  342. wmb();
  343. dispc_mgr_go(omap_crtc->channel);
  344. omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
  345. }
  346. }
  347. static bool omap_crtc_is_plane_prop(struct drm_device *dev,
  348. struct drm_property *property)
  349. {
  350. struct omap_drm_private *priv = dev->dev_private;
  351. return property == priv->zorder_prop ||
  352. property == dev->mode_config.rotation_property;
  353. }
  354. static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
  355. struct drm_crtc_state *state,
  356. struct drm_property *property,
  357. uint64_t val)
  358. {
  359. struct drm_device *dev = crtc->dev;
  360. if (omap_crtc_is_plane_prop(dev, property)) {
  361. struct drm_plane_state *plane_state;
  362. struct drm_plane *plane = crtc->primary;
  363. /*
  364. * Delegate property set to the primary plane. Get the plane
  365. * state and set the property directly.
  366. */
  367. plane_state = drm_atomic_get_plane_state(state->state, plane);
  368. if (IS_ERR(plane_state))
  369. return PTR_ERR(plane_state);
  370. return drm_atomic_plane_set_property(plane, plane_state,
  371. property, val);
  372. }
  373. return -EINVAL;
  374. }
  375. static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
  376. const struct drm_crtc_state *state,
  377. struct drm_property *property,
  378. uint64_t *val)
  379. {
  380. struct drm_device *dev = crtc->dev;
  381. if (omap_crtc_is_plane_prop(dev, property)) {
  382. /*
  383. * Delegate property get to the primary plane. The
  384. * drm_atomic_plane_get_property() function isn't exported, but
  385. * can be called through drm_object_property_get_value() as that
  386. * will call drm_atomic_get_property() for atomic drivers.
  387. */
  388. return drm_object_property_get_value(&crtc->primary->base,
  389. property, val);
  390. }
  391. return -EINVAL;
  392. }
  393. static const struct drm_crtc_funcs omap_crtc_funcs = {
  394. .reset = drm_atomic_helper_crtc_reset,
  395. .set_config = drm_atomic_helper_set_config,
  396. .destroy = omap_crtc_destroy,
  397. .page_flip = drm_atomic_helper_page_flip,
  398. .gamma_set = drm_atomic_helper_legacy_gamma_set,
  399. .set_property = drm_atomic_helper_crtc_set_property,
  400. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  401. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  402. .atomic_set_property = omap_crtc_atomic_set_property,
  403. .atomic_get_property = omap_crtc_atomic_get_property,
  404. };
  405. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  406. .mode_set_nofb = omap_crtc_mode_set_nofb,
  407. .disable = omap_crtc_disable,
  408. .enable = omap_crtc_enable,
  409. .atomic_check = omap_crtc_atomic_check,
  410. .atomic_begin = omap_crtc_atomic_begin,
  411. .atomic_flush = omap_crtc_atomic_flush,
  412. };
  413. /* -----------------------------------------------------------------------------
  414. * Init and Cleanup
  415. */
  416. static const char *channel_names[] = {
  417. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  418. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  419. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  420. [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
  421. };
  422. void omap_crtc_pre_init(void)
  423. {
  424. dss_install_mgr_ops(&mgr_ops);
  425. }
  426. void omap_crtc_pre_uninit(void)
  427. {
  428. dss_uninstall_mgr_ops();
  429. }
  430. /* initialize crtc */
  431. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  432. struct drm_plane *plane, enum omap_channel channel, int id)
  433. {
  434. struct drm_crtc *crtc = NULL;
  435. struct omap_crtc *omap_crtc;
  436. int ret;
  437. DBG("%s", channel_names[channel]);
  438. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  439. if (!omap_crtc)
  440. return NULL;
  441. crtc = &omap_crtc->base;
  442. init_waitqueue_head(&omap_crtc->pending_wait);
  443. omap_crtc->channel = channel;
  444. omap_crtc->name = channel_names[channel];
  445. omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
  446. omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
  447. omap_crtc->error_irq.irqmask =
  448. dispc_mgr_get_sync_lost_irq(channel);
  449. omap_crtc->error_irq.irq = omap_crtc_error_irq;
  450. omap_irq_register(dev, &omap_crtc->error_irq);
  451. ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
  452. &omap_crtc_funcs, NULL);
  453. if (ret < 0) {
  454. kfree(omap_crtc);
  455. return NULL;
  456. }
  457. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  458. /* The dispc API adapts to what ever size, but the HW supports
  459. * 256 element gamma table for LCDs and 1024 element table for
  460. * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
  461. * tables so lets use that. Size of HW gamma table can be
  462. * extracted with dispc_mgr_gamma_size(). If it returns 0
  463. * gamma table is not supprted.
  464. */
  465. if (dispc_mgr_gamma_size(channel)) {
  466. uint gamma_lut_size = 256;
  467. drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
  468. drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
  469. }
  470. omap_plane_install_properties(crtc->primary, &crtc->base);
  471. omap_crtcs[channel] = omap_crtc;
  472. return crtc;
  473. }