mtk_drm_ddp_comp.c 9.7 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Authors:
  4. * YT Shen <yt.shen@mediatek.com>
  5. * CK Hu <ck.hu@mediatek.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of_platform.h>
  21. #include <linux/platform_device.h>
  22. #include <drm/drmP.h>
  23. #include "mtk_drm_drv.h"
  24. #include "mtk_drm_plane.h"
  25. #include "mtk_drm_ddp_comp.h"
  26. #include "mtk_drm_crtc.h"
  27. #define DISP_OD_EN 0x0000
  28. #define DISP_OD_INTEN 0x0008
  29. #define DISP_OD_INTSTA 0x000c
  30. #define DISP_OD_CFG 0x0020
  31. #define DISP_OD_SIZE 0x0030
  32. #define DISP_DITHER_5 0x0114
  33. #define DISP_DITHER_7 0x011c
  34. #define DISP_DITHER_15 0x013c
  35. #define DISP_DITHER_16 0x0140
  36. #define DISP_REG_UFO_START 0x0000
  37. #define DISP_COLOR_CFG_MAIN 0x0400
  38. #define DISP_COLOR_START 0x0c00
  39. #define DISP_COLOR_WIDTH 0x0c50
  40. #define DISP_COLOR_HEIGHT 0x0c54
  41. #define DISP_AAL_EN 0x0000
  42. #define DISP_AAL_SIZE 0x0030
  43. #define DISP_GAMMA_EN 0x0000
  44. #define DISP_GAMMA_CFG 0x0020
  45. #define DISP_GAMMA_SIZE 0x0030
  46. #define DISP_GAMMA_LUT 0x0700
  47. #define LUT_10BIT_MASK 0x03ff
  48. #define COLOR_BYPASS_ALL BIT(7)
  49. #define COLOR_SEQ_SEL BIT(13)
  50. #define OD_RELAYMODE BIT(0)
  51. #define UFO_BYPASS BIT(2)
  52. #define AAL_EN BIT(0)
  53. #define GAMMA_EN BIT(0)
  54. #define GAMMA_LUT_EN BIT(1)
  55. #define DISP_DITHERING BIT(2)
  56. #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
  57. #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
  58. #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
  59. #define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
  60. #define DITHER_NEW_BIT_MODE BIT(0)
  61. #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
  62. #define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
  63. #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
  64. #define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
  65. #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
  66. #define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
  67. #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
  68. #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
  69. void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
  70. unsigned int CFG)
  71. {
  72. /* If bpc equal to 0, the dithering function didn't be enabled */
  73. if (bpc == 0)
  74. return;
  75. if (bpc >= MTK_MIN_BPC) {
  76. writel(0, comp->regs + DISP_DITHER_5);
  77. writel(0, comp->regs + DISP_DITHER_7);
  78. writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
  79. DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
  80. DITHER_NEW_BIT_MODE,
  81. comp->regs + DISP_DITHER_15);
  82. writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
  83. DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
  84. DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
  85. DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
  86. comp->regs + DISP_DITHER_16);
  87. writel(DISP_DITHERING, comp->regs + CFG);
  88. }
  89. }
  90. static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
  91. unsigned int h, unsigned int vrefresh,
  92. unsigned int bpc)
  93. {
  94. writel(w, comp->regs + DISP_COLOR_WIDTH);
  95. writel(h, comp->regs + DISP_COLOR_HEIGHT);
  96. }
  97. static void mtk_color_start(struct mtk_ddp_comp *comp)
  98. {
  99. writel(COLOR_BYPASS_ALL | COLOR_SEQ_SEL,
  100. comp->regs + DISP_COLOR_CFG_MAIN);
  101. writel(0x1, comp->regs + DISP_COLOR_START);
  102. }
  103. static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
  104. unsigned int h, unsigned int vrefresh,
  105. unsigned int bpc)
  106. {
  107. writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
  108. writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
  109. mtk_dither_set(comp, bpc, DISP_OD_CFG);
  110. }
  111. static void mtk_od_start(struct mtk_ddp_comp *comp)
  112. {
  113. writel(1, comp->regs + DISP_OD_EN);
  114. }
  115. static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
  116. {
  117. writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
  118. }
  119. static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
  120. unsigned int h, unsigned int vrefresh,
  121. unsigned int bpc)
  122. {
  123. writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
  124. }
  125. static void mtk_aal_start(struct mtk_ddp_comp *comp)
  126. {
  127. writel(AAL_EN, comp->regs + DISP_AAL_EN);
  128. }
  129. static void mtk_aal_stop(struct mtk_ddp_comp *comp)
  130. {
  131. writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
  132. }
  133. static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
  134. unsigned int h, unsigned int vrefresh,
  135. unsigned int bpc)
  136. {
  137. writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
  138. mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
  139. }
  140. static void mtk_gamma_start(struct mtk_ddp_comp *comp)
  141. {
  142. writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN);
  143. }
  144. static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
  145. {
  146. writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
  147. }
  148. static void mtk_gamma_set(struct mtk_ddp_comp *comp,
  149. struct drm_crtc_state *state)
  150. {
  151. unsigned int i, reg;
  152. struct drm_color_lut *lut;
  153. void __iomem *lut_base;
  154. u32 word;
  155. if (state->gamma_lut) {
  156. reg = readl(comp->regs + DISP_GAMMA_CFG);
  157. reg = reg | GAMMA_LUT_EN;
  158. writel(reg, comp->regs + DISP_GAMMA_CFG);
  159. lut_base = comp->regs + DISP_GAMMA_LUT;
  160. lut = (struct drm_color_lut *)state->gamma_lut->data;
  161. for (i = 0; i < MTK_LUT_SIZE; i++) {
  162. word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
  163. (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
  164. ((lut[i].blue >> 6) & LUT_10BIT_MASK);
  165. writel(word, (lut_base + i * 4));
  166. }
  167. }
  168. }
  169. static const struct mtk_ddp_comp_funcs ddp_aal = {
  170. .gamma_set = mtk_gamma_set,
  171. .config = mtk_aal_config,
  172. .start = mtk_aal_start,
  173. .stop = mtk_aal_stop,
  174. };
  175. static const struct mtk_ddp_comp_funcs ddp_gamma = {
  176. .gamma_set = mtk_gamma_set,
  177. .config = mtk_gamma_config,
  178. .start = mtk_gamma_start,
  179. .stop = mtk_gamma_stop,
  180. };
  181. static const struct mtk_ddp_comp_funcs ddp_color = {
  182. .config = mtk_color_config,
  183. .start = mtk_color_start,
  184. };
  185. static const struct mtk_ddp_comp_funcs ddp_od = {
  186. .config = mtk_od_config,
  187. .start = mtk_od_start,
  188. };
  189. static const struct mtk_ddp_comp_funcs ddp_ufoe = {
  190. .start = mtk_ufoe_start,
  191. };
  192. static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
  193. [MTK_DISP_OVL] = "ovl",
  194. [MTK_DISP_RDMA] = "rdma",
  195. [MTK_DISP_WDMA] = "wdma",
  196. [MTK_DISP_COLOR] = "color",
  197. [MTK_DISP_AAL] = "aal",
  198. [MTK_DISP_GAMMA] = "gamma",
  199. [MTK_DISP_UFOE] = "ufoe",
  200. [MTK_DSI] = "dsi",
  201. [MTK_DPI] = "dpi",
  202. [MTK_DISP_PWM] = "pwm",
  203. [MTK_DISP_MUTEX] = "mutex",
  204. [MTK_DISP_OD] = "od",
  205. };
  206. struct mtk_ddp_comp_match {
  207. enum mtk_ddp_comp_type type;
  208. int alias_id;
  209. const struct mtk_ddp_comp_funcs *funcs;
  210. };
  211. static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
  212. [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
  213. [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
  214. [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
  215. [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
  216. [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
  217. [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
  218. [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
  219. [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
  220. [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
  221. [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
  222. [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
  223. [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
  224. [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
  225. [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
  226. [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
  227. [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
  228. [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
  229. };
  230. int mtk_ddp_comp_get_id(struct device_node *node,
  231. enum mtk_ddp_comp_type comp_type)
  232. {
  233. int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
  234. int i;
  235. for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
  236. if (comp_type == mtk_ddp_matches[i].type &&
  237. (id < 0 || id == mtk_ddp_matches[i].alias_id))
  238. return i;
  239. }
  240. return -EINVAL;
  241. }
  242. int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
  243. struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
  244. const struct mtk_ddp_comp_funcs *funcs)
  245. {
  246. enum mtk_ddp_comp_type type;
  247. struct device_node *larb_node;
  248. struct platform_device *larb_pdev;
  249. if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
  250. return -EINVAL;
  251. comp->id = comp_id;
  252. comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
  253. if (comp_id == DDP_COMPONENT_DPI0 ||
  254. comp_id == DDP_COMPONENT_DSI0 ||
  255. comp_id == DDP_COMPONENT_PWM0) {
  256. comp->regs = NULL;
  257. comp->clk = NULL;
  258. comp->irq = 0;
  259. return 0;
  260. }
  261. comp->regs = of_iomap(node, 0);
  262. comp->irq = of_irq_get(node, 0);
  263. comp->clk = of_clk_get(node, 0);
  264. if (IS_ERR(comp->clk))
  265. comp->clk = NULL;
  266. type = mtk_ddp_matches[comp_id].type;
  267. /* Only DMA capable components need the LARB property */
  268. comp->larb_dev = NULL;
  269. if (type != MTK_DISP_OVL &&
  270. type != MTK_DISP_RDMA &&
  271. type != MTK_DISP_WDMA)
  272. return 0;
  273. larb_node = of_parse_phandle(node, "mediatek,larb", 0);
  274. if (!larb_node) {
  275. dev_err(dev,
  276. "Missing mediadek,larb phandle in %s node\n",
  277. node->full_name);
  278. return -EINVAL;
  279. }
  280. larb_pdev = of_find_device_by_node(larb_node);
  281. if (!larb_pdev) {
  282. dev_warn(dev, "Waiting for larb device %s\n",
  283. larb_node->full_name);
  284. of_node_put(larb_node);
  285. return -EPROBE_DEFER;
  286. }
  287. of_node_put(larb_node);
  288. comp->larb_dev = &larb_pdev->dev;
  289. return 0;
  290. }
  291. int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
  292. {
  293. struct mtk_drm_private *private = drm->dev_private;
  294. if (private->ddp_comp[comp->id])
  295. return -EBUSY;
  296. private->ddp_comp[comp->id] = comp;
  297. return 0;
  298. }
  299. void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
  300. {
  301. struct mtk_drm_private *private = drm->dev_private;
  302. private->ddp_comp[comp->id] = NULL;
  303. }