mpc8379_rdb.dts 10 KB

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  1. /*
  2. * MPC8379E RDB Device Tree Source
  3. *
  4. * Copyright 2007, 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. compatible = "fsl,mpc8379rdb";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. ethernet0 = &enet0;
  18. ethernet1 = &enet1;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8379@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>; // 256MB at 0
  41. };
  42. localbus@e0005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
  46. reg = <0xe0005000 0x1000>;
  47. interrupts = <77 0x8>;
  48. interrupt-parent = <&ipic>;
  49. // CS0 and CS1 are swapped when
  50. // booting from nand, but the
  51. // addresses are the same.
  52. ranges = <0x0 0x0 0xfe000000 0x00800000
  53. 0x1 0x0 0xe0600000 0x00008000
  54. 0x2 0x0 0xf0000000 0x00020000
  55. 0x3 0x0 0xfa000000 0x00008000>;
  56. flash@0,0 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "cfi-flash";
  60. reg = <0x0 0x0 0x800000>;
  61. bank-width = <2>;
  62. device-width = <1>;
  63. };
  64. nand@1,0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "fsl,mpc8379-fcm-nand",
  68. "fsl,elbc-fcm-nand";
  69. reg = <0x1 0x0 0x8000>;
  70. u-boot@0 {
  71. reg = <0x0 0x100000>;
  72. read-only;
  73. };
  74. kernel@100000 {
  75. reg = <0x100000 0x300000>;
  76. };
  77. fs@400000 {
  78. reg = <0x400000 0x1c00000>;
  79. };
  80. };
  81. };
  82. immr@e0000000 {
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. device_type = "soc";
  86. compatible = "simple-bus";
  87. ranges = <0x0 0xe0000000 0x00100000>;
  88. reg = <0xe0000000 0x00000200>;
  89. bus-frequency = <0>;
  90. wdt@200 {
  91. device_type = "watchdog";
  92. compatible = "mpc83xx_wdt";
  93. reg = <0x200 0x100>;
  94. };
  95. gpio1: gpio-controller@c00 {
  96. #gpio-cells = <2>;
  97. compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
  98. reg = <0xc00 0x100>;
  99. interrupts = <74 0x8>;
  100. interrupt-parent = <&ipic>;
  101. gpio-controller;
  102. };
  103. gpio2: gpio-controller@d00 {
  104. #gpio-cells = <2>;
  105. compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
  106. reg = <0xd00 0x100>;
  107. interrupts = <75 0x8>;
  108. interrupt-parent = <&ipic>;
  109. gpio-controller;
  110. };
  111. sleep-nexus {
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. compatible = "simple-bus";
  115. sleep = <&pmc 0x0c000000>;
  116. ranges;
  117. i2c@3000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. cell-index = <0>;
  121. compatible = "fsl-i2c";
  122. reg = <0x3000 0x100>;
  123. interrupts = <14 0x8>;
  124. interrupt-parent = <&ipic>;
  125. dfsrr;
  126. dtt@48 {
  127. compatible = "national,lm75";
  128. reg = <0x48>;
  129. };
  130. at24@50 {
  131. compatible = "at24,24c256";
  132. reg = <0x50>;
  133. };
  134. rtc@68 {
  135. compatible = "dallas,ds1339";
  136. reg = <0x68>;
  137. };
  138. mcu_pio: mcu@a {
  139. #gpio-cells = <2>;
  140. compatible = "fsl,mc9s08qg8-mpc8379erdb",
  141. "fsl,mcu-mpc8349emitx";
  142. reg = <0x0a>;
  143. gpio-controller;
  144. };
  145. };
  146. sdhci@2e000 {
  147. compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
  148. reg = <0x2e000 0x1000>;
  149. interrupts = <42 0x8>;
  150. interrupt-parent = <&ipic>;
  151. sdhci,wp-inverted;
  152. /* Filled in by U-Boot */
  153. clock-frequency = <111111111>;
  154. };
  155. };
  156. i2c@3100 {
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. cell-index = <1>;
  160. compatible = "fsl-i2c";
  161. reg = <0x3100 0x100>;
  162. interrupts = <15 0x8>;
  163. interrupt-parent = <&ipic>;
  164. dfsrr;
  165. };
  166. spi@7000 {
  167. cell-index = <0>;
  168. compatible = "fsl,spi";
  169. reg = <0x7000 0x1000>;
  170. interrupts = <16 0x8>;
  171. interrupt-parent = <&ipic>;
  172. mode = "cpu";
  173. };
  174. dma@82a8 {
  175. #address-cells = <1>;
  176. #size-cells = <1>;
  177. compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
  178. reg = <0x82a8 4>;
  179. ranges = <0 0x8100 0x1a8>;
  180. interrupt-parent = <&ipic>;
  181. interrupts = <71 8>;
  182. cell-index = <0>;
  183. dma-channel@0 {
  184. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  185. reg = <0 0x80>;
  186. cell-index = <0>;
  187. interrupt-parent = <&ipic>;
  188. interrupts = <71 8>;
  189. };
  190. dma-channel@80 {
  191. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  192. reg = <0x80 0x80>;
  193. cell-index = <1>;
  194. interrupt-parent = <&ipic>;
  195. interrupts = <71 8>;
  196. };
  197. dma-channel@100 {
  198. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  199. reg = <0x100 0x80>;
  200. cell-index = <2>;
  201. interrupt-parent = <&ipic>;
  202. interrupts = <71 8>;
  203. };
  204. dma-channel@180 {
  205. compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
  206. reg = <0x180 0x28>;
  207. cell-index = <3>;
  208. interrupt-parent = <&ipic>;
  209. interrupts = <71 8>;
  210. };
  211. };
  212. usb@23000 {
  213. compatible = "fsl-usb2-dr";
  214. reg = <0x23000 0x1000>;
  215. #address-cells = <1>;
  216. #size-cells = <0>;
  217. interrupt-parent = <&ipic>;
  218. interrupts = <38 0x8>;
  219. phy_type = "ulpi";
  220. sleep = <&pmc 0x00c00000>;
  221. };
  222. enet0: ethernet@24000 {
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. cell-index = <0>;
  226. device_type = "network";
  227. model = "eTSEC";
  228. compatible = "gianfar";
  229. reg = <0x24000 0x1000>;
  230. ranges = <0x0 0x24000 0x1000>;
  231. local-mac-address = [ 00 00 00 00 00 00 ];
  232. interrupts = <32 0x8 33 0x8 34 0x8>;
  233. phy-connection-type = "mii";
  234. interrupt-parent = <&ipic>;
  235. tbi-handle = <&tbi0>;
  236. phy-handle = <&phy2>;
  237. sleep = <&pmc 0xc0000000>;
  238. fsl,magic-packet;
  239. mdio@520 {
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. compatible = "fsl,gianfar-mdio";
  243. reg = <0x520 0x20>;
  244. phy2: ethernet-phy@2 {
  245. interrupt-parent = <&ipic>;
  246. interrupts = <17 0x8>;
  247. reg = <0x2>;
  248. };
  249. tbi0: tbi-phy@11 {
  250. reg = <0x11>;
  251. device_type = "tbi-phy";
  252. };
  253. };
  254. };
  255. enet1: ethernet@25000 {
  256. #address-cells = <1>;
  257. #size-cells = <1>;
  258. cell-index = <1>;
  259. device_type = "network";
  260. model = "eTSEC";
  261. compatible = "gianfar";
  262. reg = <0x25000 0x1000>;
  263. ranges = <0x0 0x25000 0x1000>;
  264. local-mac-address = [ 00 00 00 00 00 00 ];
  265. interrupts = <35 0x8 36 0x8 37 0x8>;
  266. phy-connection-type = "mii";
  267. interrupt-parent = <&ipic>;
  268. fixed-link = <1 1 1000 0 0>;
  269. tbi-handle = <&tbi1>;
  270. sleep = <&pmc 0x30000000>;
  271. fsl,magic-packet;
  272. mdio@520 {
  273. #address-cells = <1>;
  274. #size-cells = <0>;
  275. compatible = "fsl,gianfar-tbi";
  276. reg = <0x520 0x20>;
  277. tbi1: tbi-phy@11 {
  278. reg = <0x11>;
  279. device_type = "tbi-phy";
  280. };
  281. };
  282. };
  283. serial0: serial@4500 {
  284. cell-index = <0>;
  285. device_type = "serial";
  286. compatible = "fsl,ns16550", "ns16550";
  287. reg = <0x4500 0x100>;
  288. clock-frequency = <0>;
  289. interrupts = <9 0x8>;
  290. interrupt-parent = <&ipic>;
  291. };
  292. serial1: serial@4600 {
  293. cell-index = <1>;
  294. device_type = "serial";
  295. compatible = "fsl,ns16550", "ns16550";
  296. reg = <0x4600 0x100>;
  297. clock-frequency = <0>;
  298. interrupts = <10 0x8>;
  299. interrupt-parent = <&ipic>;
  300. };
  301. crypto@30000 {
  302. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  303. "fsl,sec2.1", "fsl,sec2.0";
  304. reg = <0x30000 0x10000>;
  305. interrupts = <11 0x8>;
  306. interrupt-parent = <&ipic>;
  307. fsl,num-channels = <4>;
  308. fsl,channel-fifo-len = <24>;
  309. fsl,exec-units-mask = <0x9fe>;
  310. fsl,descriptor-types-mask = <0x3ab0ebf>;
  311. sleep = <&pmc 0x03000000>;
  312. };
  313. sata@18000 {
  314. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  315. reg = <0x18000 0x1000>;
  316. interrupts = <44 0x8>;
  317. interrupt-parent = <&ipic>;
  318. sleep = <&pmc 0x000000c0>;
  319. };
  320. sata@19000 {
  321. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  322. reg = <0x19000 0x1000>;
  323. interrupts = <45 0x8>;
  324. interrupt-parent = <&ipic>;
  325. sleep = <&pmc 0x00000030>;
  326. };
  327. sata@1a000 {
  328. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  329. reg = <0x1a000 0x1000>;
  330. interrupts = <46 0x8>;
  331. interrupt-parent = <&ipic>;
  332. sleep = <&pmc 0x0000000c>;
  333. };
  334. sata@1b000 {
  335. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  336. reg = <0x1b000 0x1000>;
  337. interrupts = <47 0x8>;
  338. interrupt-parent = <&ipic>;
  339. sleep = <&pmc 0x00000003>;
  340. };
  341. /* IPIC
  342. * interrupts cell = <intr #, sense>
  343. * sense values match linux IORESOURCE_IRQ_* defines:
  344. * sense == 8: Level, low assertion
  345. * sense == 2: Edge, high-to-low change
  346. */
  347. ipic: interrupt-controller@700 {
  348. compatible = "fsl,ipic";
  349. interrupt-controller;
  350. #address-cells = <0>;
  351. #interrupt-cells = <2>;
  352. reg = <0x700 0x100>;
  353. };
  354. pmc: power@b00 {
  355. compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
  356. reg = <0xb00 0x100 0xa00 0x100>;
  357. interrupts = <80 0x8>;
  358. interrupt-parent = <&ipic>;
  359. };
  360. };
  361. pci0: pci@e0008500 {
  362. interrupt-map-mask = <0xf800 0 0 7>;
  363. interrupt-map = <
  364. /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
  365. /* IDSEL AD14 IRQ6 inta */
  366. 0x7000 0x0 0x0 0x1 &ipic 22 0x8
  367. /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
  368. 0x7800 0x0 0x0 0x1 &ipic 21 0x8
  369. 0x7800 0x0 0x0 0x2 &ipic 22 0x8
  370. 0x7800 0x0 0x0 0x4 &ipic 23 0x8
  371. /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
  372. 0xE000 0x0 0x0 0x1 &ipic 23 0x8
  373. 0xE000 0x0 0x0 0x2 &ipic 21 0x8
  374. 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
  375. interrupt-parent = <&ipic>;
  376. interrupts = <66 0x8>;
  377. bus-range = <0x0 0x0>;
  378. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  379. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  380. 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
  381. sleep = <&pmc 0x00010000>;
  382. clock-frequency = <66666666>;
  383. #interrupt-cells = <1>;
  384. #size-cells = <2>;
  385. #address-cells = <3>;
  386. reg = <0xe0008500 0x100 /* internal registers */
  387. 0xe0008300 0x8>; /* config space access registers */
  388. compatible = "fsl,mpc8349-pci";
  389. device_type = "pci";
  390. };
  391. leds {
  392. compatible = "gpio-leds";
  393. pwr {
  394. gpios = <&mcu_pio 0 0>;
  395. default-state = "on";
  396. };
  397. hdd {
  398. gpios = <&mcu_pio 1 0>;
  399. linux,default-trigger = "disk-activity";
  400. };
  401. };
  402. };