mpc8349emitxgp.dts 5.7 KB

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  1. /*
  2. * MPC8349E-mITX-GP Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITXGP";
  14. compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8349@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>;
  41. };
  42. soc8349@e0000000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. compatible = "simple-bus";
  47. ranges = <0x0 0xe0000000 0x00100000>;
  48. reg = <0xe0000000 0x00000200>;
  49. bus-frequency = <0>; // from bootloader
  50. wdt@200 {
  51. device_type = "watchdog";
  52. compatible = "mpc83xx_wdt";
  53. reg = <0x200 0x100>;
  54. };
  55. i2c@3000 {
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. cell-index = <0>;
  59. compatible = "fsl-i2c";
  60. reg = <0x3000 0x100>;
  61. interrupts = <14 0x8>;
  62. interrupt-parent = <&ipic>;
  63. dfsrr;
  64. };
  65. i2c@3100 {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. cell-index = <1>;
  69. compatible = "fsl-i2c";
  70. reg = <0x3100 0x100>;
  71. interrupts = <15 0x8>;
  72. interrupt-parent = <&ipic>;
  73. dfsrr;
  74. rtc@68 {
  75. compatible = "dallas,ds1339";
  76. reg = <0x68>;
  77. interrupts = <18 0x8>;
  78. interrupt-parent = <&ipic>;
  79. };
  80. };
  81. spi@7000 {
  82. cell-index = <0>;
  83. compatible = "fsl,spi";
  84. reg = <0x7000 0x1000>;
  85. interrupts = <16 0x8>;
  86. interrupt-parent = <&ipic>;
  87. mode = "cpu";
  88. };
  89. dma@82a8 {
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  93. reg = <0x82a8 4>;
  94. ranges = <0 0x8100 0x1a8>;
  95. interrupt-parent = <&ipic>;
  96. interrupts = <71 8>;
  97. cell-index = <0>;
  98. dma-channel@0 {
  99. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  100. reg = <0 0x80>;
  101. cell-index = <0>;
  102. interrupt-parent = <&ipic>;
  103. interrupts = <71 8>;
  104. };
  105. dma-channel@80 {
  106. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  107. reg = <0x80 0x80>;
  108. cell-index = <1>;
  109. interrupt-parent = <&ipic>;
  110. interrupts = <71 8>;
  111. };
  112. dma-channel@100 {
  113. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  114. reg = <0x100 0x80>;
  115. cell-index = <2>;
  116. interrupt-parent = <&ipic>;
  117. interrupts = <71 8>;
  118. };
  119. dma-channel@180 {
  120. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  121. reg = <0x180 0x28>;
  122. cell-index = <3>;
  123. interrupt-parent = <&ipic>;
  124. interrupts = <71 8>;
  125. };
  126. };
  127. usb@23000 {
  128. compatible = "fsl-usb2-dr";
  129. reg = <0x23000 0x1000>;
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. interrupt-parent = <&ipic>;
  133. interrupts = <38 0x8>;
  134. dr_mode = "otg";
  135. phy_type = "ulpi";
  136. };
  137. enet0: ethernet@24000 {
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. cell-index = <0>;
  141. device_type = "network";
  142. model = "TSEC";
  143. compatible = "gianfar";
  144. reg = <0x24000 0x1000>;
  145. ranges = <0x0 0x24000 0x1000>;
  146. local-mac-address = [ 00 00 00 00 00 00 ];
  147. interrupts = <32 0x8 33 0x8 34 0x8>;
  148. interrupt-parent = <&ipic>;
  149. tbi-handle = <&tbi0>;
  150. phy-handle = <&phy1c>;
  151. linux,network-index = <0>;
  152. mdio@520 {
  153. #address-cells = <1>;
  154. #size-cells = <0>;
  155. compatible = "fsl,gianfar-mdio";
  156. reg = <0x520 0x20>;
  157. /* Vitesse 8201 */
  158. phy1c: ethernet-phy@1c {
  159. interrupt-parent = <&ipic>;
  160. interrupts = <18 0x8>;
  161. reg = <0x1c>;
  162. };
  163. tbi0: tbi-phy@11 {
  164. reg = <0x11>;
  165. device_type = "tbi-phy";
  166. };
  167. };
  168. };
  169. serial0: serial@4500 {
  170. cell-index = <0>;
  171. device_type = "serial";
  172. compatible = "fsl,ns16550", "ns16550";
  173. reg = <0x4500 0x100>;
  174. clock-frequency = <0>; // from bootloader
  175. interrupts = <9 0x8>;
  176. interrupt-parent = <&ipic>;
  177. };
  178. serial1: serial@4600 {
  179. cell-index = <1>;
  180. device_type = "serial";
  181. compatible = "fsl,ns16550", "ns16550";
  182. reg = <0x4600 0x100>;
  183. clock-frequency = <0>; // from bootloader
  184. interrupts = <10 0x8>;
  185. interrupt-parent = <&ipic>;
  186. };
  187. crypto@30000 {
  188. compatible = "fsl,sec2.0";
  189. reg = <0x30000 0x10000>;
  190. interrupts = <11 0x8>;
  191. interrupt-parent = <&ipic>;
  192. fsl,num-channels = <4>;
  193. fsl,channel-fifo-len = <24>;
  194. fsl,exec-units-mask = <0x7e>;
  195. fsl,descriptor-types-mask = <0x01010ebf>;
  196. };
  197. ipic: pic@700 {
  198. interrupt-controller;
  199. #address-cells = <0>;
  200. #interrupt-cells = <2>;
  201. reg = <0x700 0x100>;
  202. device_type = "ipic";
  203. };
  204. };
  205. pci0: pci@e0008600 {
  206. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  207. interrupt-map = <
  208. /* IDSEL 0x0F - PCI Slot */
  209. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  210. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  211. >;
  212. interrupt-parent = <&ipic>;
  213. interrupts = <67 0x8>;
  214. bus-range = <0x1 0x1>;
  215. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  216. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  217. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  218. clock-frequency = <66666666>;
  219. #interrupt-cells = <1>;
  220. #size-cells = <2>;
  221. #address-cells = <3>;
  222. reg = <0xe0008600 0x100 /* internal registers */
  223. 0xe0008380 0x8>; /* config space access registers */
  224. compatible = "fsl,mpc8349-pci";
  225. device_type = "pci";
  226. };
  227. };