kuroboxHG.dts 3.7 KB

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  1. /*
  2. * Device Tree Souce for Buffalo KuroboxHG
  3. *
  4. * Choose CONFIG_LINKSTATION to build a kernel for KuroboxHG, or use
  5. * the default configuration linkstation_defconfig.
  6. *
  7. * Based on sandpoint.dts
  8. *
  9. * 2006 (c) G. Liakhovetski <g.liakhovetski@gmx.de>
  10. * Copyright 2008 Freescale Semiconductor, Inc.
  11. *
  12. * This file is licensed under
  13. * the terms of the GNU General Public License version 2. This program
  14. * is licensed "as is" without any warranty of any kind, whether express
  15. * or implied.
  16. XXXX add flash parts, rtc, ??
  17. */
  18. /dts-v1/;
  19. / {
  20. model = "KuroboxHG";
  21. compatible = "linkstation";
  22. #address-cells = <1>;
  23. #size-cells = <1>;
  24. aliases {
  25. serial0 = &serial0;
  26. serial1 = &serial1;
  27. pci0 = &pci0;
  28. };
  29. cpus {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. PowerPC,603e { /* Really 8241 */
  33. device_type = "cpu";
  34. reg = <0x0>;
  35. clock-frequency = <266000000>; /* Fixed by bootloader */
  36. timebase-frequency = <32522240>; /* Fixed by bootloader */
  37. bus-frequency = <0>; /* Fixed by bootloader */
  38. /* Following required by dtc but not used */
  39. i-cache-size = <0x4000>;
  40. d-cache-size = <0x4000>;
  41. };
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0x0 0x8000000>;
  46. };
  47. soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. device_type = "soc";
  51. compatible = "mpc10x";
  52. store-gathering = <0>; /* 0 == off, !0 == on */
  53. reg = <0x80000000 0x100000>;
  54. ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
  55. 0xfc000000 0xfc000000 0x100000 /* EUMB */
  56. 0xfe000000 0xfe000000 0xc00000 /* pci i/o space */
  57. 0xfec00000 0xfec00000 0x300000 /* pci cfg regs */
  58. 0xfef00000 0xfef00000 0x100000>; /* pci iack */
  59. i2c@80003000 {
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. cell-index = <0>;
  63. compatible = "fsl-i2c";
  64. reg = <0x80003000 0x1000>;
  65. interrupts = <5 2>;
  66. interrupt-parent = <&mpic>;
  67. rtc@32 {
  68. compatible = "ricoh,rs5c372a";
  69. reg = <0x32>;
  70. };
  71. };
  72. serial0: serial@80004500 {
  73. cell-index = <0>;
  74. device_type = "serial";
  75. compatible = "fsl,ns16550", "ns16550";
  76. reg = <0x80004500 0x8>;
  77. clock-frequency = <130041000>;
  78. current-speed = <9600>;
  79. interrupts = <9 0>;
  80. interrupt-parent = <&mpic>;
  81. };
  82. serial1: serial@80004600 {
  83. cell-index = <1>;
  84. device_type = "serial";
  85. compatible = "fsl,ns16550", "ns16550";
  86. reg = <0x80004600 0x8>;
  87. clock-frequency = <130041000>;
  88. current-speed = <57600>;
  89. interrupts = <10 0>;
  90. interrupt-parent = <&mpic>;
  91. };
  92. mpic: interrupt-controller@80040000 {
  93. #interrupt-cells = <2>;
  94. #address-cells = <0>;
  95. device_type = "open-pic";
  96. compatible = "chrp,open-pic";
  97. interrupt-controller;
  98. reg = <0x80040000 0x40000>;
  99. };
  100. pci0: pci@fec00000 {
  101. #address-cells = <3>;
  102. #size-cells = <2>;
  103. #interrupt-cells = <1>;
  104. device_type = "pci";
  105. compatible = "mpc10x-pci";
  106. reg = <0xfec00000 0x400000>;
  107. ranges = <0x1000000 0x0 0x0 0xfe000000 0x0 0xc00000
  108. 0x2000000 0x0 0x80000000 0x80000000 0x0 0x70000000>;
  109. bus-range = <0 255>;
  110. clock-frequency = <133333333>;
  111. interrupt-parent = <&mpic>;
  112. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  113. interrupt-map = <
  114. /* IDSEL 11 - IRQ0 ETH */
  115. 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
  116. 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
  117. 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
  118. 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
  119. /* IDSEL 12 - IRQ1 IDE0 */
  120. 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
  121. 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
  122. 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
  123. 0x6000 0x0 0x0 0x4 &mpic 0x0 0x1
  124. /* IDSEL 14 - IRQ3 USB2.0 */
  125. 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
  126. 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1
  127. 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1
  128. 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
  129. >;
  130. };
  131. };
  132. };