p2041si-post.dtsi 11 KB

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  1. /*
  2. * P2041/P2040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &bman_fbpr {
  35. compatible = "fsl,bman-fbpr";
  36. alloc-ranges = <0 0 0x10 0>;
  37. };
  38. &qman_fqd {
  39. compatible = "fsl,qman-fqd";
  40. alloc-ranges = <0 0 0x10 0>;
  41. };
  42. &qman_pfdr {
  43. compatible = "fsl,qman-pfdr";
  44. alloc-ranges = <0 0 0x10 0>;
  45. };
  46. &lbc {
  47. compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
  48. interrupts = <25 2 0 0>;
  49. #address-cells = <2>;
  50. #size-cells = <1>;
  51. };
  52. /* controller at 0x200000 */
  53. &pci0 {
  54. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  55. device_type = "pci";
  56. #size-cells = <2>;
  57. #address-cells = <3>;
  58. bus-range = <0x0 0xff>;
  59. clock-frequency = <33333333>;
  60. interrupts = <16 2 1 15>;
  61. fsl,iommu-parent = <&pamu0>;
  62. fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
  63. pcie@0 {
  64. reg = <0 0 0 0 0>;
  65. #interrupt-cells = <1>;
  66. #size-cells = <2>;
  67. #address-cells = <3>;
  68. device_type = "pci";
  69. interrupts = <16 2 1 15>;
  70. interrupt-map-mask = <0xf800 0 0 7>;
  71. interrupt-map = <
  72. /* IDSEL 0x0 */
  73. 0000 0 0 1 &mpic 40 1 0 0
  74. 0000 0 0 2 &mpic 1 1 0 0
  75. 0000 0 0 3 &mpic 2 1 0 0
  76. 0000 0 0 4 &mpic 3 1 0 0
  77. >;
  78. };
  79. };
  80. /* controller at 0x201000 */
  81. &pci1 {
  82. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  83. device_type = "pci";
  84. #size-cells = <2>;
  85. #address-cells = <3>;
  86. bus-range = <0 0xff>;
  87. clock-frequency = <33333333>;
  88. interrupts = <16 2 1 14>;
  89. fsl,iommu-parent = <&pamu0>;
  90. fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
  91. pcie@0 {
  92. reg = <0 0 0 0 0>;
  93. #interrupt-cells = <1>;
  94. #size-cells = <2>;
  95. #address-cells = <3>;
  96. device_type = "pci";
  97. interrupts = <16 2 1 14>;
  98. interrupt-map-mask = <0xf800 0 0 7>;
  99. interrupt-map = <
  100. /* IDSEL 0x0 */
  101. 0000 0 0 1 &mpic 41 1 0 0
  102. 0000 0 0 2 &mpic 5 1 0 0
  103. 0000 0 0 3 &mpic 6 1 0 0
  104. 0000 0 0 4 &mpic 7 1 0 0
  105. >;
  106. };
  107. };
  108. /* controller at 0x202000 */
  109. &pci2 {
  110. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  111. device_type = "pci";
  112. #size-cells = <2>;
  113. #address-cells = <3>;
  114. bus-range = <0x0 0xff>;
  115. clock-frequency = <33333333>;
  116. interrupts = <16 2 1 13>;
  117. fsl,iommu-parent = <&pamu0>;
  118. fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
  119. pcie@0 {
  120. reg = <0 0 0 0 0>;
  121. #interrupt-cells = <1>;
  122. #size-cells = <2>;
  123. #address-cells = <3>;
  124. device_type = "pci";
  125. interrupts = <16 2 1 13>;
  126. interrupt-map-mask = <0xf800 0 0 7>;
  127. interrupt-map = <
  128. /* IDSEL 0x0 */
  129. 0000 0 0 1 &mpic 42 1 0 0
  130. 0000 0 0 2 &mpic 9 1 0 0
  131. 0000 0 0 3 &mpic 10 1 0 0
  132. 0000 0 0 4 &mpic 11 1 0 0
  133. >;
  134. };
  135. };
  136. &rio {
  137. compatible = "fsl,srio";
  138. interrupts = <16 2 1 11>;
  139. #address-cells = <2>;
  140. #size-cells = <2>;
  141. fsl,iommu-parent = <&pamu0>;
  142. ranges;
  143. port1 {
  144. #address-cells = <2>;
  145. #size-cells = <2>;
  146. cell-index = <1>;
  147. fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
  148. };
  149. port2 {
  150. #address-cells = <2>;
  151. #size-cells = <2>;
  152. cell-index = <2>;
  153. fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
  154. };
  155. };
  156. &dcsr {
  157. #address-cells = <1>;
  158. #size-cells = <1>;
  159. compatible = "fsl,dcsr", "simple-bus";
  160. dcsr-epu@0 {
  161. compatible = "fsl,p2041-dcsr-epu", "fsl,dcsr-epu";
  162. interrupts = <52 2 0 0
  163. 84 2 0 0
  164. 85 2 0 0>;
  165. reg = <0x0 0x1000>;
  166. };
  167. dcsr-npc {
  168. compatible = "fsl,dcsr-npc";
  169. reg = <0x1000 0x1000 0x1000000 0x8000>;
  170. };
  171. dcsr-nxc@2000 {
  172. compatible = "fsl,dcsr-nxc";
  173. reg = <0x2000 0x1000>;
  174. };
  175. dcsr-corenet {
  176. compatible = "fsl,dcsr-corenet";
  177. reg = <0x8000 0x1000 0xB0000 0x1000>;
  178. };
  179. dcsr-dpaa@9000 {
  180. compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
  181. reg = <0x9000 0x1000>;
  182. };
  183. dcsr-ocn@11000 {
  184. compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
  185. reg = <0x11000 0x1000>;
  186. };
  187. dcsr-ddr@12000 {
  188. compatible = "fsl,dcsr-ddr";
  189. dev-handle = <&ddr1>;
  190. reg = <0x12000 0x1000>;
  191. };
  192. dcsr-nal@18000 {
  193. compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
  194. reg = <0x18000 0x1000>;
  195. };
  196. dcsr-rcpm@22000 {
  197. compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
  198. reg = <0x22000 0x1000>;
  199. };
  200. dcsr-cpu-sb-proxy@40000 {
  201. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  202. cpu-handle = <&cpu0>;
  203. reg = <0x40000 0x1000>;
  204. };
  205. dcsr-cpu-sb-proxy@41000 {
  206. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  207. cpu-handle = <&cpu1>;
  208. reg = <0x41000 0x1000>;
  209. };
  210. dcsr-cpu-sb-proxy@42000 {
  211. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  212. cpu-handle = <&cpu2>;
  213. reg = <0x42000 0x1000>;
  214. };
  215. dcsr-cpu-sb-proxy@43000 {
  216. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  217. cpu-handle = <&cpu3>;
  218. reg = <0x43000 0x1000>;
  219. };
  220. };
  221. /include/ "qoriq-bman1-portals.dtsi"
  222. /include/ "qoriq-qman1-portals.dtsi"
  223. &soc {
  224. #address-cells = <1>;
  225. #size-cells = <1>;
  226. device_type = "soc";
  227. compatible = "simple-bus";
  228. soc-sram-error {
  229. compatible = "fsl,soc-sram-error";
  230. interrupts = <16 2 1 29>;
  231. };
  232. corenet-law@0 {
  233. compatible = "fsl,corenet-law";
  234. reg = <0x0 0x1000>;
  235. fsl,num-laws = <32>;
  236. };
  237. ddr1: memory-controller@8000 {
  238. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  239. reg = <0x8000 0x1000>;
  240. interrupts = <16 2 1 23>;
  241. };
  242. cpc: l3-cache-controller@10000 {
  243. compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  244. reg = <0x10000 0x1000>;
  245. interrupts = <16 2 1 27>;
  246. };
  247. corenet-cf@18000 {
  248. compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
  249. reg = <0x18000 0x1000>;
  250. interrupts = <16 2 1 31>;
  251. fsl,ccf-num-csdids = <32>;
  252. fsl,ccf-num-snoopids = <32>;
  253. };
  254. iommu@20000 {
  255. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  256. reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
  257. ranges = <0 0x20000 0x4000>;
  258. #address-cells = <1>;
  259. #size-cells = <1>;
  260. interrupts = <
  261. 24 2 0 0
  262. 16 2 1 30>;
  263. fsl,portid-mapping = <0x0f000000>;
  264. pamu0: pamu@0 {
  265. reg = <0 0x1000>;
  266. fsl,primary-cache-geometry = <32 1>;
  267. fsl,secondary-cache-geometry = <128 2>;
  268. };
  269. pamu1: pamu@1000 {
  270. reg = <0x1000 0x1000>;
  271. fsl,primary-cache-geometry = <32 1>;
  272. fsl,secondary-cache-geometry = <128 2>;
  273. };
  274. pamu2: pamu@2000 {
  275. reg = <0x2000 0x1000>;
  276. fsl,primary-cache-geometry = <32 1>;
  277. fsl,secondary-cache-geometry = <128 2>;
  278. };
  279. pamu3: pamu@3000 {
  280. reg = <0x3000 0x1000>;
  281. fsl,primary-cache-geometry = <32 1>;
  282. fsl,secondary-cache-geometry = <128 2>;
  283. };
  284. };
  285. /include/ "qoriq-mpic.dtsi"
  286. guts: global-utilities@e0000 {
  287. compatible = "fsl,qoriq-device-config-1.0";
  288. reg = <0xe0000 0xe00>;
  289. fsl,has-rstcr;
  290. #sleep-cells = <1>;
  291. fsl,liodn-bits = <12>;
  292. };
  293. pins: global-utilities@e0e00 {
  294. compatible = "fsl,qoriq-pin-control-1.0";
  295. reg = <0xe0e00 0x200>;
  296. #sleep-cells = <2>;
  297. };
  298. /include/ "qoriq-clockgen1.dtsi"
  299. global-utilities@e1000 {
  300. compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
  301. mux2: mux2@40 {
  302. #clock-cells = <0>;
  303. reg = <0x40 0x4>;
  304. compatible = "fsl,qoriq-core-mux-1.0";
  305. clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
  306. clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
  307. clock-output-names = "cmux2";
  308. };
  309. mux3: mux3@60 {
  310. #clock-cells = <0>;
  311. reg = <0x60 0x4>;
  312. compatible = "fsl,qoriq-core-mux-1.0";
  313. clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
  314. clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
  315. clock-output-names = "cmux3";
  316. };
  317. };
  318. rcpm: global-utilities@e2000 {
  319. compatible = "fsl,qoriq-rcpm-1.0";
  320. reg = <0xe2000 0x1000>;
  321. #sleep-cells = <1>;
  322. };
  323. sfp: sfp@e8000 {
  324. compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
  325. reg = <0xe8000 0x1000>;
  326. };
  327. serdes: serdes@ea000 {
  328. compatible = "fsl,p2041-serdes";
  329. reg = <0xea000 0x1000>;
  330. };
  331. /include/ "qoriq-dma-0.dtsi"
  332. dma@100300 {
  333. fsl,iommu-parent = <&pamu0>;
  334. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  335. };
  336. /include/ "qoriq-dma-1.dtsi"
  337. dma@101300 {
  338. fsl,iommu-parent = <&pamu0>;
  339. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  340. };
  341. /include/ "qoriq-espi-0.dtsi"
  342. spi@110000 {
  343. fsl,espi-num-chipselects = <4>;
  344. };
  345. /include/ "qoriq-esdhc-0.dtsi"
  346. sdhc@114000 {
  347. compatible = "fsl,p2041-esdhc", "fsl,esdhc";
  348. fsl,iommu-parent = <&pamu1>;
  349. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  350. sdhci,auto-cmd12;
  351. };
  352. /include/ "qoriq-i2c-0.dtsi"
  353. /include/ "qoriq-i2c-1.dtsi"
  354. /include/ "qoriq-duart-0.dtsi"
  355. /include/ "qoriq-duart-1.dtsi"
  356. /include/ "qoriq-gpio-0.dtsi"
  357. /include/ "qoriq-usb2-mph-0.dtsi"
  358. usb0: usb@210000 {
  359. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  360. phy_type = "utmi";
  361. fsl,iommu-parent = <&pamu1>;
  362. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  363. port0;
  364. };
  365. /include/ "qoriq-usb2-dr-0.dtsi"
  366. usb1: usb@211000 {
  367. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  368. fsl,iommu-parent = <&pamu1>;
  369. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  370. dr_mode = "host";
  371. phy_type = "utmi";
  372. };
  373. /include/ "qoriq-sata2-0.dtsi"
  374. sata@220000 {
  375. fsl,iommu-parent = <&pamu1>;
  376. fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
  377. };
  378. /include/ "qoriq-sata2-1.dtsi"
  379. sata@221000 {
  380. fsl,iommu-parent = <&pamu1>;
  381. fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
  382. };
  383. /include/ "qoriq-sec4.2-0.dtsi"
  384. crypto: crypto@300000 {
  385. fsl,iommu-parent = <&pamu1>;
  386. };
  387. /include/ "qoriq-qman1.dtsi"
  388. /include/ "qoriq-bman1.dtsi"
  389. /include/ "qoriq-fman-0.dtsi"
  390. /include/ "qoriq-fman-0-1g-0.dtsi"
  391. /include/ "qoriq-fman-0-1g-1.dtsi"
  392. /include/ "qoriq-fman-0-1g-2.dtsi"
  393. /include/ "qoriq-fman-0-1g-3.dtsi"
  394. /include/ "qoriq-fman-0-1g-4.dtsi"
  395. /include/ "qoriq-fman-0-10g-0.dtsi"
  396. fman@400000 {
  397. enet0: ethernet@e0000 {
  398. };
  399. enet1: ethernet@e2000 {
  400. };
  401. enet2: ethernet@e4000 {
  402. };
  403. enet3: ethernet@e6000 {
  404. };
  405. enet4: ethernet@e8000 {
  406. };
  407. enet5: ethernet@f0000 {
  408. };
  409. };
  410. };