mpc8536si-post.dtsi 6.4 KB

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  1. /*
  2. * MPC8536 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
  38. interrupts = <19 2 0 0>;
  39. };
  40. /* controller at 0x8000 */
  41. &pci0 {
  42. compatible = "fsl,mpc8540-pci";
  43. device_type = "pci";
  44. interrupts = <24 0x2 0 0>;
  45. bus-range = <0 0xff>;
  46. #interrupt-cells = <1>;
  47. #size-cells = <2>;
  48. #address-cells = <3>;
  49. };
  50. /* controller at 0x9000 */
  51. &pci1 {
  52. compatible = "fsl,mpc8548-pcie";
  53. device_type = "pci";
  54. #size-cells = <2>;
  55. #address-cells = <3>;
  56. bus-range = <0 255>;
  57. clock-frequency = <33333333>;
  58. interrupts = <25 2 0 0>;
  59. pcie@0 {
  60. reg = <0 0 0 0 0>;
  61. #interrupt-cells = <1>;
  62. #size-cells = <2>;
  63. #address-cells = <3>;
  64. device_type = "pci";
  65. interrupts = <25 2 0 0>;
  66. interrupt-map-mask = <0xf800 0 0 7>;
  67. interrupt-map = <
  68. /* IDSEL 0x0 */
  69. 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  70. 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  71. 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  72. 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  73. >;
  74. };
  75. };
  76. /* controller at 0xa000 */
  77. &pci2 {
  78. compatible = "fsl,mpc8548-pcie";
  79. device_type = "pci";
  80. #size-cells = <2>;
  81. #address-cells = <3>;
  82. bus-range = <0 255>;
  83. clock-frequency = <33333333>;
  84. interrupts = <26 2 0 0>;
  85. pcie@0 {
  86. reg = <0 0 0 0 0>;
  87. #interrupt-cells = <1>;
  88. #size-cells = <2>;
  89. #address-cells = <3>;
  90. device_type = "pci";
  91. interrupts = <26 2 0 0>;
  92. interrupt-map-mask = <0xf800 0 0 7>;
  93. interrupt-map = <
  94. /* IDSEL 0x0 */
  95. 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  96. 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  97. 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  98. 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  99. >;
  100. };
  101. };
  102. /* controller at 0xb000 */
  103. &pci3 {
  104. compatible = "fsl,mpc8548-pcie";
  105. device_type = "pci";
  106. #size-cells = <2>;
  107. #address-cells = <3>;
  108. bus-range = <0 255>;
  109. clock-frequency = <33333333>;
  110. interrupts = <27 2 0 0>;
  111. pcie@0 {
  112. reg = <0 0 0 0 0>;
  113. #interrupt-cells = <1>;
  114. #size-cells = <2>;
  115. #address-cells = <3>;
  116. device_type = "pci";
  117. interrupts = <27 2 0 0>;
  118. interrupt-map-mask = <0xf800 0 0 7>;
  119. interrupt-map = <
  120. /* IDSEL 0x0 */
  121. 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
  122. 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
  123. 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
  124. 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
  125. >;
  126. };
  127. };
  128. &soc {
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. device_type = "soc";
  132. compatible = "fsl,mpc8536-immr", "simple-bus";
  133. bus-frequency = <0>; // Filled out by uboot.
  134. ecm-law@0 {
  135. compatible = "fsl,ecm-law";
  136. reg = <0x0 0x1000>;
  137. fsl,num-laws = <12>;
  138. };
  139. ecm@1000 {
  140. compatible = "fsl,mpc8536-ecm", "fsl,ecm";
  141. reg = <0x1000 0x1000>;
  142. interrupts = <17 2 0 0>;
  143. };
  144. memory-controller@2000 {
  145. compatible = "fsl,mpc8536-memory-controller";
  146. reg = <0x2000 0x1000>;
  147. interrupts = <18 2 0 0>;
  148. };
  149. /include/ "pq3-i2c-0.dtsi"
  150. /include/ "pq3-i2c-1.dtsi"
  151. /include/ "pq3-duart-0.dtsi"
  152. /include/ "pq3-espi-0.dtsi"
  153. spi@7000 {
  154. fsl,espi-num-chipselects = <4>;
  155. };
  156. /include/ "pq3-gpio-0.dtsi"
  157. /* mark compat w/8572 to get some erratum treatment */
  158. gpio-controller@f000 {
  159. compatible = "fsl,mpc8572-gpio";
  160. };
  161. sata@18000 {
  162. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  163. reg = <0x18000 0x1000>;
  164. cell-index = <1>;
  165. interrupts = <74 0x2 0 0>;
  166. };
  167. sata@19000 {
  168. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  169. reg = <0x19000 0x1000>;
  170. cell-index = <2>;
  171. interrupts = <41 0x2 0 0>;
  172. };
  173. L2: l2-cache-controller@20000 {
  174. compatible = "fsl,mpc8536-l2-cache-controller";
  175. reg = <0x20000 0x1000>;
  176. cache-line-size = <32>; // 32 bytes
  177. cache-size = <0x80000>; // L2, 512K
  178. interrupts = <16 2 0 0>;
  179. };
  180. /include/ "pq3-dma-0.dtsi"
  181. /include/ "pq3-etsec1-0.dtsi"
  182. /include/ "pq3-etsec1-timer-0.dtsi"
  183. usb@22000 {
  184. compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  185. reg = <0x22000 0x1000>;
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. interrupts = <28 0x2 0 0>;
  189. };
  190. usb@23000 {
  191. compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  192. reg = <0x23000 0x1000>;
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. interrupts = <46 0x2 0 0>;
  196. };
  197. ptp_clock@24e00 {
  198. interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
  199. };
  200. /include/ "pq3-etsec1-2.dtsi"
  201. ethernet@26000 {
  202. cell-index = <1>;
  203. };
  204. usb@2b000 {
  205. compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
  206. reg = <0x2b000 0x1000>;
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. interrupts = <60 0x2 0 0>;
  210. };
  211. /include/ "pq3-esdhc-0.dtsi"
  212. sdhc@2e000 {
  213. compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
  214. };
  215. /include/ "pq3-sec3.0-0.dtsi"
  216. /include/ "pq3-mpic.dtsi"
  217. /include/ "pq3-mpic-timer-B.dtsi"
  218. global-utilities@e0000 {
  219. compatible = "fsl,mpc8536-guts";
  220. reg = <0xe0000 0x1000>;
  221. fsl,has-rstcr;
  222. };
  223. };