ebony.dts 8.2 KB

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  1. /*
  2. * Device Tree Source for IBM Ebony
  3. *
  4. * Copyright (c) 2006, 2007 IBM Corp.
  5. * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
  6. *
  7. * FIXME: Draft only!
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without
  11. * any warranty of any kind, whether express or implied.
  12. */
  13. /dts-v1/;
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "ibm,ebony";
  18. compatible = "ibm,ebony";
  19. dcr-parent = <&{/cpus/cpu@0}>;
  20. aliases {
  21. ethernet0 = &EMAC0;
  22. ethernet1 = &EMAC1;
  23. serial0 = &UART0;
  24. serial1 = &UART1;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. device_type = "cpu";
  31. model = "PowerPC,440GP";
  32. reg = <0x00000000>;
  33. clock-frequency = <0>; // Filled in by zImage
  34. timebase-frequency = <0>; // Filled in by zImage
  35. i-cache-line-size = <32>;
  36. d-cache-line-size = <32>;
  37. i-cache-size = <32768>; /* 32 kB */
  38. d-cache-size = <32768>; /* 32 kB */
  39. dcr-controller;
  40. dcr-access-method = "native";
  41. };
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
  46. };
  47. UIC0: interrupt-controller0 {
  48. compatible = "ibm,uic-440gp", "ibm,uic";
  49. interrupt-controller;
  50. cell-index = <0>;
  51. dcr-reg = <0x0c0 0x009>;
  52. #address-cells = <0>;
  53. #size-cells = <0>;
  54. #interrupt-cells = <2>;
  55. };
  56. UIC1: interrupt-controller1 {
  57. compatible = "ibm,uic-440gp", "ibm,uic";
  58. interrupt-controller;
  59. cell-index = <1>;
  60. dcr-reg = <0x0d0 0x009>;
  61. #address-cells = <0>;
  62. #size-cells = <0>;
  63. #interrupt-cells = <2>;
  64. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  65. interrupt-parent = <&UIC0>;
  66. };
  67. CPC0: cpc {
  68. compatible = "ibm,cpc-440gp";
  69. dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
  70. // FIXME: anything else?
  71. };
  72. plb {
  73. compatible = "ibm,plb-440gp", "ibm,plb4";
  74. #address-cells = <2>;
  75. #size-cells = <1>;
  76. ranges;
  77. clock-frequency = <0>; // Filled in by zImage
  78. SDRAM0: memory-controller {
  79. compatible = "ibm,sdram-440gp";
  80. dcr-reg = <0x010 0x002>;
  81. // FIXME: anything else?
  82. };
  83. SRAM0: sram {
  84. compatible = "ibm,sram-440gp";
  85. dcr-reg = <0x020 0x008 0x00a 0x001>;
  86. };
  87. DMA0: dma {
  88. // FIXME: ???
  89. compatible = "ibm,dma-440gp";
  90. dcr-reg = <0x100 0x027>;
  91. };
  92. MAL0: mcmal {
  93. compatible = "ibm,mcmal-440gp", "ibm,mcmal";
  94. dcr-reg = <0x180 0x062>;
  95. num-tx-chans = <4>;
  96. num-rx-chans = <4>;
  97. interrupt-parent = <&MAL0>;
  98. interrupts = <0x0 0x1 0x2 0x3 0x4>;
  99. #interrupt-cells = <1>;
  100. #address-cells = <0>;
  101. #size-cells = <0>;
  102. interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
  103. /*RXEOB*/ 0x1 &UIC0 0xb 0x4
  104. /*SERR*/ 0x2 &UIC1 0x0 0x4
  105. /*TXDE*/ 0x3 &UIC1 0x1 0x4
  106. /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
  107. interrupt-map-mask = <0xffffffff>;
  108. };
  109. POB0: opb {
  110. compatible = "ibm,opb-440gp", "ibm,opb";
  111. #address-cells = <1>;
  112. #size-cells = <1>;
  113. /* Wish there was a nicer way of specifying a full 32-bit
  114. range */
  115. ranges = <0x00000000 0x00000001 0x00000000 0x80000000
  116. 0x80000000 0x00000001 0x80000000 0x80000000>;
  117. dcr-reg = <0x090 0x00b>;
  118. interrupt-parent = <&UIC1>;
  119. interrupts = <0x7 0x4>;
  120. clock-frequency = <0>; // Filled in by zImage
  121. EBC0: ebc {
  122. compatible = "ibm,ebc-440gp", "ibm,ebc";
  123. dcr-reg = <0x012 0x002>;
  124. #address-cells = <2>;
  125. #size-cells = <1>;
  126. clock-frequency = <0>; // Filled in by zImage
  127. // ranges property is supplied by zImage
  128. // based on firmware's configuration of the
  129. // EBC bridge
  130. interrupts = <0x5 0x4>;
  131. interrupt-parent = <&UIC1>;
  132. small-flash@0,80000 {
  133. compatible = "jedec-flash";
  134. bank-width = <1>;
  135. reg = <0x00000000 0x00080000 0x00080000>;
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. partition@0 {
  139. label = "OpenBIOS";
  140. reg = <0x00000000 0x00080000>;
  141. read-only;
  142. };
  143. };
  144. nvram@1,0 {
  145. /* NVRAM & RTC */
  146. compatible = "ds1743-nvram";
  147. #bytes = <0x2000>;
  148. reg = <0x00000001 0x00000000 0x00002000>;
  149. };
  150. large-flash@2,0 {
  151. compatible = "jedec-flash";
  152. bank-width = <1>;
  153. reg = <0x00000002 0x00000000 0x00400000>;
  154. #address-cells = <1>;
  155. #size-cells = <1>;
  156. partition@0 {
  157. label = "fs";
  158. reg = <0x00000000 0x00380000>;
  159. };
  160. partition@380000 {
  161. label = "firmware";
  162. reg = <0x00380000 0x00080000>;
  163. };
  164. };
  165. ir@3,0 {
  166. reg = <0x00000003 0x00000000 0x00000010>;
  167. };
  168. fpga@7,0 {
  169. compatible = "Ebony-FPGA";
  170. reg = <0x00000007 0x00000000 0x00000010>;
  171. virtual-reg = <0xe8300000>;
  172. };
  173. };
  174. UART0: serial@40000200 {
  175. device_type = "serial";
  176. compatible = "ns16550";
  177. reg = <0x40000200 0x00000008>;
  178. virtual-reg = <0xe0000200>;
  179. clock-frequency = <11059200>;
  180. current-speed = <9600>;
  181. interrupt-parent = <&UIC0>;
  182. interrupts = <0x0 0x4>;
  183. };
  184. UART1: serial@40000300 {
  185. device_type = "serial";
  186. compatible = "ns16550";
  187. reg = <0x40000300 0x00000008>;
  188. virtual-reg = <0xe0000300>;
  189. clock-frequency = <11059200>;
  190. current-speed = <9600>;
  191. interrupt-parent = <&UIC0>;
  192. interrupts = <0x1 0x4>;
  193. };
  194. IIC0: i2c@40000400 {
  195. /* FIXME */
  196. compatible = "ibm,iic-440gp", "ibm,iic";
  197. reg = <0x40000400 0x00000014>;
  198. interrupt-parent = <&UIC0>;
  199. interrupts = <0x2 0x4>;
  200. };
  201. IIC1: i2c@40000500 {
  202. /* FIXME */
  203. compatible = "ibm,iic-440gp", "ibm,iic";
  204. reg = <0x40000500 0x00000014>;
  205. interrupt-parent = <&UIC0>;
  206. interrupts = <0x3 0x4>;
  207. };
  208. GPIO0: gpio@40000700 {
  209. /* FIXME */
  210. compatible = "ibm,gpio-440gp";
  211. reg = <0x40000700 0x00000020>;
  212. };
  213. ZMII0: emac-zmii@40000780 {
  214. compatible = "ibm,zmii-440gp", "ibm,zmii";
  215. reg = <0x40000780 0x0000000c>;
  216. };
  217. EMAC0: ethernet@40000800 {
  218. device_type = "network";
  219. compatible = "ibm,emac-440gp", "ibm,emac";
  220. interrupt-parent = <&UIC1>;
  221. interrupts = <0x1c 0x4 0x1d 0x4>;
  222. reg = <0x40000800 0x00000070>;
  223. local-mac-address = [000000000000]; // Filled in by zImage
  224. mal-device = <&MAL0>;
  225. mal-tx-channel = <0 1>;
  226. mal-rx-channel = <0>;
  227. cell-index = <0>;
  228. max-frame-size = <1500>;
  229. rx-fifo-size = <4096>;
  230. tx-fifo-size = <2048>;
  231. phy-mode = "rmii";
  232. phy-map = <0x00000001>;
  233. zmii-device = <&ZMII0>;
  234. zmii-channel = <0>;
  235. };
  236. EMAC1: ethernet@40000900 {
  237. device_type = "network";
  238. compatible = "ibm,emac-440gp", "ibm,emac";
  239. interrupt-parent = <&UIC1>;
  240. interrupts = <0x1e 0x4 0x1f 0x4>;
  241. reg = <0x40000900 0x00000070>;
  242. local-mac-address = [000000000000]; // Filled in by zImage
  243. mal-device = <&MAL0>;
  244. mal-tx-channel = <2 3>;
  245. mal-rx-channel = <1>;
  246. cell-index = <1>;
  247. max-frame-size = <1500>;
  248. rx-fifo-size = <4096>;
  249. tx-fifo-size = <2048>;
  250. phy-mode = "rmii";
  251. phy-map = <0x00000001>;
  252. zmii-device = <&ZMII0>;
  253. zmii-channel = <1>;
  254. };
  255. GPT0: gpt@40000a00 {
  256. /* FIXME */
  257. reg = <0x40000a00 0x000000d4>;
  258. interrupt-parent = <&UIC0>;
  259. interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
  260. };
  261. };
  262. PCIX0: pci@20ec00000 {
  263. device_type = "pci";
  264. #interrupt-cells = <1>;
  265. #size-cells = <2>;
  266. #address-cells = <3>;
  267. compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
  268. primary;
  269. reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
  270. 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
  271. 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
  272. 0x00000002 0x0ec80000 0x000000f0 /* Internal registers */
  273. 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
  274. /* Outbound ranges, one memory and one IO,
  275. * later cannot be changed
  276. */
  277. ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
  278. 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
  279. /* Inbound 2GB range starting at 0 */
  280. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  281. /* Ebony has all 4 IRQ pins tied together per slot */
  282. interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
  283. interrupt-map = <
  284. /* IDSEL 1 */
  285. 0x800 0x0 0x0 0x0 &UIC0 0x17 0x8
  286. /* IDSEL 2 */
  287. 0x1000 0x0 0x0 0x0 &UIC0 0x18 0x8
  288. /* IDSEL 3 */
  289. 0x1800 0x0 0x0 0x0 &UIC0 0x19 0x8
  290. /* IDSEL 4 */
  291. 0x2000 0x0 0x0 0x0 &UIC0 0x1a 0x8
  292. >;
  293. };
  294. };
  295. chosen {
  296. linux,stdout-path = "/plb/opb/serial@40000200";
  297. };
  298. };