arches.dts 9.1 KB

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  1. /*
  2. * Device Tree Source for AMCC Arches (dual 460GT board)
  3. *
  4. * (C) Copyright 2008 Applied Micro Circuits Corporation
  5. * Victor Gallardo <vgallardo@amcc.com>
  6. * Adam Graham <agraham@amcc.com>
  7. *
  8. * Based on the glacier.dts file
  9. * Stefan Roese <sr@denx.de>
  10. * Copyright 2008 DENX Software Engineering
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. /dts-v1/;
  31. / {
  32. #address-cells = <2>;
  33. #size-cells = <1>;
  34. model = "amcc,arches";
  35. compatible = "amcc,arches";
  36. dcr-parent = <&{/cpus/cpu@0}>;
  37. aliases {
  38. ethernet0 = &EMAC0;
  39. ethernet1 = &EMAC1;
  40. ethernet2 = &EMAC2;
  41. serial0 = &UART0;
  42. };
  43. cpus {
  44. #address-cells = <1>;
  45. #size-cells = <0>;
  46. cpu@0 {
  47. device_type = "cpu";
  48. model = "PowerPC,460GT";
  49. reg = <0x00000000>;
  50. clock-frequency = <0>; /* Filled in by U-Boot */
  51. timebase-frequency = <0>; /* Filled in by U-Boot */
  52. i-cache-line-size = <32>;
  53. d-cache-line-size = <32>;
  54. i-cache-size = <32768>;
  55. d-cache-size = <32768>;
  56. dcr-controller;
  57. dcr-access-method = "native";
  58. next-level-cache = <&L2C0>;
  59. };
  60. };
  61. memory {
  62. device_type = "memory";
  63. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  64. };
  65. UIC0: interrupt-controller0 {
  66. compatible = "ibm,uic-460gt","ibm,uic";
  67. interrupt-controller;
  68. cell-index = <0>;
  69. dcr-reg = <0x0c0 0x009>;
  70. #address-cells = <0>;
  71. #size-cells = <0>;
  72. #interrupt-cells = <2>;
  73. };
  74. UIC1: interrupt-controller1 {
  75. compatible = "ibm,uic-460gt","ibm,uic";
  76. interrupt-controller;
  77. cell-index = <1>;
  78. dcr-reg = <0x0d0 0x009>;
  79. #address-cells = <0>;
  80. #size-cells = <0>;
  81. #interrupt-cells = <2>;
  82. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  83. interrupt-parent = <&UIC0>;
  84. };
  85. UIC2: interrupt-controller2 {
  86. compatible = "ibm,uic-460gt","ibm,uic";
  87. interrupt-controller;
  88. cell-index = <2>;
  89. dcr-reg = <0x0e0 0x009>;
  90. #address-cells = <0>;
  91. #size-cells = <0>;
  92. #interrupt-cells = <2>;
  93. interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
  94. interrupt-parent = <&UIC0>;
  95. };
  96. UIC3: interrupt-controller3 {
  97. compatible = "ibm,uic-460gt","ibm,uic";
  98. interrupt-controller;
  99. cell-index = <3>;
  100. dcr-reg = <0x0f0 0x009>;
  101. #address-cells = <0>;
  102. #size-cells = <0>;
  103. #interrupt-cells = <2>;
  104. interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
  105. interrupt-parent = <&UIC0>;
  106. };
  107. SDR0: sdr {
  108. compatible = "ibm,sdr-460gt";
  109. dcr-reg = <0x00e 0x002>;
  110. };
  111. CPR0: cpr {
  112. compatible = "ibm,cpr-460gt";
  113. dcr-reg = <0x00c 0x002>;
  114. };
  115. L2C0: l2c {
  116. compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
  117. dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
  118. 0x030 0x008>; /* L2 cache DCR's */
  119. cache-line-size = <32>; /* 32 bytes */
  120. cache-size = <262144>; /* L2, 256K */
  121. interrupt-parent = <&UIC1>;
  122. interrupts = <11 1>;
  123. };
  124. plb {
  125. compatible = "ibm,plb-460gt", "ibm,plb4";
  126. #address-cells = <2>;
  127. #size-cells = <1>;
  128. ranges;
  129. clock-frequency = <0>; /* Filled in by U-Boot */
  130. SDRAM0: sdram {
  131. compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
  132. dcr-reg = <0x010 0x002>;
  133. };
  134. CRYPTO: crypto@180000 {
  135. compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
  136. reg = <4 0x00180000 0x80400>;
  137. interrupt-parent = <&UIC0>;
  138. interrupts = <0x1d 0x4>;
  139. };
  140. MAL0: mcmal {
  141. compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
  142. dcr-reg = <0x180 0x062>;
  143. num-tx-chans = <3>;
  144. num-rx-chans = <24>;
  145. #address-cells = <0>;
  146. #size-cells = <0>;
  147. interrupt-parent = <&UIC2>;
  148. interrupts = < /*TXEOB*/ 0x6 0x4
  149. /*RXEOB*/ 0x7 0x4
  150. /*SERR*/ 0x3 0x4
  151. /*TXDE*/ 0x4 0x4
  152. /*RXDE*/ 0x5 0x4>;
  153. desc-base-addr-high = <0x8>;
  154. };
  155. POB0: opb {
  156. compatible = "ibm,opb-460gt", "ibm,opb";
  157. #address-cells = <1>;
  158. #size-cells = <1>;
  159. ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
  160. clock-frequency = <0>; /* Filled in by U-Boot */
  161. EBC0: ebc {
  162. compatible = "ibm,ebc-460gt", "ibm,ebc";
  163. dcr-reg = <0x012 0x002>;
  164. #address-cells = <2>;
  165. #size-cells = <1>;
  166. clock-frequency = <0>; /* Filled in by U-Boot */
  167. /* ranges property is supplied by U-Boot */
  168. interrupts = <0x6 0x4>;
  169. interrupt-parent = <&UIC1>;
  170. nor_flash@0,0 {
  171. compatible = "amd,s29gl256n", "cfi-flash";
  172. bank-width = <2>;
  173. reg = <0x00000000 0x00000000 0x02000000>;
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. partition@0 {
  177. label = "kernel";
  178. reg = <0x00000000 0x001e0000>;
  179. };
  180. partition@1e0000 {
  181. label = "dtb";
  182. reg = <0x001e0000 0x00020000>;
  183. };
  184. partition@200000 {
  185. label = "root";
  186. reg = <0x00200000 0x00200000>;
  187. };
  188. partition@400000 {
  189. label = "user";
  190. reg = <0x00400000 0x01b60000>;
  191. };
  192. partition@1f60000 {
  193. label = "env";
  194. reg = <0x01f60000 0x00040000>;
  195. };
  196. partition@1fa0000 {
  197. label = "u-boot";
  198. reg = <0x01fa0000 0x00060000>;
  199. };
  200. };
  201. };
  202. UART0: serial@ef600300 {
  203. device_type = "serial";
  204. compatible = "ns16550";
  205. reg = <0xef600300 0x00000008>;
  206. virtual-reg = <0xef600300>;
  207. clock-frequency = <0>; /* Filled in by U-Boot */
  208. current-speed = <0>; /* Filled in by U-Boot */
  209. interrupt-parent = <&UIC1>;
  210. interrupts = <0x1 0x4>;
  211. };
  212. IIC0: i2c@ef600700 {
  213. compatible = "ibm,iic-460gt", "ibm,iic";
  214. reg = <0xef600700 0x00000014>;
  215. interrupt-parent = <&UIC0>;
  216. interrupts = <0x2 0x4>;
  217. #address-cells = <1>;
  218. #size-cells = <0>;
  219. sttm@4a {
  220. compatible = "ad,ad7414";
  221. reg = <0x4a>;
  222. interrupt-parent = <&UIC1>;
  223. interrupts = <0x0 0x8>;
  224. };
  225. };
  226. IIC1: i2c@ef600800 {
  227. compatible = "ibm,iic-460gt", "ibm,iic";
  228. reg = <0xef600800 0x00000014>;
  229. interrupt-parent = <&UIC0>;
  230. interrupts = <0x3 0x4>;
  231. };
  232. TAH0: emac-tah@ef601350 {
  233. compatible = "ibm,tah-460gt", "ibm,tah";
  234. reg = <0xef601350 0x00000030>;
  235. };
  236. TAH1: emac-tah@ef601450 {
  237. compatible = "ibm,tah-460gt", "ibm,tah";
  238. reg = <0xef601450 0x00000030>;
  239. };
  240. EMAC0: ethernet@ef600e00 {
  241. device_type = "network";
  242. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  243. interrupt-parent = <&EMAC0>;
  244. interrupts = <0x0 0x1>;
  245. #interrupt-cells = <1>;
  246. #address-cells = <0>;
  247. #size-cells = <0>;
  248. interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
  249. /*Wake*/ 0x1 &UIC2 0x14 0x4>;
  250. reg = <0xef600e00 0x000000c4>;
  251. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  252. mal-device = <&MAL0>;
  253. mal-tx-channel = <0>;
  254. mal-rx-channel = <0>;
  255. cell-index = <0>;
  256. max-frame-size = <9000>;
  257. rx-fifo-size = <4096>;
  258. tx-fifo-size = <2048>;
  259. rx-fifo-size-gige = <16384>;
  260. phy-mode = "sgmii";
  261. phy-map = <0xffffffff>;
  262. gpcs-address = <0x0000000a>;
  263. tah-device = <&TAH0>;
  264. tah-channel = <0>;
  265. has-inverted-stacr-oc;
  266. has-new-stacr-staopc;
  267. };
  268. EMAC1: ethernet@ef600f00 {
  269. device_type = "network";
  270. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  271. interrupt-parent = <&EMAC1>;
  272. interrupts = <0x0 0x1>;
  273. #interrupt-cells = <1>;
  274. #address-cells = <0>;
  275. #size-cells = <0>;
  276. interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
  277. /*Wake*/ 0x1 &UIC2 0x15 0x4>;
  278. reg = <0xef600f00 0x000000c4>;
  279. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  280. mal-device = <&MAL0>;
  281. mal-tx-channel = <1>;
  282. mal-rx-channel = <8>;
  283. cell-index = <1>;
  284. max-frame-size = <9000>;
  285. rx-fifo-size = <4096>;
  286. tx-fifo-size = <2048>;
  287. rx-fifo-size-gige = <16384>;
  288. phy-mode = "sgmii";
  289. phy-map = <0x00000000>;
  290. gpcs-address = <0x0000000b>;
  291. tah-device = <&TAH1>;
  292. tah-channel = <1>;
  293. has-inverted-stacr-oc;
  294. has-new-stacr-staopc;
  295. mdio-device = <&EMAC0>;
  296. };
  297. EMAC2: ethernet@ef601100 {
  298. device_type = "network";
  299. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  300. interrupt-parent = <&EMAC2>;
  301. interrupts = <0x0 0x1>;
  302. #interrupt-cells = <1>;
  303. #address-cells = <0>;
  304. #size-cells = <0>;
  305. interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
  306. /*Wake*/ 0x1 &UIC2 0x16 0x4>;
  307. reg = <0xef601100 0x000000c4>;
  308. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  309. mal-device = <&MAL0>;
  310. mal-tx-channel = <2>;
  311. mal-rx-channel = <16>;
  312. cell-index = <2>;
  313. max-frame-size = <9000>;
  314. rx-fifo-size = <4096>;
  315. tx-fifo-size = <2048>;
  316. rx-fifo-size-gige = <16384>;
  317. tx-fifo-size-gige = <16384>; /* emac2&3 only */
  318. phy-mode = "sgmii";
  319. phy-map = <0x00000001>;
  320. gpcs-address = <0x0000000C>;
  321. has-inverted-stacr-oc;
  322. has-new-stacr-staopc;
  323. mdio-device = <&EMAC0>;
  324. };
  325. };
  326. };
  327. };