irq.c 4.1 KB

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  1. /*
  2. * Copyright 2001 MontaVista Software Inc.
  3. * Author: MontaVista Software, Inc.
  4. * ahennessy@mvista.com
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. *
  10. * Copyright (C) 2000-2001 Toshiba Corporation
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  18. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  20. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  23. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  24. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27. *
  28. * You should have received a copy of the GNU General Public License along
  29. * with this program; if not, write to the Free Software Foundation, Inc.,
  30. * 675 Mass Ave, Cambridge, MA 02139, USA.
  31. */
  32. #include <linux/init.h>
  33. #include <linux/types.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/irq.h>
  36. #include <asm/io.h>
  37. #include <asm/mipsregs.h>
  38. #include <asm/txx9/generic.h>
  39. #include <asm/txx9/jmr3927.h>
  40. #if JMR3927_IRQ_END > NR_IRQS
  41. #error JMR3927_IRQ_END > NR_IRQS
  42. #endif
  43. /*
  44. * CP0_STATUS is a thread's resource (saved/restored on context switch).
  45. * So disable_irq/enable_irq MUST handle IOC/IRC registers.
  46. */
  47. static void mask_irq_ioc(struct irq_data *d)
  48. {
  49. /* 0: mask */
  50. unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
  51. unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
  52. unsigned int bit = 1 << irq_nr;
  53. jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
  54. /* flush write buffer */
  55. (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
  56. }
  57. static void unmask_irq_ioc(struct irq_data *d)
  58. {
  59. /* 0: mask */
  60. unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
  61. unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
  62. unsigned int bit = 1 << irq_nr;
  63. jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
  64. /* flush write buffer */
  65. (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
  66. }
  67. static int jmr3927_ioc_irqroute(void)
  68. {
  69. unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
  70. int i;
  71. for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
  72. if (istat & (1 << i))
  73. return JMR3927_IRQ_IOC + i;
  74. }
  75. return -1;
  76. }
  77. static int jmr3927_irq_dispatch(int pending)
  78. {
  79. int irq;
  80. if ((pending & CAUSEF_IP7) == 0)
  81. return -1;
  82. irq = (pending >> CAUSEB_IP2) & 0x0f;
  83. irq += JMR3927_IRQ_IRC;
  84. if (irq == JMR3927_IRQ_IOCINT)
  85. irq = jmr3927_ioc_irqroute();
  86. return irq;
  87. }
  88. static struct irq_chip jmr3927_irq_ioc = {
  89. .name = "jmr3927_ioc",
  90. .irq_mask = mask_irq_ioc,
  91. .irq_unmask = unmask_irq_ioc,
  92. };
  93. void __init jmr3927_irq_setup(void)
  94. {
  95. int i;
  96. txx9_irq_dispatch = jmr3927_irq_dispatch;
  97. /* Now, interrupt control disabled, */
  98. /* all IRC interrupts are masked, */
  99. /* all IRC interrupt mode are Low Active. */
  100. /* mask all IOC interrupts */
  101. jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
  102. /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
  103. jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
  104. /* clear PCI Soft interrupts */
  105. jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
  106. /* clear PCI Reset interrupts */
  107. jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
  108. tx3927_irq_init();
  109. for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
  110. irq_set_chip_and_handler(i, &jmr3927_irq_ioc,
  111. handle_level_irq);
  112. /* setup IOC interrupt 1 (PCI, MODEM) */
  113. irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
  114. }