early_pin.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276
  1. /*
  2. * Joshua Henderson <joshua.henderson@microchip.com>
  3. * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
  4. *
  5. * This program is free software; you can distribute it and/or modify it
  6. * under the terms of the GNU General Public License (Version 2) as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. */
  14. #include <asm/io.h>
  15. #include "early_pin.h"
  16. #define PPS_BASE 0x1f800000
  17. /* Input PPS Registers */
  18. #define INT1R 0x1404
  19. #define INT2R 0x1408
  20. #define INT3R 0x140C
  21. #define INT4R 0x1410
  22. #define T2CKR 0x1418
  23. #define T3CKR 0x141C
  24. #define T4CKR 0x1420
  25. #define T5CKR 0x1424
  26. #define T6CKR 0x1428
  27. #define T7CKR 0x142C
  28. #define T8CKR 0x1430
  29. #define T9CKR 0x1434
  30. #define IC1R 0x1438
  31. #define IC2R 0x143C
  32. #define IC3R 0x1440
  33. #define IC4R 0x1444
  34. #define IC5R 0x1448
  35. #define IC6R 0x144C
  36. #define IC7R 0x1450
  37. #define IC8R 0x1454
  38. #define IC9R 0x1458
  39. #define OCFAR 0x1460
  40. #define U1RXR 0x1468
  41. #define U1CTSR 0x146C
  42. #define U2RXR 0x1470
  43. #define U2CTSR 0x1474
  44. #define U3RXR 0x1478
  45. #define U3CTSR 0x147C
  46. #define U4RXR 0x1480
  47. #define U4CTSR 0x1484
  48. #define U5RXR 0x1488
  49. #define U5CTSR 0x148C
  50. #define U6RXR 0x1490
  51. #define U6CTSR 0x1494
  52. #define SDI1R 0x149C
  53. #define SS1R 0x14A0
  54. #define SDI2R 0x14A8
  55. #define SS2R 0x14AC
  56. #define SDI3R 0x14B4
  57. #define SS3R 0x14B8
  58. #define SDI4R 0x14C0
  59. #define SS4R 0x14C4
  60. #define SDI5R 0x14CC
  61. #define SS5R 0x14D0
  62. #define SDI6R 0x14D8
  63. #define SS6R 0x14DC
  64. #define C1RXR 0x14E0
  65. #define C2RXR 0x14E4
  66. #define REFCLKI1R 0x14E8
  67. #define REFCLKI3R 0x14F0
  68. #define REFCLKI4R 0x14F4
  69. static const struct
  70. {
  71. int function;
  72. int reg;
  73. } input_pin_reg[] = {
  74. { IN_FUNC_INT3, INT3R },
  75. { IN_FUNC_T2CK, T2CKR },
  76. { IN_FUNC_T6CK, T6CKR },
  77. { IN_FUNC_IC3, IC3R },
  78. { IN_FUNC_IC7, IC7R },
  79. { IN_FUNC_U1RX, U1RXR },
  80. { IN_FUNC_U2CTS, U2CTSR },
  81. { IN_FUNC_U5RX, U5RXR },
  82. { IN_FUNC_U6CTS, U6CTSR },
  83. { IN_FUNC_SDI1, SDI1R },
  84. { IN_FUNC_SDI3, SDI3R },
  85. { IN_FUNC_SDI5, SDI5R },
  86. { IN_FUNC_SS6, SS6R },
  87. { IN_FUNC_REFCLKI1, REFCLKI1R },
  88. { IN_FUNC_INT4, INT4R },
  89. { IN_FUNC_T5CK, T5CKR },
  90. { IN_FUNC_T7CK, T7CKR },
  91. { IN_FUNC_IC4, IC4R },
  92. { IN_FUNC_IC8, IC8R },
  93. { IN_FUNC_U3RX, U3RXR },
  94. { IN_FUNC_U4CTS, U4CTSR },
  95. { IN_FUNC_SDI2, SDI2R },
  96. { IN_FUNC_SDI4, SDI4R },
  97. { IN_FUNC_C1RX, C1RXR },
  98. { IN_FUNC_REFCLKI4, REFCLKI4R },
  99. { IN_FUNC_INT2, INT2R },
  100. { IN_FUNC_T3CK, T3CKR },
  101. { IN_FUNC_T8CK, T8CKR },
  102. { IN_FUNC_IC2, IC2R },
  103. { IN_FUNC_IC5, IC5R },
  104. { IN_FUNC_IC9, IC9R },
  105. { IN_FUNC_U1CTS, U1CTSR },
  106. { IN_FUNC_U2RX, U2RXR },
  107. { IN_FUNC_U5CTS, U5CTSR },
  108. { IN_FUNC_SS1, SS1R },
  109. { IN_FUNC_SS3, SS3R },
  110. { IN_FUNC_SS4, SS4R },
  111. { IN_FUNC_SS5, SS5R },
  112. { IN_FUNC_C2RX, C2RXR },
  113. { IN_FUNC_INT1, INT1R },
  114. { IN_FUNC_T4CK, T4CKR },
  115. { IN_FUNC_T9CK, T9CKR },
  116. { IN_FUNC_IC1, IC1R },
  117. { IN_FUNC_IC6, IC6R },
  118. { IN_FUNC_U3CTS, U3CTSR },
  119. { IN_FUNC_U4RX, U4RXR },
  120. { IN_FUNC_U6RX, U6RXR },
  121. { IN_FUNC_SS2, SS2R },
  122. { IN_FUNC_SDI6, SDI6R },
  123. { IN_FUNC_OCFA, OCFAR },
  124. { IN_FUNC_REFCLKI3, REFCLKI3R },
  125. };
  126. void pic32_pps_input(int function, int pin)
  127. {
  128. void __iomem *pps_base = ioremap_nocache(PPS_BASE, 0xF4);
  129. int i;
  130. for (i = 0; i < ARRAY_SIZE(input_pin_reg); i++) {
  131. if (input_pin_reg[i].function == function) {
  132. __raw_writel(pin, pps_base + input_pin_reg[i].reg);
  133. return;
  134. }
  135. }
  136. iounmap(pps_base);
  137. }
  138. /* Output PPS Registers */
  139. #define RPA14R 0x1538
  140. #define RPA15R 0x153C
  141. #define RPB0R 0x1540
  142. #define RPB1R 0x1544
  143. #define RPB2R 0x1548
  144. #define RPB3R 0x154C
  145. #define RPB5R 0x1554
  146. #define RPB6R 0x1558
  147. #define RPB7R 0x155C
  148. #define RPB8R 0x1560
  149. #define RPB9R 0x1564
  150. #define RPB10R 0x1568
  151. #define RPB14R 0x1578
  152. #define RPB15R 0x157C
  153. #define RPC1R 0x1584
  154. #define RPC2R 0x1588
  155. #define RPC3R 0x158C
  156. #define RPC4R 0x1590
  157. #define RPC13R 0x15B4
  158. #define RPC14R 0x15B8
  159. #define RPD0R 0x15C0
  160. #define RPD1R 0x15C4
  161. #define RPD2R 0x15C8
  162. #define RPD3R 0x15CC
  163. #define RPD4R 0x15D0
  164. #define RPD5R 0x15D4
  165. #define RPD6R 0x15D8
  166. #define RPD7R 0x15DC
  167. #define RPD9R 0x15E4
  168. #define RPD10R 0x15E8
  169. #define RPD11R 0x15EC
  170. #define RPD12R 0x15F0
  171. #define RPD14R 0x15F8
  172. #define RPD15R 0x15FC
  173. #define RPE3R 0x160C
  174. #define RPE5R 0x1614
  175. #define RPE8R 0x1620
  176. #define RPE9R 0x1624
  177. #define RPF0R 0x1640
  178. #define RPF1R 0x1644
  179. #define RPF2R 0x1648
  180. #define RPF3R 0x164C
  181. #define RPF4R 0x1650
  182. #define RPF5R 0x1654
  183. #define RPF8R 0x1660
  184. #define RPF12R 0x1670
  185. #define RPF13R 0x1674
  186. #define RPG0R 0x1680
  187. #define RPG1R 0x1684
  188. #define RPG6R 0x1698
  189. #define RPG7R 0x169C
  190. #define RPG8R 0x16A0
  191. #define RPG9R 0x16A4
  192. static const struct
  193. {
  194. int pin;
  195. int reg;
  196. } output_pin_reg[] = {
  197. { OUT_RPD2, RPD2R },
  198. { OUT_RPG8, RPG8R },
  199. { OUT_RPF4, RPF4R },
  200. { OUT_RPD10, RPD10R },
  201. { OUT_RPF1, RPF1R },
  202. { OUT_RPB9, RPB9R },
  203. { OUT_RPB10, RPB10R },
  204. { OUT_RPC14, RPC14R },
  205. { OUT_RPB5, RPB5R },
  206. { OUT_RPC1, RPC1R },
  207. { OUT_RPD14, RPD14R },
  208. { OUT_RPG1, RPG1R },
  209. { OUT_RPA14, RPA14R },
  210. { OUT_RPD6, RPD6R },
  211. { OUT_RPD3, RPD3R },
  212. { OUT_RPG7, RPG7R },
  213. { OUT_RPF5, RPF5R },
  214. { OUT_RPD11, RPD11R },
  215. { OUT_RPF0, RPF0R },
  216. { OUT_RPB1, RPB1R },
  217. { OUT_RPE5, RPE5R },
  218. { OUT_RPC13, RPC13R },
  219. { OUT_RPB3, RPB3R },
  220. { OUT_RPC4, RPC4R },
  221. { OUT_RPD15, RPD15R },
  222. { OUT_RPG0, RPG0R },
  223. { OUT_RPA15, RPA15R },
  224. { OUT_RPD7, RPD7R },
  225. { OUT_RPD9, RPD9R },
  226. { OUT_RPG6, RPG6R },
  227. { OUT_RPB8, RPB8R },
  228. { OUT_RPB15, RPB15R },
  229. { OUT_RPD4, RPD4R },
  230. { OUT_RPB0, RPB0R },
  231. { OUT_RPE3, RPE3R },
  232. { OUT_RPB7, RPB7R },
  233. { OUT_RPF12, RPF12R },
  234. { OUT_RPD12, RPD12R },
  235. { OUT_RPF8, RPF8R },
  236. { OUT_RPC3, RPC3R },
  237. { OUT_RPE9, RPE9R },
  238. { OUT_RPD1, RPD1R },
  239. { OUT_RPG9, RPG9R },
  240. { OUT_RPB14, RPB14R },
  241. { OUT_RPD0, RPD0R },
  242. { OUT_RPB6, RPB6R },
  243. { OUT_RPD5, RPD5R },
  244. { OUT_RPB2, RPB2R },
  245. { OUT_RPF3, RPF3R },
  246. { OUT_RPF13, RPF13R },
  247. { OUT_RPC2, RPC2R },
  248. { OUT_RPE8, RPE8R },
  249. { OUT_RPF2, RPF2R },
  250. };
  251. void pic32_pps_output(int function, int pin)
  252. {
  253. void __iomem *pps_base = ioremap_nocache(PPS_BASE, 0x170);
  254. int i;
  255. for (i = 0; i < ARRAY_SIZE(output_pin_reg); i++) {
  256. if (output_pin_reg[i].pin == pin) {
  257. __raw_writel(function,
  258. pps_base + output_pin_reg[i].reg);
  259. return;
  260. }
  261. }
  262. iounmap(pps_base);
  263. }