iomap.c 4.5 KB

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  1. /*
  2. * Implement the default iomap interfaces
  3. *
  4. * (C) Copyright 2004 Linus Torvalds
  5. * (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org>
  6. * (C) Copyright 2007 MIPS Technologies, Inc.
  7. * written by Ralf Baechle <ralf@linux-mips.org>
  8. */
  9. #include <linux/export.h>
  10. #include <asm/io.h>
  11. /*
  12. * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
  13. * access or a MMIO access, these functions don't care. The info is
  14. * encoded in the hardware mapping set up by the mapping functions
  15. * (or the cookie itself, depending on implementation and hw).
  16. *
  17. * The generic routines don't assume any hardware mappings, and just
  18. * encode the PIO/MMIO as part of the cookie. They coldly assume that
  19. * the MMIO IO mappings are not in the low address range.
  20. *
  21. * Architectures for which this is not true can't use this generic
  22. * implementation and should do their own copy.
  23. */
  24. #define PIO_MASK 0x0ffffUL
  25. unsigned int ioread8(void __iomem *addr)
  26. {
  27. return readb(addr);
  28. }
  29. EXPORT_SYMBOL(ioread8);
  30. unsigned int ioread16(void __iomem *addr)
  31. {
  32. return readw(addr);
  33. }
  34. EXPORT_SYMBOL(ioread16);
  35. unsigned int ioread16be(void __iomem *addr)
  36. {
  37. return be16_to_cpu(__raw_readw(addr));
  38. }
  39. EXPORT_SYMBOL(ioread16be);
  40. unsigned int ioread32(void __iomem *addr)
  41. {
  42. return readl(addr);
  43. }
  44. EXPORT_SYMBOL(ioread32);
  45. unsigned int ioread32be(void __iomem *addr)
  46. {
  47. return be32_to_cpu(__raw_readl(addr));
  48. }
  49. EXPORT_SYMBOL(ioread32be);
  50. void iowrite8(u8 val, void __iomem *addr)
  51. {
  52. writeb(val, addr);
  53. }
  54. EXPORT_SYMBOL(iowrite8);
  55. void iowrite16(u16 val, void __iomem *addr)
  56. {
  57. writew(val, addr);
  58. }
  59. EXPORT_SYMBOL(iowrite16);
  60. void iowrite16be(u16 val, void __iomem *addr)
  61. {
  62. __raw_writew(cpu_to_be16(val), addr);
  63. }
  64. EXPORT_SYMBOL(iowrite16be);
  65. void iowrite32(u32 val, void __iomem *addr)
  66. {
  67. writel(val, addr);
  68. }
  69. EXPORT_SYMBOL(iowrite32);
  70. void iowrite32be(u32 val, void __iomem *addr)
  71. {
  72. __raw_writel(cpu_to_be32(val), addr);
  73. }
  74. EXPORT_SYMBOL(iowrite32be);
  75. /*
  76. * These are the "repeat MMIO read/write" functions.
  77. * Note the "__mem" accesses, since we want to convert
  78. * to CPU byte order if the host bus happens to not match the
  79. * endianness of PCI/ISA (see mach-generic/mangle-port.h).
  80. */
  81. static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
  82. {
  83. while (--count >= 0) {
  84. u8 data = __mem_readb(addr);
  85. *dst = data;
  86. dst++;
  87. }
  88. }
  89. static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
  90. {
  91. while (--count >= 0) {
  92. u16 data = __mem_readw(addr);
  93. *dst = data;
  94. dst++;
  95. }
  96. }
  97. static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
  98. {
  99. while (--count >= 0) {
  100. u32 data = __mem_readl(addr);
  101. *dst = data;
  102. dst++;
  103. }
  104. }
  105. static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
  106. {
  107. while (--count >= 0) {
  108. __mem_writeb(*src, addr);
  109. src++;
  110. }
  111. }
  112. static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
  113. {
  114. while (--count >= 0) {
  115. __mem_writew(*src, addr);
  116. src++;
  117. }
  118. }
  119. static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
  120. {
  121. while (--count >= 0) {
  122. __mem_writel(*src, addr);
  123. src++;
  124. }
  125. }
  126. void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
  127. {
  128. mmio_insb(addr, dst, count);
  129. }
  130. EXPORT_SYMBOL(ioread8_rep);
  131. void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
  132. {
  133. mmio_insw(addr, dst, count);
  134. }
  135. EXPORT_SYMBOL(ioread16_rep);
  136. void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
  137. {
  138. mmio_insl(addr, dst, count);
  139. }
  140. EXPORT_SYMBOL(ioread32_rep);
  141. void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
  142. {
  143. mmio_outsb(addr, src, count);
  144. }
  145. EXPORT_SYMBOL(iowrite8_rep);
  146. void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
  147. {
  148. mmio_outsw(addr, src, count);
  149. }
  150. EXPORT_SYMBOL(iowrite16_rep);
  151. void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
  152. {
  153. mmio_outsl(addr, src, count);
  154. }
  155. EXPORT_SYMBOL(iowrite32_rep);
  156. /*
  157. * Create a virtual mapping cookie for an IO port range
  158. *
  159. * This uses the same mapping are as the in/out family which has to be setup
  160. * by the platform initialization code.
  161. *
  162. * Just to make matters somewhat more interesting on MIPS systems with
  163. * multiple host bridge each will have it's own ioport address space.
  164. */
  165. static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr)
  166. {
  167. return (void __iomem *) (mips_io_port_base + port);
  168. }
  169. void __iomem *ioport_map(unsigned long port, unsigned int nr)
  170. {
  171. if (port > PIO_MASK)
  172. return NULL;
  173. return ioport_map_legacy(port, nr);
  174. }
  175. EXPORT_SYMBOL(ioport_map);
  176. void ioport_unmap(void __iomem *addr)
  177. {
  178. /* Nothing to do */
  179. }
  180. EXPORT_SYMBOL(ioport_unmap);