cvmx-helper-xaui.c 12 KB

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  1. /***********************license start***************
  2. * Author: Cavium Networks
  3. *
  4. * Contact: support@caviumnetworks.com
  5. * This file is part of the OCTEON SDK
  6. *
  7. * Copyright (c) 2003-2008 Cavium Networks
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this file; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. * or visit http://www.gnu.org/licenses/.
  23. *
  24. * This file may also be available under a different license from Cavium.
  25. * Contact Cavium Networks for more information
  26. ***********************license end**************************************/
  27. /*
  28. * Functions for XAUI initialization, configuration,
  29. * and monitoring.
  30. *
  31. */
  32. #include <asm/octeon/octeon.h>
  33. #include <asm/octeon/cvmx-config.h>
  34. #include <asm/octeon/cvmx-helper.h>
  35. #include <asm/octeon/cvmx-pko-defs.h>
  36. #include <asm/octeon/cvmx-gmxx-defs.h>
  37. #include <asm/octeon/cvmx-pcsxx-defs.h>
  38. void __cvmx_interrupt_gmxx_enable(int interface);
  39. void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
  40. void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
  41. int __cvmx_helper_xaui_enumerate(int interface)
  42. {
  43. union cvmx_gmxx_hg2_control gmx_hg2_control;
  44. /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
  45. gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
  46. if (gmx_hg2_control.s.hg2tx_en)
  47. return 16;
  48. else
  49. return 1;
  50. }
  51. /**
  52. * Probe a XAUI interface and determine the number of ports
  53. * connected to it. The XAUI interface should still be down
  54. * after this call.
  55. *
  56. * @interface: Interface to probe
  57. *
  58. * Returns Number of ports on the interface. Zero to disable.
  59. */
  60. int __cvmx_helper_xaui_probe(int interface)
  61. {
  62. int i;
  63. union cvmx_gmxx_inf_mode mode;
  64. /*
  65. * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
  66. * interface needs to be enabled before IPD otherwise per port
  67. * backpressure may not work properly.
  68. */
  69. mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
  70. mode.s.en = 1;
  71. cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
  72. __cvmx_helper_setup_gmx(interface, 1);
  73. /*
  74. * Setup PKO to support 16 ports for HiGig2 virtual
  75. * ports. We're pointing all of the PKO packet ports for this
  76. * interface to the XAUI. This allows us to use HiGig2
  77. * backpressure per port.
  78. */
  79. for (i = 0; i < 16; i++) {
  80. union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
  81. pko_mem_port_ptrs.u64 = 0;
  82. /*
  83. * We set each PKO port to have equal priority in a
  84. * round robin fashion.
  85. */
  86. pko_mem_port_ptrs.s.static_p = 0;
  87. pko_mem_port_ptrs.s.qos_mask = 0xff;
  88. /* All PKO ports map to the same XAUI hardware port */
  89. pko_mem_port_ptrs.s.eid = interface * 4;
  90. pko_mem_port_ptrs.s.pid = interface * 16 + i;
  91. cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
  92. }
  93. return __cvmx_helper_xaui_enumerate(interface);
  94. }
  95. /**
  96. * Bringup and enable a XAUI interface. After this call packet
  97. * I/O should be fully functional. This is called with IPD
  98. * enabled but PKO disabled.
  99. *
  100. * @interface: Interface to bring up
  101. *
  102. * Returns Zero on success, negative on failure
  103. */
  104. int __cvmx_helper_xaui_enable(int interface)
  105. {
  106. union cvmx_gmxx_prtx_cfg gmx_cfg;
  107. union cvmx_pcsxx_control1_reg xauiCtl;
  108. union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
  109. union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
  110. union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
  111. union cvmx_gmxx_tx_int_en gmx_tx_int_en;
  112. union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
  113. /* Setup PKND */
  114. if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
  115. gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
  116. gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
  117. cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
  118. }
  119. /* (1) Interface has already been enabled. */
  120. /* (2) Disable GMX. */
  121. xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
  122. xauiMiscCtl.s.gmxeno = 1;
  123. cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
  124. /* (3) Disable GMX and PCSX interrupts. */
  125. gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
  126. cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
  127. gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
  128. cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
  129. pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
  130. cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
  131. /* (4) Bring up the PCSX and GMX reconciliation layer. */
  132. /* (4)a Set polarity and lane swapping. */
  133. /* (4)b */
  134. gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
  135. /* Enable better IFG packing and improves performance */
  136. gmxXauiTxCtl.s.dic_en = 1;
  137. gmxXauiTxCtl.s.uni_en = 0;
  138. cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
  139. /* (4)c Aply reset sequence */
  140. xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
  141. xauiCtl.s.lo_pwr = 0;
  142. /* Issuing a reset here seems to hang some CN68XX chips. */
  143. if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
  144. !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
  145. xauiCtl.s.reset = 1;
  146. cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
  147. /* Wait for PCS to come out of reset */
  148. if (CVMX_WAIT_FOR_FIELD64
  149. (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
  150. reset, ==, 0, 10000))
  151. return -1;
  152. /* Wait for PCS to be aligned */
  153. if (CVMX_WAIT_FOR_FIELD64
  154. (CVMX_PCSXX_10GBX_STATUS_REG(interface),
  155. union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
  156. return -1;
  157. /* Wait for RX to be ready */
  158. if (CVMX_WAIT_FOR_FIELD64
  159. (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
  160. status, ==, 0, 10000))
  161. return -1;
  162. /* (6) Configure GMX */
  163. gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
  164. gmx_cfg.s.en = 0;
  165. cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
  166. /* Wait for GMX RX to be idle */
  167. if (CVMX_WAIT_FOR_FIELD64
  168. (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
  169. rx_idle, ==, 1, 10000))
  170. return -1;
  171. /* Wait for GMX TX to be idle */
  172. if (CVMX_WAIT_FOR_FIELD64
  173. (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
  174. tx_idle, ==, 1, 10000))
  175. return -1;
  176. /* GMX configure */
  177. gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
  178. gmx_cfg.s.speed = 1;
  179. gmx_cfg.s.speed_msb = 0;
  180. gmx_cfg.s.slottime = 1;
  181. cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
  182. cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
  183. cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
  184. cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
  185. /* (7) Clear out any error state */
  186. cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
  187. cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
  188. cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
  189. cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
  190. cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
  191. cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
  192. /* Wait for receive link */
  193. if (CVMX_WAIT_FOR_FIELD64
  194. (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
  195. rcv_lnk, ==, 1, 10000))
  196. return -1;
  197. if (CVMX_WAIT_FOR_FIELD64
  198. (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
  199. xmtflt, ==, 0, 10000))
  200. return -1;
  201. if (CVMX_WAIT_FOR_FIELD64
  202. (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
  203. rcvflt, ==, 0, 10000))
  204. return -1;
  205. cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
  206. cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
  207. cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
  208. /* (8) Enable packet reception */
  209. xauiMiscCtl.s.gmxeno = 0;
  210. cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
  211. gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
  212. gmx_cfg.s.en = 1;
  213. cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
  214. __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
  215. __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
  216. __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
  217. __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
  218. __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
  219. __cvmx_interrupt_gmxx_enable(interface);
  220. return 0;
  221. }
  222. /**
  223. * Return the link state of an IPD/PKO port as returned by
  224. * auto negotiation. The result of this function may not match
  225. * Octeon's link config if auto negotiation has changed since
  226. * the last call to cvmx_helper_link_set().
  227. *
  228. * @ipd_port: IPD/PKO port to query
  229. *
  230. * Returns Link state
  231. */
  232. cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
  233. {
  234. int interface = cvmx_helper_get_interface_num(ipd_port);
  235. union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
  236. union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
  237. union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
  238. cvmx_helper_link_info_t result;
  239. gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
  240. gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
  241. pcsxx_status1_reg.u64 =
  242. cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
  243. result.u64 = 0;
  244. /* Only return a link if both RX and TX are happy */
  245. if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
  246. (pcsxx_status1_reg.s.rcv_lnk == 1)) {
  247. result.s.link_up = 1;
  248. result.s.full_duplex = 1;
  249. result.s.speed = 10000;
  250. } else {
  251. /* Disable GMX and PCSX interrupts. */
  252. cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
  253. cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
  254. cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
  255. }
  256. return result;
  257. }
  258. /**
  259. * Configure an IPD/PKO port for the specified link state. This
  260. * function does not influence auto negotiation at the PHY level.
  261. * The passed link state must always match the link state returned
  262. * by cvmx_helper_link_get(). It is normally best to use
  263. * cvmx_helper_link_autoconf() instead.
  264. *
  265. * @ipd_port: IPD/PKO port to configure
  266. * @link_info: The new link state
  267. *
  268. * Returns Zero on success, negative on failure
  269. */
  270. int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
  271. {
  272. int interface = cvmx_helper_get_interface_num(ipd_port);
  273. union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
  274. union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
  275. gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
  276. gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
  277. /* If the link shouldn't be up, then just return */
  278. if (!link_info.s.link_up)
  279. return 0;
  280. /* Do nothing if both RX and TX are happy */
  281. if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
  282. return 0;
  283. /* Bring the link up */
  284. return __cvmx_helper_xaui_enable(interface);
  285. }
  286. /**
  287. * Configure a port for internal and/or external loopback. Internal loopback
  288. * causes packets sent by the port to be received by Octeon. External loopback
  289. * causes packets received from the wire to sent out again.
  290. *
  291. * @ipd_port: IPD/PKO port to loopback.
  292. * @enable_internal:
  293. * Non zero if you want internal loopback
  294. * @enable_external:
  295. * Non zero if you want external loopback
  296. *
  297. * Returns Zero on success, negative on failure.
  298. */
  299. extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
  300. int enable_internal,
  301. int enable_external)
  302. {
  303. int interface = cvmx_helper_get_interface_num(ipd_port);
  304. union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
  305. union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
  306. /* Set the internal loop */
  307. pcsxx_control1_reg.u64 =
  308. cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
  309. pcsxx_control1_reg.s.loopbck1 = enable_internal;
  310. cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
  311. pcsxx_control1_reg.u64);
  312. /* Set the external loop */
  313. gmxx_xaui_ext_loopback.u64 =
  314. cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
  315. gmxx_xaui_ext_loopback.s.en = enable_external;
  316. cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
  317. gmxx_xaui_ext_loopback.u64);
  318. /* Take the link through a reset */
  319. return __cvmx_helper_xaui_enable(interface);
  320. }