flowctrl.h 2.3 KB

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  1. /*
  2. * arch/arm/mach-tegra/flowctrl.h
  3. *
  4. * functions and macros to control the flowcontroller
  5. *
  6. * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2, as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #ifndef __MACH_TEGRA_FLOWCTRL_H
  21. #define __MACH_TEGRA_FLOWCTRL_H
  22. #define FLOW_CTRL_HALT_CPU0_EVENTS 0x0
  23. #define FLOW_CTRL_WAITEVENT (2 << 29)
  24. #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29)
  25. #define FLOW_CTRL_JTAG_RESUME (1 << 28)
  26. #define FLOW_CTRL_SCLK_RESUME (1 << 27)
  27. #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
  28. #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
  29. #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
  30. #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
  31. #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
  32. #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
  33. #define FLOW_CTRL_CPU0_CSR 0x8
  34. #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
  35. #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
  36. #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
  37. #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
  38. #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
  39. FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
  40. FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
  41. #define FLOW_CTRL_CSR_ENABLE (1 << 0)
  42. #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
  43. #define FLOW_CTRL_CPU1_CSR 0x18
  44. #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4)
  45. #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4)
  46. #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0
  47. #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8)
  48. #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4)
  49. #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8)
  50. #ifndef __ASSEMBLY__
  51. u32 flowctrl_read_cpu_csr(unsigned int cpuid);
  52. void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
  53. void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
  54. void flowctrl_cpu_suspend_enter(unsigned int cpuid);
  55. void flowctrl_cpu_suspend_exit(unsigned int cpuid);
  56. void tegra_flowctrl_init(void);
  57. #endif
  58. #endif