Home Explore Help
Sign In
phreedom2600net
/
linux-libre
Watch 2
Star 0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Branch: master
Branches Tags
linux-libre
/
arch
/
arm
/
mach-omap2
/
cm-regbits-54xx.h

cm-regbits-54xx.h 4.5 KB
Permalink History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105 
  1. /*
    2. 

  2.  * OMAP54xx Clock Management register bits
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
    5. 

  5.  *
    6. 

  6.  * Paul Walmsley (paul@pwsan.com)
    7. 

  7.  * Rajendra Nayak (rnayak@ti.com)
    8. 

  8.  * Benoit Cousson (b-cousson@ti.com)
    9. 

  9.  *
    10. 

  10.  * This file is automatically generated from the OMAP hardware databases.
    11. 

  11.  * We respectfully ask that any modifications to this file be coordinated
    12. 

  12.  * with the public linux-omap@vger.kernel.org mailing list and the
    13. 

  13.  * authors above to ensure that the autogeneration scripts are kept
    14. 

  14.  * up-to-date with the file contents.
    15. 

  15.  *
    16. 

  16.  * This program is free software; you can redistribute it and/or modify
    17. 

  17.  * it under the terms of the GNU General Public License version 2 as
    18. 

  18.  * published by the Free Software Foundation.
    19. 

  19.  */
    20. 

  20. 

  21. #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
    22. 

  22. #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
    23. 

  23. 

  24. #define OMAP54XX_ABE_STATDEP_SHIFT					3
    25. 

  25. #define OMAP54XX_AUTO_DPLL_MODE_MASK					(0x7 << 0)
    26. 

  26. #define OMAP54XX_CLKSEL_SHIFT						24
    27. 

  27. #define OMAP54XX_CLKSEL_WIDTH						0x1
    28. 

  28. #define OMAP54XX_CLKSEL_0_0_SHIFT					0
    29. 

  29. #define OMAP54XX_CLKSEL_0_0_WIDTH					0x1
    30. 

  30. #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT					24
    31. 

  31. #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH					0x1
    32. 

  32. #define OMAP54XX_CLKSEL_DIV_SHIFT					25
    33. 

  33. #define OMAP54XX_CLKSEL_DIV_WIDTH					0x1
    34. 

  34. #define OMAP54XX_CLKSEL_FCLK_SHIFT					24
    35. 

  35. #define OMAP54XX_CLKSEL_FCLK_WIDTH					0x1
    36. 

  36. #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT				24
    37. 

  37. #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH				0x1
    38. 

  38. #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT				25
    39. 

  39. #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH				0x1
    40. 

  40. #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT				26
    41. 

  41. #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH				0x2
    42. 

  42. #define OMAP54XX_CLKSEL_OPP_SHIFT					0
    43. 

  43. #define OMAP54XX_CLKSEL_OPP_WIDTH					0x2
    44. 

  44. #define OMAP54XX_CLKSEL_SOURCE_SHIFT					24
    45. 

  45. #define OMAP54XX_CLKSEL_SOURCE_WIDTH					0x2
    46. 

  46. #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT			24
    47. 

  47. #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH			0x1
    48. 

  48. #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT					24
    49. 

  49. #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH					0x1
    50. 

  50. #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT					25
    51. 

  51. #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH					0x1
    52. 

  52. #define OMAP54XX_DIVHS_MASK						(0x3f << 0)
    53. 

  53. #define OMAP54XX_DIVHS_0_4_MASK						(0x1f << 0)
    54. 

  54. #define OMAP54XX_DIVHS_0_6_MASK						(0x7f << 0)
    55. 

  55. #define OMAP54XX_DPLL_DIV_MASK						(0x7f << 0)
    56. 

  56. #define OMAP54XX_DPLL_EN_MASK						(0x7 << 0)
    57. 

  57. #define OMAP54XX_DPLL_LPMODE_EN_MASK					(1 << 10)
    58. 

  58. #define OMAP54XX_DPLL_MULT_MASK						(0x7ff << 8)
    59. 

  59. #define OMAP54XX_DPLL_REGM4XEN_MASK					(1 << 11)
    60. 

  60. #define OMAP54XX_DPLL_SD_DIV_MASK					(0xff << 24)
    61. 

  61. #define OMAP54XX_DSP_STATDEP_SHIFT					1
    62. 

  62. #define OMAP54XX_DSS_STATDEP_SHIFT					8
    63. 

  63. #define OMAP54XX_EMIF_STATDEP_SHIFT					4
    64. 

  64. #define OMAP54XX_GPU_STATDEP_SHIFT					10
    65. 

  65. #define OMAP54XX_IPU_STATDEP_SHIFT					0
    66. 

  66. #define OMAP54XX_IVA_STATDEP_SHIFT					2
    67. 

  67. #define OMAP54XX_L3INIT_STATDEP_SHIFT					7
    68. 

  68. #define OMAP54XX_L3MAIN1_STATDEP_SHIFT					5
    69. 

  69. #define OMAP54XX_L3MAIN2_STATDEP_SHIFT					6
    70. 

  70. #define OMAP54XX_L4CFG_STATDEP_SHIFT					12
    71. 

  71. #define OMAP54XX_L4PER_STATDEP_SHIFT					13
    72. 

  72. #define OMAP54XX_L4SEC_STATDEP_SHIFT					14
    73. 

  73. #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT				11
    74. 

  74. #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT				8
    75. 

  75. #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT				9
    76. 

  76. #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT					8
    77. 

  77. #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT				8
    78. 

  78. #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT					8
    79. 

  79. #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT					8
    80. 

  80. #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT			13
    81. 

  81. #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT			14
    82. 

  82. #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT			7
    83. 

  83. #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT				11
    84. 

  84. #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT				12
    85. 

  85. #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT				6
    86. 

  86. #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT				8
    87. 

  87. #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT				8
    88. 

  88. #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT				11
    89. 

  89. #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT				10
    90. 

  90. #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT				8
    91. 

  91. #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT				9
    92. 

  92. #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT				8
    93. 

  93. #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT				9
    94. 

  94. #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT				10
    95. 

  95. #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT				8
    96. 

  96. #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT				9
    97. 

  97. #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT				10
    98. 

  98. #define OMAP54XX_PAD_CLKS_GATE_SHIFT					8
    99. 

  99. #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT				10
    100. 

  100. #define OMAP54XX_ST_DPLL_CLK_MASK					(1 << 0)
    101. 

  101. #define OMAP54XX_SYS_CLKSEL_SHIFT					0
    102. 

  102. #define OMAP54XX_SYS_CLKSEL_WIDTH					0x3
    103. 

  103. #define OMAP54XX_WKUPAON_STATDEP_SHIFT					15
    104. 

  104. #endif
    105. 

  105.