dm365.c 37 KB

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  1. /*
  2. * TI DaVinci DM365 chip specific setup
  3. *
  4. * Copyright (C) 2009 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/clk.h>
  17. #include <linux/serial_8250.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/dmaengine.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/platform_data/edma.h>
  23. #include <linux/platform_data/gpio-davinci.h>
  24. #include <linux/platform_data/keyscan-davinci.h>
  25. #include <linux/platform_data/spi-davinci.h>
  26. #include <asm/mach/map.h>
  27. #include <mach/cputype.h>
  28. #include "psc.h"
  29. #include <mach/mux.h>
  30. #include <mach/irqs.h>
  31. #include <mach/time.h>
  32. #include <mach/serial.h>
  33. #include <mach/common.h>
  34. #include "davinci.h"
  35. #include "clock.h"
  36. #include "mux.h"
  37. #include "asp.h"
  38. #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
  39. #define DM365_RTC_BASE 0x01c69000
  40. #define DM365_KEYSCAN_BASE 0x01c69400
  41. #define DM365_OSD_BASE 0x01c71c00
  42. #define DM365_VENC_BASE 0x01c71e00
  43. #define DAVINCI_DM365_VC_BASE 0x01d0c000
  44. #define DAVINCI_DMA_VC_TX 2
  45. #define DAVINCI_DMA_VC_RX 3
  46. #define DM365_EMAC_BASE 0x01d07000
  47. #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
  48. #define DM365_EMAC_CNTRL_OFFSET 0x0000
  49. #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
  50. #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
  51. #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
  52. static struct pll_data pll1_data = {
  53. .num = 1,
  54. .phys_base = DAVINCI_PLL1_BASE,
  55. .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  56. };
  57. static struct pll_data pll2_data = {
  58. .num = 2,
  59. .phys_base = DAVINCI_PLL2_BASE,
  60. .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  61. };
  62. static struct clk ref_clk = {
  63. .name = "ref_clk",
  64. .rate = DM365_REF_FREQ,
  65. };
  66. static struct clk pll1_clk = {
  67. .name = "pll1",
  68. .parent = &ref_clk,
  69. .flags = CLK_PLL,
  70. .pll_data = &pll1_data,
  71. };
  72. static struct clk pll1_aux_clk = {
  73. .name = "pll1_aux_clk",
  74. .parent = &pll1_clk,
  75. .flags = CLK_PLL | PRE_PLL,
  76. };
  77. static struct clk pll1_sysclkbp = {
  78. .name = "pll1_sysclkbp",
  79. .parent = &pll1_clk,
  80. .flags = CLK_PLL | PRE_PLL,
  81. .div_reg = BPDIV
  82. };
  83. static struct clk clkout0_clk = {
  84. .name = "clkout0",
  85. .parent = &pll1_clk,
  86. .flags = CLK_PLL | PRE_PLL,
  87. };
  88. static struct clk pll1_sysclk1 = {
  89. .name = "pll1_sysclk1",
  90. .parent = &pll1_clk,
  91. .flags = CLK_PLL,
  92. .div_reg = PLLDIV1,
  93. };
  94. static struct clk pll1_sysclk2 = {
  95. .name = "pll1_sysclk2",
  96. .parent = &pll1_clk,
  97. .flags = CLK_PLL,
  98. .div_reg = PLLDIV2,
  99. };
  100. static struct clk pll1_sysclk3 = {
  101. .name = "pll1_sysclk3",
  102. .parent = &pll1_clk,
  103. .flags = CLK_PLL,
  104. .div_reg = PLLDIV3,
  105. };
  106. static struct clk pll1_sysclk4 = {
  107. .name = "pll1_sysclk4",
  108. .parent = &pll1_clk,
  109. .flags = CLK_PLL,
  110. .div_reg = PLLDIV4,
  111. };
  112. static struct clk pll1_sysclk5 = {
  113. .name = "pll1_sysclk5",
  114. .parent = &pll1_clk,
  115. .flags = CLK_PLL,
  116. .div_reg = PLLDIV5,
  117. };
  118. static struct clk pll1_sysclk6 = {
  119. .name = "pll1_sysclk6",
  120. .parent = &pll1_clk,
  121. .flags = CLK_PLL,
  122. .div_reg = PLLDIV6,
  123. };
  124. static struct clk pll1_sysclk7 = {
  125. .name = "pll1_sysclk7",
  126. .parent = &pll1_clk,
  127. .flags = CLK_PLL,
  128. .div_reg = PLLDIV7,
  129. };
  130. static struct clk pll1_sysclk8 = {
  131. .name = "pll1_sysclk8",
  132. .parent = &pll1_clk,
  133. .flags = CLK_PLL,
  134. .div_reg = PLLDIV8,
  135. };
  136. static struct clk pll1_sysclk9 = {
  137. .name = "pll1_sysclk9",
  138. .parent = &pll1_clk,
  139. .flags = CLK_PLL,
  140. .div_reg = PLLDIV9,
  141. };
  142. static struct clk pll2_clk = {
  143. .name = "pll2",
  144. .parent = &ref_clk,
  145. .flags = CLK_PLL,
  146. .pll_data = &pll2_data,
  147. };
  148. static struct clk pll2_aux_clk = {
  149. .name = "pll2_aux_clk",
  150. .parent = &pll2_clk,
  151. .flags = CLK_PLL | PRE_PLL,
  152. };
  153. static struct clk clkout1_clk = {
  154. .name = "clkout1",
  155. .parent = &pll2_clk,
  156. .flags = CLK_PLL | PRE_PLL,
  157. };
  158. static struct clk pll2_sysclk1 = {
  159. .name = "pll2_sysclk1",
  160. .parent = &pll2_clk,
  161. .flags = CLK_PLL,
  162. .div_reg = PLLDIV1,
  163. };
  164. static struct clk pll2_sysclk2 = {
  165. .name = "pll2_sysclk2",
  166. .parent = &pll2_clk,
  167. .flags = CLK_PLL,
  168. .div_reg = PLLDIV2,
  169. };
  170. static struct clk pll2_sysclk3 = {
  171. .name = "pll2_sysclk3",
  172. .parent = &pll2_clk,
  173. .flags = CLK_PLL,
  174. .div_reg = PLLDIV3,
  175. };
  176. static struct clk pll2_sysclk4 = {
  177. .name = "pll2_sysclk4",
  178. .parent = &pll2_clk,
  179. .flags = CLK_PLL,
  180. .div_reg = PLLDIV4,
  181. };
  182. static struct clk pll2_sysclk5 = {
  183. .name = "pll2_sysclk5",
  184. .parent = &pll2_clk,
  185. .flags = CLK_PLL,
  186. .div_reg = PLLDIV5,
  187. };
  188. static struct clk pll2_sysclk6 = {
  189. .name = "pll2_sysclk6",
  190. .parent = &pll2_clk,
  191. .flags = CLK_PLL,
  192. .div_reg = PLLDIV6,
  193. };
  194. static struct clk pll2_sysclk7 = {
  195. .name = "pll2_sysclk7",
  196. .parent = &pll2_clk,
  197. .flags = CLK_PLL,
  198. .div_reg = PLLDIV7,
  199. };
  200. static struct clk pll2_sysclk8 = {
  201. .name = "pll2_sysclk8",
  202. .parent = &pll2_clk,
  203. .flags = CLK_PLL,
  204. .div_reg = PLLDIV8,
  205. };
  206. static struct clk pll2_sysclk9 = {
  207. .name = "pll2_sysclk9",
  208. .parent = &pll2_clk,
  209. .flags = CLK_PLL,
  210. .div_reg = PLLDIV9,
  211. };
  212. static struct clk vpss_dac_clk = {
  213. .name = "vpss_dac",
  214. .parent = &pll1_sysclk3,
  215. .lpsc = DM365_LPSC_DAC_CLK,
  216. };
  217. static struct clk vpss_master_clk = {
  218. .name = "vpss_master",
  219. .parent = &pll1_sysclk5,
  220. .lpsc = DM365_LPSC_VPSSMSTR,
  221. .flags = CLK_PSC,
  222. };
  223. static struct clk vpss_slave_clk = {
  224. .name = "vpss_slave",
  225. .parent = &pll1_sysclk5,
  226. .lpsc = DAVINCI_LPSC_VPSSSLV,
  227. };
  228. static struct clk arm_clk = {
  229. .name = "arm_clk",
  230. .parent = &pll2_sysclk2,
  231. .lpsc = DAVINCI_LPSC_ARM,
  232. .flags = ALWAYS_ENABLED,
  233. };
  234. static struct clk uart0_clk = {
  235. .name = "uart0",
  236. .parent = &pll1_aux_clk,
  237. .lpsc = DAVINCI_LPSC_UART0,
  238. };
  239. static struct clk uart1_clk = {
  240. .name = "uart1",
  241. .parent = &pll1_sysclk4,
  242. .lpsc = DAVINCI_LPSC_UART1,
  243. };
  244. static struct clk i2c_clk = {
  245. .name = "i2c",
  246. .parent = &pll1_aux_clk,
  247. .lpsc = DAVINCI_LPSC_I2C,
  248. };
  249. static struct clk mmcsd0_clk = {
  250. .name = "mmcsd0",
  251. .parent = &pll1_sysclk8,
  252. .lpsc = DAVINCI_LPSC_MMC_SD,
  253. };
  254. static struct clk mmcsd1_clk = {
  255. .name = "mmcsd1",
  256. .parent = &pll1_sysclk4,
  257. .lpsc = DM365_LPSC_MMC_SD1,
  258. };
  259. static struct clk spi0_clk = {
  260. .name = "spi0",
  261. .parent = &pll1_sysclk4,
  262. .lpsc = DAVINCI_LPSC_SPI,
  263. };
  264. static struct clk spi1_clk = {
  265. .name = "spi1",
  266. .parent = &pll1_sysclk4,
  267. .lpsc = DM365_LPSC_SPI1,
  268. };
  269. static struct clk spi2_clk = {
  270. .name = "spi2",
  271. .parent = &pll1_sysclk4,
  272. .lpsc = DM365_LPSC_SPI2,
  273. };
  274. static struct clk spi3_clk = {
  275. .name = "spi3",
  276. .parent = &pll1_sysclk4,
  277. .lpsc = DM365_LPSC_SPI3,
  278. };
  279. static struct clk spi4_clk = {
  280. .name = "spi4",
  281. .parent = &pll1_aux_clk,
  282. .lpsc = DM365_LPSC_SPI4,
  283. };
  284. static struct clk gpio_clk = {
  285. .name = "gpio",
  286. .parent = &pll1_sysclk4,
  287. .lpsc = DAVINCI_LPSC_GPIO,
  288. };
  289. static struct clk aemif_clk = {
  290. .name = "aemif",
  291. .parent = &pll1_sysclk4,
  292. .lpsc = DAVINCI_LPSC_AEMIF,
  293. };
  294. static struct clk pwm0_clk = {
  295. .name = "pwm0",
  296. .parent = &pll1_aux_clk,
  297. .lpsc = DAVINCI_LPSC_PWM0,
  298. };
  299. static struct clk pwm1_clk = {
  300. .name = "pwm1",
  301. .parent = &pll1_aux_clk,
  302. .lpsc = DAVINCI_LPSC_PWM1,
  303. };
  304. static struct clk pwm2_clk = {
  305. .name = "pwm2",
  306. .parent = &pll1_aux_clk,
  307. .lpsc = DAVINCI_LPSC_PWM2,
  308. };
  309. static struct clk pwm3_clk = {
  310. .name = "pwm3",
  311. .parent = &ref_clk,
  312. .lpsc = DM365_LPSC_PWM3,
  313. };
  314. static struct clk timer0_clk = {
  315. .name = "timer0",
  316. .parent = &pll1_aux_clk,
  317. .lpsc = DAVINCI_LPSC_TIMER0,
  318. };
  319. static struct clk timer1_clk = {
  320. .name = "timer1",
  321. .parent = &pll1_aux_clk,
  322. .lpsc = DAVINCI_LPSC_TIMER1,
  323. };
  324. static struct clk timer2_clk = {
  325. .name = "timer2",
  326. .parent = &pll1_aux_clk,
  327. .lpsc = DAVINCI_LPSC_TIMER2,
  328. .usecount = 1,
  329. };
  330. static struct clk timer3_clk = {
  331. .name = "timer3",
  332. .parent = &pll1_aux_clk,
  333. .lpsc = DM365_LPSC_TIMER3,
  334. };
  335. static struct clk usb_clk = {
  336. .name = "usb",
  337. .parent = &pll1_aux_clk,
  338. .lpsc = DAVINCI_LPSC_USB,
  339. };
  340. static struct clk emac_clk = {
  341. .name = "emac",
  342. .parent = &pll1_sysclk4,
  343. .lpsc = DM365_LPSC_EMAC,
  344. };
  345. static struct clk voicecodec_clk = {
  346. .name = "voice_codec",
  347. .parent = &pll2_sysclk4,
  348. .lpsc = DM365_LPSC_VOICE_CODEC,
  349. };
  350. static struct clk asp0_clk = {
  351. .name = "asp0",
  352. .parent = &pll1_sysclk4,
  353. .lpsc = DM365_LPSC_McBSP1,
  354. };
  355. static struct clk rto_clk = {
  356. .name = "rto",
  357. .parent = &pll1_sysclk4,
  358. .lpsc = DM365_LPSC_RTO,
  359. };
  360. static struct clk mjcp_clk = {
  361. .name = "mjcp",
  362. .parent = &pll1_sysclk3,
  363. .lpsc = DM365_LPSC_MJCP,
  364. };
  365. static struct clk_lookup dm365_clks[] = {
  366. CLK(NULL, "ref", &ref_clk),
  367. CLK(NULL, "pll1", &pll1_clk),
  368. CLK(NULL, "pll1_aux", &pll1_aux_clk),
  369. CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
  370. CLK(NULL, "clkout0", &clkout0_clk),
  371. CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
  372. CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
  373. CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
  374. CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
  375. CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
  376. CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
  377. CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
  378. CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
  379. CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
  380. CLK(NULL, "pll2", &pll2_clk),
  381. CLK(NULL, "pll2_aux", &pll2_aux_clk),
  382. CLK(NULL, "clkout1", &clkout1_clk),
  383. CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
  384. CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
  385. CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
  386. CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
  387. CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
  388. CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
  389. CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
  390. CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
  391. CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
  392. CLK(NULL, "vpss_dac", &vpss_dac_clk),
  393. CLK("vpss", "master", &vpss_master_clk),
  394. CLK("vpss", "slave", &vpss_slave_clk),
  395. CLK(NULL, "arm", &arm_clk),
  396. CLK("serial8250.0", NULL, &uart0_clk),
  397. CLK("serial8250.1", NULL, &uart1_clk),
  398. CLK("i2c_davinci.1", NULL, &i2c_clk),
  399. CLK("da830-mmc.0", NULL, &mmcsd0_clk),
  400. CLK("da830-mmc.1", NULL, &mmcsd1_clk),
  401. CLK("spi_davinci.0", NULL, &spi0_clk),
  402. CLK("spi_davinci.1", NULL, &spi1_clk),
  403. CLK("spi_davinci.2", NULL, &spi2_clk),
  404. CLK("spi_davinci.3", NULL, &spi3_clk),
  405. CLK("spi_davinci.4", NULL, &spi4_clk),
  406. CLK(NULL, "gpio", &gpio_clk),
  407. CLK(NULL, "aemif", &aemif_clk),
  408. CLK(NULL, "pwm0", &pwm0_clk),
  409. CLK(NULL, "pwm1", &pwm1_clk),
  410. CLK(NULL, "pwm2", &pwm2_clk),
  411. CLK(NULL, "pwm3", &pwm3_clk),
  412. CLK(NULL, "timer0", &timer0_clk),
  413. CLK(NULL, "timer1", &timer1_clk),
  414. CLK("davinci-wdt", NULL, &timer2_clk),
  415. CLK(NULL, "timer3", &timer3_clk),
  416. CLK(NULL, "usb", &usb_clk),
  417. CLK("davinci_emac.1", NULL, &emac_clk),
  418. CLK("davinci_mdio.0", "fck", &emac_clk),
  419. CLK("davinci_voicecodec", NULL, &voicecodec_clk),
  420. CLK("davinci-mcbsp", NULL, &asp0_clk),
  421. CLK(NULL, "rto", &rto_clk),
  422. CLK(NULL, "mjcp", &mjcp_clk),
  423. CLK(NULL, NULL, NULL),
  424. };
  425. /*----------------------------------------------------------------------*/
  426. #define INTMUX 0x18
  427. #define EVTMUX 0x1c
  428. static const struct mux_config dm365_pins[] = {
  429. #ifdef CONFIG_DAVINCI_MUX
  430. MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
  431. MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
  432. MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
  433. MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
  434. MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
  435. MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
  436. MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
  437. MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
  438. MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
  439. MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
  440. MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
  441. MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
  442. MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
  443. MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
  444. MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
  445. MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
  446. MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
  447. MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
  448. MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
  449. MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
  450. MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
  451. MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
  452. MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
  453. MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
  454. MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
  455. MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
  456. MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
  457. MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
  458. MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
  459. MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
  460. MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
  461. MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
  462. MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
  463. MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
  464. MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
  465. MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
  466. MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
  467. MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
  468. MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
  469. MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
  470. MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
  471. MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
  472. MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
  473. MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
  474. MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
  475. MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
  476. MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
  477. MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
  478. MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
  479. MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
  480. MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
  481. MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
  482. MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
  483. MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
  484. MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
  485. MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
  486. MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
  487. MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
  488. MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
  489. MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
  490. MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
  491. MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
  492. MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
  493. MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
  494. MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
  495. MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
  496. MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
  497. MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
  498. MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
  499. MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
  500. MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
  501. MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
  502. MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
  503. MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
  504. MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
  505. MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
  506. MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
  507. MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
  508. MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
  509. MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
  510. MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
  511. MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
  512. MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
  513. MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
  514. MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
  515. MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
  516. MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
  517. MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
  518. MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
  519. MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
  520. MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
  521. MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
  522. MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
  523. MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
  524. MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
  525. MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
  526. MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
  527. MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
  528. MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
  529. MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
  530. MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
  531. MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
  532. MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
  533. MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
  534. INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
  535. INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
  536. INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
  537. INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
  538. INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
  539. INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
  540. INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
  541. INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
  542. INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
  543. INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
  544. INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
  545. INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
  546. INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
  547. INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
  548. INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
  549. INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
  550. INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
  551. INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
  552. EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
  553. EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
  554. EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
  555. EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
  556. #endif
  557. };
  558. static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
  559. static struct davinci_spi_platform_data dm365_spi0_pdata = {
  560. .version = SPI_VERSION_1,
  561. .num_chipselect = 2,
  562. .dma_event_q = EVENTQ_3,
  563. .prescaler_limit = 1,
  564. };
  565. static struct resource dm365_spi0_resources[] = {
  566. {
  567. .start = 0x01c66000,
  568. .end = 0x01c667ff,
  569. .flags = IORESOURCE_MEM,
  570. },
  571. {
  572. .start = IRQ_DM365_SPIINT0_0,
  573. .flags = IORESOURCE_IRQ,
  574. },
  575. {
  576. .start = 17,
  577. .flags = IORESOURCE_DMA,
  578. },
  579. {
  580. .start = 16,
  581. .flags = IORESOURCE_DMA,
  582. },
  583. };
  584. static struct platform_device dm365_spi0_device = {
  585. .name = "spi_davinci",
  586. .id = 0,
  587. .dev = {
  588. .dma_mask = &dm365_spi0_dma_mask,
  589. .coherent_dma_mask = DMA_BIT_MASK(32),
  590. .platform_data = &dm365_spi0_pdata,
  591. },
  592. .num_resources = ARRAY_SIZE(dm365_spi0_resources),
  593. .resource = dm365_spi0_resources,
  594. };
  595. void __init dm365_init_spi0(unsigned chipselect_mask,
  596. const struct spi_board_info *info, unsigned len)
  597. {
  598. davinci_cfg_reg(DM365_SPI0_SCLK);
  599. davinci_cfg_reg(DM365_SPI0_SDI);
  600. davinci_cfg_reg(DM365_SPI0_SDO);
  601. /* not all slaves will be wired up */
  602. if (chipselect_mask & BIT(0))
  603. davinci_cfg_reg(DM365_SPI0_SDENA0);
  604. if (chipselect_mask & BIT(1))
  605. davinci_cfg_reg(DM365_SPI0_SDENA1);
  606. spi_register_board_info(info, len);
  607. platform_device_register(&dm365_spi0_device);
  608. }
  609. static struct resource dm365_gpio_resources[] = {
  610. { /* registers */
  611. .start = DAVINCI_GPIO_BASE,
  612. .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
  613. .flags = IORESOURCE_MEM,
  614. },
  615. { /* interrupt */
  616. .start = IRQ_DM365_GPIO0,
  617. .end = IRQ_DM365_GPIO7,
  618. .flags = IORESOURCE_IRQ,
  619. },
  620. };
  621. static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
  622. .ngpio = 104,
  623. .gpio_unbanked = 8,
  624. };
  625. int __init dm365_gpio_register(void)
  626. {
  627. return davinci_gpio_register(dm365_gpio_resources,
  628. ARRAY_SIZE(dm365_gpio_resources),
  629. &dm365_gpio_platform_data);
  630. }
  631. static struct emac_platform_data dm365_emac_pdata = {
  632. .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
  633. .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
  634. .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
  635. .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
  636. .version = EMAC_VERSION_2,
  637. };
  638. static struct resource dm365_emac_resources[] = {
  639. {
  640. .start = DM365_EMAC_BASE,
  641. .end = DM365_EMAC_BASE + SZ_16K - 1,
  642. .flags = IORESOURCE_MEM,
  643. },
  644. {
  645. .start = IRQ_DM365_EMAC_RXTHRESH,
  646. .end = IRQ_DM365_EMAC_RXTHRESH,
  647. .flags = IORESOURCE_IRQ,
  648. },
  649. {
  650. .start = IRQ_DM365_EMAC_RXPULSE,
  651. .end = IRQ_DM365_EMAC_RXPULSE,
  652. .flags = IORESOURCE_IRQ,
  653. },
  654. {
  655. .start = IRQ_DM365_EMAC_TXPULSE,
  656. .end = IRQ_DM365_EMAC_TXPULSE,
  657. .flags = IORESOURCE_IRQ,
  658. },
  659. {
  660. .start = IRQ_DM365_EMAC_MISCPULSE,
  661. .end = IRQ_DM365_EMAC_MISCPULSE,
  662. .flags = IORESOURCE_IRQ,
  663. },
  664. };
  665. static struct platform_device dm365_emac_device = {
  666. .name = "davinci_emac",
  667. .id = 1,
  668. .dev = {
  669. .platform_data = &dm365_emac_pdata,
  670. },
  671. .num_resources = ARRAY_SIZE(dm365_emac_resources),
  672. .resource = dm365_emac_resources,
  673. };
  674. static struct resource dm365_mdio_resources[] = {
  675. {
  676. .start = DM365_EMAC_MDIO_BASE,
  677. .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
  678. .flags = IORESOURCE_MEM,
  679. },
  680. };
  681. static struct platform_device dm365_mdio_device = {
  682. .name = "davinci_mdio",
  683. .id = 0,
  684. .num_resources = ARRAY_SIZE(dm365_mdio_resources),
  685. .resource = dm365_mdio_resources,
  686. };
  687. static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
  688. [IRQ_VDINT0] = 2,
  689. [IRQ_VDINT1] = 6,
  690. [IRQ_VDINT2] = 6,
  691. [IRQ_HISTINT] = 6,
  692. [IRQ_H3AINT] = 6,
  693. [IRQ_PRVUINT] = 6,
  694. [IRQ_RSZINT] = 6,
  695. [IRQ_DM365_INSFINT] = 7,
  696. [IRQ_VENCINT] = 6,
  697. [IRQ_ASQINT] = 6,
  698. [IRQ_IMXINT] = 6,
  699. [IRQ_DM365_IMCOPINT] = 4,
  700. [IRQ_USBINT] = 4,
  701. [IRQ_DM365_RTOINT] = 7,
  702. [IRQ_DM365_TINT5] = 7,
  703. [IRQ_DM365_TINT6] = 5,
  704. [IRQ_CCINT0] = 5,
  705. [IRQ_CCERRINT] = 5,
  706. [IRQ_TCERRINT0] = 5,
  707. [IRQ_TCERRINT] = 7,
  708. [IRQ_PSCIN] = 4,
  709. [IRQ_DM365_SPINT2_1] = 7,
  710. [IRQ_DM365_TINT7] = 7,
  711. [IRQ_DM365_SDIOINT0] = 7,
  712. [IRQ_MBXINT] = 7,
  713. [IRQ_MBRINT] = 7,
  714. [IRQ_MMCINT] = 7,
  715. [IRQ_DM365_MMCINT1] = 7,
  716. [IRQ_DM365_PWMINT3] = 7,
  717. [IRQ_AEMIFINT] = 2,
  718. [IRQ_DM365_SDIOINT1] = 2,
  719. [IRQ_TINT0_TINT12] = 7,
  720. [IRQ_TINT0_TINT34] = 7,
  721. [IRQ_TINT1_TINT12] = 7,
  722. [IRQ_TINT1_TINT34] = 7,
  723. [IRQ_PWMINT0] = 7,
  724. [IRQ_PWMINT1] = 3,
  725. [IRQ_PWMINT2] = 3,
  726. [IRQ_I2C] = 3,
  727. [IRQ_UARTINT0] = 3,
  728. [IRQ_UARTINT1] = 3,
  729. [IRQ_DM365_RTCINT] = 3,
  730. [IRQ_DM365_SPIINT0_0] = 3,
  731. [IRQ_DM365_SPIINT3_0] = 3,
  732. [IRQ_DM365_GPIO0] = 3,
  733. [IRQ_DM365_GPIO1] = 7,
  734. [IRQ_DM365_GPIO2] = 4,
  735. [IRQ_DM365_GPIO3] = 4,
  736. [IRQ_DM365_GPIO4] = 7,
  737. [IRQ_DM365_GPIO5] = 7,
  738. [IRQ_DM365_GPIO6] = 7,
  739. [IRQ_DM365_GPIO7] = 7,
  740. [IRQ_DM365_EMAC_RXTHRESH] = 7,
  741. [IRQ_DM365_EMAC_RXPULSE] = 7,
  742. [IRQ_DM365_EMAC_TXPULSE] = 7,
  743. [IRQ_DM365_EMAC_MISCPULSE] = 7,
  744. [IRQ_DM365_GPIO12] = 7,
  745. [IRQ_DM365_GPIO13] = 7,
  746. [IRQ_DM365_GPIO14] = 7,
  747. [IRQ_DM365_GPIO15] = 7,
  748. [IRQ_DM365_KEYINT] = 7,
  749. [IRQ_DM365_TCERRINT2] = 7,
  750. [IRQ_DM365_TCERRINT3] = 7,
  751. [IRQ_DM365_EMUINT] = 7,
  752. };
  753. /* Four Transfer Controllers on DM365 */
  754. static s8 dm365_queue_priority_mapping[][2] = {
  755. /* {event queue no, Priority} */
  756. {0, 7},
  757. {1, 7},
  758. {2, 7},
  759. {3, 0},
  760. {-1, -1},
  761. };
  762. static const struct dma_slave_map dm365_edma_map[] = {
  763. { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
  764. { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
  765. { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
  766. { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
  767. { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
  768. { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
  769. { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
  770. { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
  771. { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
  772. { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
  773. { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
  774. { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
  775. { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
  776. { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
  777. { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
  778. { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
  779. };
  780. static struct edma_soc_info dm365_edma_pdata = {
  781. .queue_priority_mapping = dm365_queue_priority_mapping,
  782. .default_queue = EVENTQ_3,
  783. .slave_map = dm365_edma_map,
  784. .slavecnt = ARRAY_SIZE(dm365_edma_map),
  785. };
  786. static struct resource edma_resources[] = {
  787. {
  788. .name = "edma3_cc",
  789. .start = 0x01c00000,
  790. .end = 0x01c00000 + SZ_64K - 1,
  791. .flags = IORESOURCE_MEM,
  792. },
  793. {
  794. .name = "edma3_tc0",
  795. .start = 0x01c10000,
  796. .end = 0x01c10000 + SZ_1K - 1,
  797. .flags = IORESOURCE_MEM,
  798. },
  799. {
  800. .name = "edma3_tc1",
  801. .start = 0x01c10400,
  802. .end = 0x01c10400 + SZ_1K - 1,
  803. .flags = IORESOURCE_MEM,
  804. },
  805. {
  806. .name = "edma3_tc2",
  807. .start = 0x01c10800,
  808. .end = 0x01c10800 + SZ_1K - 1,
  809. .flags = IORESOURCE_MEM,
  810. },
  811. {
  812. .name = "edma3_tc3",
  813. .start = 0x01c10c00,
  814. .end = 0x01c10c00 + SZ_1K - 1,
  815. .flags = IORESOURCE_MEM,
  816. },
  817. {
  818. .name = "edma3_ccint",
  819. .start = IRQ_CCINT0,
  820. .flags = IORESOURCE_IRQ,
  821. },
  822. {
  823. .name = "edma3_ccerrint",
  824. .start = IRQ_CCERRINT,
  825. .flags = IORESOURCE_IRQ,
  826. },
  827. /* not using TC*_ERR */
  828. };
  829. static struct platform_device dm365_edma_device = {
  830. .name = "edma",
  831. .id = 0,
  832. .dev.platform_data = &dm365_edma_pdata,
  833. .num_resources = ARRAY_SIZE(edma_resources),
  834. .resource = edma_resources,
  835. };
  836. static struct resource dm365_asp_resources[] = {
  837. {
  838. .name = "mpu",
  839. .start = DAVINCI_DM365_ASP0_BASE,
  840. .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
  841. .flags = IORESOURCE_MEM,
  842. },
  843. {
  844. .start = DAVINCI_DMA_ASP0_TX,
  845. .end = DAVINCI_DMA_ASP0_TX,
  846. .flags = IORESOURCE_DMA,
  847. },
  848. {
  849. .start = DAVINCI_DMA_ASP0_RX,
  850. .end = DAVINCI_DMA_ASP0_RX,
  851. .flags = IORESOURCE_DMA,
  852. },
  853. };
  854. static struct platform_device dm365_asp_device = {
  855. .name = "davinci-mcbsp",
  856. .id = -1,
  857. .num_resources = ARRAY_SIZE(dm365_asp_resources),
  858. .resource = dm365_asp_resources,
  859. };
  860. static struct resource dm365_vc_resources[] = {
  861. {
  862. .start = DAVINCI_DM365_VC_BASE,
  863. .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
  864. .flags = IORESOURCE_MEM,
  865. },
  866. {
  867. .start = DAVINCI_DMA_VC_TX,
  868. .end = DAVINCI_DMA_VC_TX,
  869. .flags = IORESOURCE_DMA,
  870. },
  871. {
  872. .start = DAVINCI_DMA_VC_RX,
  873. .end = DAVINCI_DMA_VC_RX,
  874. .flags = IORESOURCE_DMA,
  875. },
  876. };
  877. static struct platform_device dm365_vc_device = {
  878. .name = "davinci_voicecodec",
  879. .id = -1,
  880. .num_resources = ARRAY_SIZE(dm365_vc_resources),
  881. .resource = dm365_vc_resources,
  882. };
  883. static struct resource dm365_rtc_resources[] = {
  884. {
  885. .start = DM365_RTC_BASE,
  886. .end = DM365_RTC_BASE + SZ_1K - 1,
  887. .flags = IORESOURCE_MEM,
  888. },
  889. {
  890. .start = IRQ_DM365_RTCINT,
  891. .flags = IORESOURCE_IRQ,
  892. },
  893. };
  894. static struct platform_device dm365_rtc_device = {
  895. .name = "rtc_davinci",
  896. .id = 0,
  897. .num_resources = ARRAY_SIZE(dm365_rtc_resources),
  898. .resource = dm365_rtc_resources,
  899. };
  900. static struct map_desc dm365_io_desc[] = {
  901. {
  902. .virtual = IO_VIRT,
  903. .pfn = __phys_to_pfn(IO_PHYS),
  904. .length = IO_SIZE,
  905. .type = MT_DEVICE
  906. },
  907. };
  908. static struct resource dm365_ks_resources[] = {
  909. {
  910. /* registers */
  911. .start = DM365_KEYSCAN_BASE,
  912. .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
  913. .flags = IORESOURCE_MEM,
  914. },
  915. {
  916. /* interrupt */
  917. .start = IRQ_DM365_KEYINT,
  918. .end = IRQ_DM365_KEYINT,
  919. .flags = IORESOURCE_IRQ,
  920. },
  921. };
  922. static struct platform_device dm365_ks_device = {
  923. .name = "davinci_keyscan",
  924. .id = 0,
  925. .num_resources = ARRAY_SIZE(dm365_ks_resources),
  926. .resource = dm365_ks_resources,
  927. };
  928. /* Contents of JTAG ID register used to identify exact cpu type */
  929. static struct davinci_id dm365_ids[] = {
  930. {
  931. .variant = 0x0,
  932. .part_no = 0xb83e,
  933. .manufacturer = 0x017,
  934. .cpu_id = DAVINCI_CPU_ID_DM365,
  935. .name = "dm365_rev1.1",
  936. },
  937. {
  938. .variant = 0x8,
  939. .part_no = 0xb83e,
  940. .manufacturer = 0x017,
  941. .cpu_id = DAVINCI_CPU_ID_DM365,
  942. .name = "dm365_rev1.2",
  943. },
  944. };
  945. static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
  946. static struct davinci_timer_info dm365_timer_info = {
  947. .timers = davinci_timer_instance,
  948. .clockevent_id = T0_BOT,
  949. .clocksource_id = T0_TOP,
  950. };
  951. #define DM365_UART1_BASE (IO_PHYS + 0x106000)
  952. static struct plat_serial8250_port dm365_serial0_platform_data[] = {
  953. {
  954. .mapbase = DAVINCI_UART0_BASE,
  955. .irq = IRQ_UARTINT0,
  956. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  957. UPF_IOREMAP,
  958. .iotype = UPIO_MEM,
  959. .regshift = 2,
  960. },
  961. {
  962. .flags = 0,
  963. }
  964. };
  965. static struct plat_serial8250_port dm365_serial1_platform_data[] = {
  966. {
  967. .mapbase = DM365_UART1_BASE,
  968. .irq = IRQ_UARTINT1,
  969. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  970. UPF_IOREMAP,
  971. .iotype = UPIO_MEM,
  972. .regshift = 2,
  973. },
  974. {
  975. .flags = 0,
  976. }
  977. };
  978. struct platform_device dm365_serial_device[] = {
  979. {
  980. .name = "serial8250",
  981. .id = PLAT8250_DEV_PLATFORM,
  982. .dev = {
  983. .platform_data = dm365_serial0_platform_data,
  984. }
  985. },
  986. {
  987. .name = "serial8250",
  988. .id = PLAT8250_DEV_PLATFORM1,
  989. .dev = {
  990. .platform_data = dm365_serial1_platform_data,
  991. }
  992. },
  993. {
  994. }
  995. };
  996. static struct davinci_soc_info davinci_soc_info_dm365 = {
  997. .io_desc = dm365_io_desc,
  998. .io_desc_num = ARRAY_SIZE(dm365_io_desc),
  999. .jtag_id_reg = 0x01c40028,
  1000. .ids = dm365_ids,
  1001. .ids_num = ARRAY_SIZE(dm365_ids),
  1002. .cpu_clks = dm365_clks,
  1003. .psc_bases = dm365_psc_bases,
  1004. .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
  1005. .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
  1006. .pinmux_pins = dm365_pins,
  1007. .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
  1008. .intc_base = DAVINCI_ARM_INTC_BASE,
  1009. .intc_type = DAVINCI_INTC_TYPE_AINTC,
  1010. .intc_irq_prios = dm365_default_priorities,
  1011. .intc_irq_num = DAVINCI_N_AINTC_IRQ,
  1012. .timer_info = &dm365_timer_info,
  1013. .emac_pdata = &dm365_emac_pdata,
  1014. .sram_dma = 0x00010000,
  1015. .sram_len = SZ_32K,
  1016. };
  1017. void __init dm365_init_asp(void)
  1018. {
  1019. davinci_cfg_reg(DM365_MCBSP0_BDX);
  1020. davinci_cfg_reg(DM365_MCBSP0_X);
  1021. davinci_cfg_reg(DM365_MCBSP0_BFSX);
  1022. davinci_cfg_reg(DM365_MCBSP0_BDR);
  1023. davinci_cfg_reg(DM365_MCBSP0_R);
  1024. davinci_cfg_reg(DM365_MCBSP0_BFSR);
  1025. davinci_cfg_reg(DM365_EVT2_ASP_TX);
  1026. davinci_cfg_reg(DM365_EVT3_ASP_RX);
  1027. platform_device_register(&dm365_asp_device);
  1028. }
  1029. void __init dm365_init_vc(void)
  1030. {
  1031. davinci_cfg_reg(DM365_EVT2_VC_TX);
  1032. davinci_cfg_reg(DM365_EVT3_VC_RX);
  1033. platform_device_register(&dm365_vc_device);
  1034. }
  1035. void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
  1036. {
  1037. dm365_ks_device.dev.platform_data = pdata;
  1038. platform_device_register(&dm365_ks_device);
  1039. }
  1040. void __init dm365_init_rtc(void)
  1041. {
  1042. davinci_cfg_reg(DM365_INT_PRTCSS);
  1043. platform_device_register(&dm365_rtc_device);
  1044. }
  1045. void __init dm365_init(void)
  1046. {
  1047. davinci_common_init(&davinci_soc_info_dm365);
  1048. davinci_map_sysmod();
  1049. davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
  1050. }
  1051. static struct resource dm365_vpss_resources[] = {
  1052. {
  1053. /* VPSS ISP5 Base address */
  1054. .name = "isp5",
  1055. .start = 0x01c70000,
  1056. .end = 0x01c70000 + 0xff,
  1057. .flags = IORESOURCE_MEM,
  1058. },
  1059. {
  1060. /* VPSS CLK Base address */
  1061. .name = "vpss",
  1062. .start = 0x01c70200,
  1063. .end = 0x01c70200 + 0xff,
  1064. .flags = IORESOURCE_MEM,
  1065. },
  1066. };
  1067. static struct platform_device dm365_vpss_device = {
  1068. .name = "vpss",
  1069. .id = -1,
  1070. .dev.platform_data = "dm365_vpss",
  1071. .num_resources = ARRAY_SIZE(dm365_vpss_resources),
  1072. .resource = dm365_vpss_resources,
  1073. };
  1074. static struct resource vpfe_resources[] = {
  1075. {
  1076. .start = IRQ_VDINT0,
  1077. .end = IRQ_VDINT0,
  1078. .flags = IORESOURCE_IRQ,
  1079. },
  1080. {
  1081. .start = IRQ_VDINT1,
  1082. .end = IRQ_VDINT1,
  1083. .flags = IORESOURCE_IRQ,
  1084. },
  1085. };
  1086. static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
  1087. static struct platform_device vpfe_capture_dev = {
  1088. .name = CAPTURE_DRV_NAME,
  1089. .id = -1,
  1090. .num_resources = ARRAY_SIZE(vpfe_resources),
  1091. .resource = vpfe_resources,
  1092. .dev = {
  1093. .dma_mask = &vpfe_capture_dma_mask,
  1094. .coherent_dma_mask = DMA_BIT_MASK(32),
  1095. },
  1096. };
  1097. static void dm365_isif_setup_pinmux(void)
  1098. {
  1099. davinci_cfg_reg(DM365_VIN_CAM_WEN);
  1100. davinci_cfg_reg(DM365_VIN_CAM_VD);
  1101. davinci_cfg_reg(DM365_VIN_CAM_HD);
  1102. davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
  1103. davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
  1104. }
  1105. static struct resource isif_resource[] = {
  1106. /* ISIF Base address */
  1107. {
  1108. .start = 0x01c71000,
  1109. .end = 0x01c71000 + 0x1ff,
  1110. .flags = IORESOURCE_MEM,
  1111. },
  1112. /* ISIF Linearization table 0 */
  1113. {
  1114. .start = 0x1C7C000,
  1115. .end = 0x1C7C000 + 0x2ff,
  1116. .flags = IORESOURCE_MEM,
  1117. },
  1118. /* ISIF Linearization table 1 */
  1119. {
  1120. .start = 0x1C7C400,
  1121. .end = 0x1C7C400 + 0x2ff,
  1122. .flags = IORESOURCE_MEM,
  1123. },
  1124. };
  1125. static struct platform_device dm365_isif_dev = {
  1126. .name = "isif",
  1127. .id = -1,
  1128. .num_resources = ARRAY_SIZE(isif_resource),
  1129. .resource = isif_resource,
  1130. .dev = {
  1131. .dma_mask = &vpfe_capture_dma_mask,
  1132. .coherent_dma_mask = DMA_BIT_MASK(32),
  1133. .platform_data = dm365_isif_setup_pinmux,
  1134. },
  1135. };
  1136. static struct resource dm365_osd_resources[] = {
  1137. {
  1138. .start = DM365_OSD_BASE,
  1139. .end = DM365_OSD_BASE + 0xff,
  1140. .flags = IORESOURCE_MEM,
  1141. },
  1142. };
  1143. static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
  1144. static struct platform_device dm365_osd_dev = {
  1145. .name = DM365_VPBE_OSD_SUBDEV_NAME,
  1146. .id = -1,
  1147. .num_resources = ARRAY_SIZE(dm365_osd_resources),
  1148. .resource = dm365_osd_resources,
  1149. .dev = {
  1150. .dma_mask = &dm365_video_dma_mask,
  1151. .coherent_dma_mask = DMA_BIT_MASK(32),
  1152. },
  1153. };
  1154. static struct resource dm365_venc_resources[] = {
  1155. {
  1156. .start = IRQ_VENCINT,
  1157. .end = IRQ_VENCINT,
  1158. .flags = IORESOURCE_IRQ,
  1159. },
  1160. /* venc registers io space */
  1161. {
  1162. .start = DM365_VENC_BASE,
  1163. .end = DM365_VENC_BASE + 0x177,
  1164. .flags = IORESOURCE_MEM,
  1165. },
  1166. /* vdaccfg registers io space */
  1167. {
  1168. .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
  1169. .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
  1170. .flags = IORESOURCE_MEM,
  1171. },
  1172. };
  1173. static struct resource dm365_v4l2_disp_resources[] = {
  1174. {
  1175. .start = IRQ_VENCINT,
  1176. .end = IRQ_VENCINT,
  1177. .flags = IORESOURCE_IRQ,
  1178. },
  1179. /* venc registers io space */
  1180. {
  1181. .start = DM365_VENC_BASE,
  1182. .end = DM365_VENC_BASE + 0x177,
  1183. .flags = IORESOURCE_MEM,
  1184. },
  1185. };
  1186. static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
  1187. {
  1188. switch (if_type) {
  1189. case MEDIA_BUS_FMT_SGRBG8_1X8:
  1190. davinci_cfg_reg(DM365_VOUT_FIELD_G81);
  1191. davinci_cfg_reg(DM365_VOUT_COUTL_EN);
  1192. davinci_cfg_reg(DM365_VOUT_COUTH_EN);
  1193. break;
  1194. case MEDIA_BUS_FMT_YUYV10_1X20:
  1195. if (field)
  1196. davinci_cfg_reg(DM365_VOUT_FIELD);
  1197. else
  1198. davinci_cfg_reg(DM365_VOUT_FIELD_G81);
  1199. davinci_cfg_reg(DM365_VOUT_COUTL_EN);
  1200. davinci_cfg_reg(DM365_VOUT_COUTH_EN);
  1201. break;
  1202. default:
  1203. return -EINVAL;
  1204. }
  1205. return 0;
  1206. }
  1207. static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
  1208. unsigned int pclock)
  1209. {
  1210. void __iomem *vpss_clkctl_reg;
  1211. u32 val;
  1212. vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
  1213. switch (type) {
  1214. case VPBE_ENC_STD:
  1215. val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
  1216. break;
  1217. case VPBE_ENC_DV_TIMINGS:
  1218. if (pclock <= 27000000) {
  1219. val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
  1220. } else {
  1221. /* set sysclk4 to output 74.25 MHz from pll1 */
  1222. val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
  1223. VPSS_VENCCLKEN_ENABLE;
  1224. }
  1225. break;
  1226. default:
  1227. return -EINVAL;
  1228. }
  1229. writel(val, vpss_clkctl_reg);
  1230. return 0;
  1231. }
  1232. static struct platform_device dm365_vpbe_display = {
  1233. .name = "vpbe-v4l2",
  1234. .id = -1,
  1235. .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
  1236. .resource = dm365_v4l2_disp_resources,
  1237. .dev = {
  1238. .dma_mask = &dm365_video_dma_mask,
  1239. .coherent_dma_mask = DMA_BIT_MASK(32),
  1240. },
  1241. };
  1242. static struct venc_platform_data dm365_venc_pdata = {
  1243. .setup_pinmux = dm365_vpbe_setup_pinmux,
  1244. .setup_clock = dm365_venc_setup_clock,
  1245. };
  1246. static struct platform_device dm365_venc_dev = {
  1247. .name = DM365_VPBE_VENC_SUBDEV_NAME,
  1248. .id = -1,
  1249. .num_resources = ARRAY_SIZE(dm365_venc_resources),
  1250. .resource = dm365_venc_resources,
  1251. .dev = {
  1252. .dma_mask = &dm365_video_dma_mask,
  1253. .coherent_dma_mask = DMA_BIT_MASK(32),
  1254. .platform_data = (void *)&dm365_venc_pdata,
  1255. },
  1256. };
  1257. static struct platform_device dm365_vpbe_dev = {
  1258. .name = "vpbe_controller",
  1259. .id = -1,
  1260. .dev = {
  1261. .dma_mask = &dm365_video_dma_mask,
  1262. .coherent_dma_mask = DMA_BIT_MASK(32),
  1263. },
  1264. };
  1265. int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
  1266. struct vpbe_config *vpbe_cfg)
  1267. {
  1268. if (vpfe_cfg || vpbe_cfg)
  1269. platform_device_register(&dm365_vpss_device);
  1270. if (vpfe_cfg) {
  1271. vpfe_capture_dev.dev.platform_data = vpfe_cfg;
  1272. platform_device_register(&dm365_isif_dev);
  1273. platform_device_register(&vpfe_capture_dev);
  1274. }
  1275. if (vpbe_cfg) {
  1276. dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
  1277. platform_device_register(&dm365_osd_dev);
  1278. platform_device_register(&dm365_venc_dev);
  1279. platform_device_register(&dm365_vpbe_dev);
  1280. platform_device_register(&dm365_vpbe_display);
  1281. }
  1282. return 0;
  1283. }
  1284. static int __init dm365_init_devices(void)
  1285. {
  1286. int ret = 0;
  1287. if (!cpu_is_davinci_dm365())
  1288. return 0;
  1289. davinci_cfg_reg(DM365_INT_EDMA_CC);
  1290. platform_device_register(&dm365_edma_device);
  1291. platform_device_register(&dm365_mdio_device);
  1292. platform_device_register(&dm365_emac_device);
  1293. ret = davinci_init_wdt();
  1294. if (ret)
  1295. pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
  1296. return ret;
  1297. }
  1298. postcore_initcall(dm365_init_devices);