board-dm644x-evm.c 20 KB

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  1. /*
  2. * TI DaVinci EVM board support
  3. *
  4. * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  5. *
  6. * 2007 (c) MontaVista Software, Inc. This file is licensed under
  7. * the terms of the GNU General Public License version 2. This program
  8. * is licensed "as is" without any warranty of any kind, whether express
  9. * or implied.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/init.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/gpio.h>
  16. #include <linux/i2c.h>
  17. #include <linux/i2c/pcf857x.h>
  18. #include <linux/platform_data/at24.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/nand.h>
  21. #include <linux/mtd/partitions.h>
  22. #include <linux/mtd/physmap.h>
  23. #include <linux/phy.h>
  24. #include <linux/clk.h>
  25. #include <linux/videodev2.h>
  26. #include <linux/v4l2-dv-timings.h>
  27. #include <linux/export.h>
  28. #include <media/i2c/tvp514x.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/mach/arch.h>
  31. #include <mach/common.h>
  32. #include <linux/platform_data/i2c-davinci.h>
  33. #include <mach/serial.h>
  34. #include <mach/mux.h>
  35. #include <linux/platform_data/mtd-davinci.h>
  36. #include <linux/platform_data/mmc-davinci.h>
  37. #include <linux/platform_data/usb-davinci.h>
  38. #include <linux/platform_data/mtd-davinci-aemif.h>
  39. #include "davinci.h"
  40. #define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
  41. #define LXT971_PHY_ID (0x001378e2)
  42. #define LXT971_PHY_MASK (0xfffffff0)
  43. static struct mtd_partition davinci_evm_norflash_partitions[] = {
  44. /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
  45. {
  46. .name = "bootloader",
  47. .offset = 0,
  48. .size = 5 * SZ_64K,
  49. .mask_flags = MTD_WRITEABLE, /* force read-only */
  50. },
  51. /* bootloader params in the next 1 sectors */
  52. {
  53. .name = "params",
  54. .offset = MTDPART_OFS_APPEND,
  55. .size = SZ_64K,
  56. .mask_flags = 0,
  57. },
  58. /* kernel */
  59. {
  60. .name = "kernel",
  61. .offset = MTDPART_OFS_APPEND,
  62. .size = SZ_2M,
  63. .mask_flags = 0
  64. },
  65. /* file system */
  66. {
  67. .name = "filesystem",
  68. .offset = MTDPART_OFS_APPEND,
  69. .size = MTDPART_SIZ_FULL,
  70. .mask_flags = 0
  71. }
  72. };
  73. static struct physmap_flash_data davinci_evm_norflash_data = {
  74. .width = 2,
  75. .parts = davinci_evm_norflash_partitions,
  76. .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
  77. };
  78. /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
  79. * limits addresses to 16M, so using addresses past 16M will wrap */
  80. static struct resource davinci_evm_norflash_resource = {
  81. .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
  82. .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
  83. .flags = IORESOURCE_MEM,
  84. };
  85. static struct platform_device davinci_evm_norflash_device = {
  86. .name = "physmap-flash",
  87. .id = 0,
  88. .dev = {
  89. .platform_data = &davinci_evm_norflash_data,
  90. },
  91. .num_resources = 1,
  92. .resource = &davinci_evm_norflash_resource,
  93. };
  94. /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
  95. * It may used instead of the (default) NOR chip to boot, using TI's
  96. * tools to install the secondary boot loader (UBL) and U-Boot.
  97. */
  98. static struct mtd_partition davinci_evm_nandflash_partition[] = {
  99. /* Bootloader layout depends on whose u-boot is installed, but we
  100. * can hide all the details.
  101. * - block 0 for u-boot environment ... in mainline u-boot
  102. * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
  103. * - blocks 6...? for u-boot
  104. * - blocks 16..23 for u-boot environment ... in TI's u-boot
  105. */
  106. {
  107. .name = "bootloader",
  108. .offset = 0,
  109. .size = SZ_256K + SZ_128K,
  110. .mask_flags = MTD_WRITEABLE, /* force read-only */
  111. },
  112. /* Kernel */
  113. {
  114. .name = "kernel",
  115. .offset = MTDPART_OFS_APPEND,
  116. .size = SZ_4M,
  117. .mask_flags = 0,
  118. },
  119. /* File system (older GIT kernels started this on the 5MB mark) */
  120. {
  121. .name = "filesystem",
  122. .offset = MTDPART_OFS_APPEND,
  123. .size = MTDPART_SIZ_FULL,
  124. .mask_flags = 0,
  125. }
  126. /* A few blocks at end hold a flash BBT ... created by TI's CCS
  127. * using flashwriter_nand.out, but ignored by TI's versions of
  128. * Linux and u-boot. We boot faster by using them.
  129. */
  130. };
  131. static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
  132. .wsetup = 20,
  133. .wstrobe = 40,
  134. .whold = 20,
  135. .rsetup = 10,
  136. .rstrobe = 40,
  137. .rhold = 10,
  138. .ta = 40,
  139. };
  140. static struct davinci_nand_pdata davinci_evm_nandflash_data = {
  141. .parts = davinci_evm_nandflash_partition,
  142. .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
  143. .ecc_mode = NAND_ECC_HW,
  144. .ecc_bits = 1,
  145. .bbt_options = NAND_BBT_USE_FLASH,
  146. .timing = &davinci_evm_nandflash_timing,
  147. };
  148. static struct resource davinci_evm_nandflash_resource[] = {
  149. {
  150. .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
  151. .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
  152. .flags = IORESOURCE_MEM,
  153. }, {
  154. .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
  155. .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
  156. .flags = IORESOURCE_MEM,
  157. },
  158. };
  159. static struct platform_device davinci_evm_nandflash_device = {
  160. .name = "davinci_nand",
  161. .id = 0,
  162. .dev = {
  163. .platform_data = &davinci_evm_nandflash_data,
  164. },
  165. .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
  166. .resource = davinci_evm_nandflash_resource,
  167. };
  168. static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
  169. static struct platform_device davinci_fb_device = {
  170. .name = "davincifb",
  171. .id = -1,
  172. .dev = {
  173. .dma_mask = &davinci_fb_dma_mask,
  174. .coherent_dma_mask = DMA_BIT_MASK(32),
  175. },
  176. .num_resources = 0,
  177. };
  178. static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
  179. .clk_polarity = 0,
  180. .hs_polarity = 1,
  181. .vs_polarity = 1
  182. };
  183. #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
  184. /* Inputs available at the TVP5146 */
  185. static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
  186. {
  187. .index = 0,
  188. .name = "Composite",
  189. .type = V4L2_INPUT_TYPE_CAMERA,
  190. .std = TVP514X_STD_ALL,
  191. },
  192. {
  193. .index = 1,
  194. .name = "S-Video",
  195. .type = V4L2_INPUT_TYPE_CAMERA,
  196. .std = TVP514X_STD_ALL,
  197. },
  198. };
  199. /*
  200. * this is the route info for connecting each input to decoder
  201. * ouput that goes to vpfe. There is a one to one correspondence
  202. * with tvp5146_inputs
  203. */
  204. static struct vpfe_route dm644xevm_tvp5146_routes[] = {
  205. {
  206. .input = INPUT_CVBS_VI2B,
  207. .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
  208. },
  209. {
  210. .input = INPUT_SVIDEO_VI2C_VI1C,
  211. .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
  212. },
  213. };
  214. static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
  215. {
  216. .name = "tvp5146",
  217. .grp_id = 0,
  218. .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
  219. .inputs = dm644xevm_tvp5146_inputs,
  220. .routes = dm644xevm_tvp5146_routes,
  221. .can_route = 1,
  222. .ccdc_if_params = {
  223. .if_type = VPFE_BT656,
  224. .hdpol = VPFE_PINPOL_POSITIVE,
  225. .vdpol = VPFE_PINPOL_POSITIVE,
  226. },
  227. .board_info = {
  228. I2C_BOARD_INFO("tvp5146", 0x5d),
  229. .platform_data = &dm644xevm_tvp5146_pdata,
  230. },
  231. },
  232. };
  233. static struct vpfe_config dm644xevm_capture_cfg = {
  234. .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
  235. .i2c_adapter_id = 1,
  236. .sub_devs = dm644xevm_vpfe_sub_devs,
  237. .card_name = "DM6446 EVM",
  238. .ccdc = "DM6446 CCDC",
  239. };
  240. static struct platform_device rtc_dev = {
  241. .name = "rtc_davinci_evm",
  242. .id = -1,
  243. };
  244. /*----------------------------------------------------------------------*/
  245. #ifdef CONFIG_I2C
  246. /*
  247. * I2C GPIO expanders
  248. */
  249. #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
  250. /* U2 -- LEDs */
  251. static struct gpio_led evm_leds[] = {
  252. { .name = "DS8", .active_low = 1,
  253. .default_trigger = "heartbeat", },
  254. { .name = "DS7", .active_low = 1, },
  255. { .name = "DS6", .active_low = 1, },
  256. { .name = "DS5", .active_low = 1, },
  257. { .name = "DS4", .active_low = 1, },
  258. { .name = "DS3", .active_low = 1, },
  259. { .name = "DS2", .active_low = 1,
  260. .default_trigger = "mmc0", },
  261. { .name = "DS1", .active_low = 1,
  262. .default_trigger = "disk-activity", },
  263. };
  264. static const struct gpio_led_platform_data evm_led_data = {
  265. .num_leds = ARRAY_SIZE(evm_leds),
  266. .leds = evm_leds,
  267. };
  268. static struct platform_device *evm_led_dev;
  269. static int
  270. evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
  271. {
  272. struct gpio_led *leds = evm_leds;
  273. int status;
  274. while (ngpio--) {
  275. leds->gpio = gpio++;
  276. leds++;
  277. }
  278. /* what an extremely annoying way to be forced to handle
  279. * device unregistration ...
  280. */
  281. evm_led_dev = platform_device_alloc("leds-gpio", 0);
  282. platform_device_add_data(evm_led_dev,
  283. &evm_led_data, sizeof evm_led_data);
  284. evm_led_dev->dev.parent = &client->dev;
  285. status = platform_device_add(evm_led_dev);
  286. if (status < 0) {
  287. platform_device_put(evm_led_dev);
  288. evm_led_dev = NULL;
  289. }
  290. return status;
  291. }
  292. static int
  293. evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
  294. {
  295. if (evm_led_dev) {
  296. platform_device_unregister(evm_led_dev);
  297. evm_led_dev = NULL;
  298. }
  299. return 0;
  300. }
  301. static struct pcf857x_platform_data pcf_data_u2 = {
  302. .gpio_base = PCF_Uxx_BASE(0),
  303. .setup = evm_led_setup,
  304. .teardown = evm_led_teardown,
  305. };
  306. /* U18 - A/V clock generator and user switch */
  307. static int sw_gpio;
  308. static ssize_t
  309. sw_show(struct device *d, struct device_attribute *a, char *buf)
  310. {
  311. char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
  312. strcpy(buf, s);
  313. return strlen(s);
  314. }
  315. static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
  316. static int
  317. evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
  318. {
  319. int status;
  320. /* export dip switch option */
  321. sw_gpio = gpio + 7;
  322. status = gpio_request(sw_gpio, "user_sw");
  323. if (status == 0)
  324. status = gpio_direction_input(sw_gpio);
  325. if (status == 0)
  326. status = device_create_file(&client->dev, &dev_attr_user_sw);
  327. else
  328. gpio_free(sw_gpio);
  329. if (status != 0)
  330. sw_gpio = -EINVAL;
  331. /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
  332. gpio_request(gpio + 3, "pll_fs2");
  333. gpio_direction_output(gpio + 3, 0);
  334. gpio_request(gpio + 2, "pll_fs1");
  335. gpio_direction_output(gpio + 2, 0);
  336. gpio_request(gpio + 1, "pll_sr");
  337. gpio_direction_output(gpio + 1, 0);
  338. return 0;
  339. }
  340. static int
  341. evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
  342. {
  343. gpio_free(gpio + 1);
  344. gpio_free(gpio + 2);
  345. gpio_free(gpio + 3);
  346. if (sw_gpio > 0) {
  347. device_remove_file(&client->dev, &dev_attr_user_sw);
  348. gpio_free(sw_gpio);
  349. }
  350. return 0;
  351. }
  352. static struct pcf857x_platform_data pcf_data_u18 = {
  353. .gpio_base = PCF_Uxx_BASE(1),
  354. .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
  355. .setup = evm_u18_setup,
  356. .teardown = evm_u18_teardown,
  357. };
  358. /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
  359. static int
  360. evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
  361. {
  362. /* p0 = nDRV_VBUS (initial: don't supply it) */
  363. gpio_request(gpio + 0, "nDRV_VBUS");
  364. gpio_direction_output(gpio + 0, 1);
  365. /* p1 = VDDIMX_EN */
  366. gpio_request(gpio + 1, "VDDIMX_EN");
  367. gpio_direction_output(gpio + 1, 1);
  368. /* p2 = VLYNQ_EN */
  369. gpio_request(gpio + 2, "VLYNQ_EN");
  370. gpio_direction_output(gpio + 2, 1);
  371. /* p3 = n3V3_CF_RESET (initial: stay in reset) */
  372. gpio_request(gpio + 3, "nCF_RESET");
  373. gpio_direction_output(gpio + 3, 0);
  374. /* (p4 unused) */
  375. /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
  376. gpio_request(gpio + 5, "WLAN_RESET");
  377. gpio_direction_output(gpio + 5, 1);
  378. /* p6 = nATA_SEL (initial: select) */
  379. gpio_request(gpio + 6, "nATA_SEL");
  380. gpio_direction_output(gpio + 6, 0);
  381. /* p7 = nCF_SEL (initial: deselect) */
  382. gpio_request(gpio + 7, "nCF_SEL");
  383. gpio_direction_output(gpio + 7, 1);
  384. return 0;
  385. }
  386. static int
  387. evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
  388. {
  389. gpio_free(gpio + 7);
  390. gpio_free(gpio + 6);
  391. gpio_free(gpio + 5);
  392. gpio_free(gpio + 3);
  393. gpio_free(gpio + 2);
  394. gpio_free(gpio + 1);
  395. gpio_free(gpio + 0);
  396. return 0;
  397. }
  398. static struct pcf857x_platform_data pcf_data_u35 = {
  399. .gpio_base = PCF_Uxx_BASE(2),
  400. .setup = evm_u35_setup,
  401. .teardown = evm_u35_teardown,
  402. };
  403. /*----------------------------------------------------------------------*/
  404. /* Most of this EEPROM is unused, but U-Boot uses some data:
  405. * - 0x7f00, 6 bytes Ethernet Address
  406. * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
  407. * - ... newer boards may have more
  408. */
  409. static struct at24_platform_data eeprom_info = {
  410. .byte_len = (256*1024) / 8,
  411. .page_size = 64,
  412. .flags = AT24_FLAG_ADDR16,
  413. .setup = davinci_get_mac_addr,
  414. .context = (void *)0x7f00,
  415. };
  416. /*
  417. * MSP430 supports RTC, card detection, input from IR remote, and
  418. * a bit more. It triggers interrupts on GPIO(7) from pressing
  419. * buttons on the IR remote, and for card detect switches.
  420. */
  421. static struct i2c_client *dm6446evm_msp;
  422. static int dm6446evm_msp_probe(struct i2c_client *client,
  423. const struct i2c_device_id *id)
  424. {
  425. dm6446evm_msp = client;
  426. return 0;
  427. }
  428. static int dm6446evm_msp_remove(struct i2c_client *client)
  429. {
  430. dm6446evm_msp = NULL;
  431. return 0;
  432. }
  433. static const struct i2c_device_id dm6446evm_msp_ids[] = {
  434. { "dm6446evm_msp", 0, },
  435. { /* end of list */ },
  436. };
  437. static struct i2c_driver dm6446evm_msp_driver = {
  438. .driver.name = "dm6446evm_msp",
  439. .id_table = dm6446evm_msp_ids,
  440. .probe = dm6446evm_msp_probe,
  441. .remove = dm6446evm_msp_remove,
  442. };
  443. static int dm6444evm_msp430_get_pins(void)
  444. {
  445. static const char txbuf[2] = { 2, 4, };
  446. char buf[4];
  447. struct i2c_msg msg[2] = {
  448. {
  449. .flags = 0,
  450. .len = 2,
  451. .buf = (void __force *)txbuf,
  452. },
  453. {
  454. .flags = I2C_M_RD,
  455. .len = 4,
  456. .buf = buf,
  457. },
  458. };
  459. int status;
  460. if (!dm6446evm_msp)
  461. return -ENXIO;
  462. msg[0].addr = dm6446evm_msp->addr;
  463. msg[1].addr = dm6446evm_msp->addr;
  464. /* Command 4 == get input state, returns port 2 and port3 data
  465. * S Addr W [A] len=2 [A] cmd=4 [A]
  466. * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
  467. */
  468. status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
  469. if (status < 0)
  470. return status;
  471. dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
  472. return (buf[3] << 8) | buf[2];
  473. }
  474. static int dm6444evm_mmc_get_cd(int module)
  475. {
  476. int status = dm6444evm_msp430_get_pins();
  477. return (status < 0) ? status : !(status & BIT(1));
  478. }
  479. static int dm6444evm_mmc_get_ro(int module)
  480. {
  481. int status = dm6444evm_msp430_get_pins();
  482. return (status < 0) ? status : status & BIT(6 + 8);
  483. }
  484. static struct davinci_mmc_config dm6446evm_mmc_config = {
  485. .get_cd = dm6444evm_mmc_get_cd,
  486. .get_ro = dm6444evm_mmc_get_ro,
  487. .wires = 4,
  488. };
  489. static struct i2c_board_info __initdata i2c_info[] = {
  490. {
  491. I2C_BOARD_INFO("dm6446evm_msp", 0x23),
  492. },
  493. {
  494. I2C_BOARD_INFO("pcf8574", 0x38),
  495. .platform_data = &pcf_data_u2,
  496. },
  497. {
  498. I2C_BOARD_INFO("pcf8574", 0x39),
  499. .platform_data = &pcf_data_u18,
  500. },
  501. {
  502. I2C_BOARD_INFO("pcf8574", 0x3a),
  503. .platform_data = &pcf_data_u35,
  504. },
  505. {
  506. I2C_BOARD_INFO("24c256", 0x50),
  507. .platform_data = &eeprom_info,
  508. },
  509. {
  510. I2C_BOARD_INFO("tlv320aic33", 0x1b),
  511. },
  512. };
  513. /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
  514. * which requires 100 usec of idle bus after i2c writes sent to it.
  515. */
  516. static struct davinci_i2c_platform_data i2c_pdata = {
  517. .bus_freq = 20 /* kHz */,
  518. .bus_delay = 100 /* usec */,
  519. .sda_pin = 44,
  520. .scl_pin = 43,
  521. };
  522. static void __init evm_init_i2c(void)
  523. {
  524. davinci_init_i2c(&i2c_pdata);
  525. i2c_add_driver(&dm6446evm_msp_driver);
  526. i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
  527. }
  528. #endif
  529. #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
  530. /* venc standard timings */
  531. static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
  532. {
  533. .name = "ntsc",
  534. .timings_type = VPBE_ENC_STD,
  535. .std_id = V4L2_STD_NTSC,
  536. .interlaced = 1,
  537. .xres = 720,
  538. .yres = 480,
  539. .aspect = {11, 10},
  540. .fps = {30000, 1001},
  541. .left_margin = 0x79,
  542. .upper_margin = 0x10,
  543. },
  544. {
  545. .name = "pal",
  546. .timings_type = VPBE_ENC_STD,
  547. .std_id = V4L2_STD_PAL,
  548. .interlaced = 1,
  549. .xres = 720,
  550. .yres = 576,
  551. .aspect = {54, 59},
  552. .fps = {25, 1},
  553. .left_margin = 0x7e,
  554. .upper_margin = 0x16,
  555. },
  556. };
  557. /* venc dv preset timings */
  558. static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
  559. {
  560. .name = "480p59_94",
  561. .timings_type = VPBE_ENC_DV_TIMINGS,
  562. .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
  563. .interlaced = 0,
  564. .xres = 720,
  565. .yres = 480,
  566. .aspect = {1, 1},
  567. .fps = {5994, 100},
  568. .left_margin = 0x80,
  569. .upper_margin = 0x20,
  570. },
  571. {
  572. .name = "576p50",
  573. .timings_type = VPBE_ENC_DV_TIMINGS,
  574. .dv_timings = V4L2_DV_BT_CEA_720X576P50,
  575. .interlaced = 0,
  576. .xres = 720,
  577. .yres = 576,
  578. .aspect = {1, 1},
  579. .fps = {50, 1},
  580. .left_margin = 0x7e,
  581. .upper_margin = 0x30,
  582. },
  583. };
  584. /*
  585. * The outputs available from VPBE + encoders. Keep the order same
  586. * as that of encoders. First those from venc followed by that from
  587. * encoders. Index in the output refers to index on a particular encoder.
  588. * Driver uses this index to pass it to encoder when it supports more
  589. * than one output. Userspace applications use index of the array to
  590. * set an output.
  591. */
  592. static struct vpbe_output dm644xevm_vpbe_outputs[] = {
  593. {
  594. .output = {
  595. .index = 0,
  596. .name = "Composite",
  597. .type = V4L2_OUTPUT_TYPE_ANALOG,
  598. .std = VENC_STD_ALL,
  599. .capabilities = V4L2_OUT_CAP_STD,
  600. },
  601. .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
  602. .default_mode = "ntsc",
  603. .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
  604. .modes = dm644xevm_enc_std_timing,
  605. },
  606. {
  607. .output = {
  608. .index = 1,
  609. .name = "Component",
  610. .type = V4L2_OUTPUT_TYPE_ANALOG,
  611. .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
  612. },
  613. .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
  614. .default_mode = "480p59_94",
  615. .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
  616. .modes = dm644xevm_enc_preset_timing,
  617. },
  618. };
  619. static struct vpbe_config dm644xevm_display_cfg = {
  620. .module_name = "dm644x-vpbe-display",
  621. .i2c_adapter_id = 1,
  622. .osd = {
  623. .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
  624. },
  625. .venc = {
  626. .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
  627. },
  628. .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
  629. .outputs = dm644xevm_vpbe_outputs,
  630. };
  631. static struct platform_device *davinci_evm_devices[] __initdata = {
  632. &davinci_fb_device,
  633. &rtc_dev,
  634. };
  635. static void __init
  636. davinci_evm_map_io(void)
  637. {
  638. dm644x_init();
  639. }
  640. static int davinci_phy_fixup(struct phy_device *phydev)
  641. {
  642. unsigned int control;
  643. /* CRITICAL: Fix for increasing PHY signal drive strength for
  644. * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
  645. * signal strength was low causing TX to fail randomly. The
  646. * fix is to Set bit 11 (Increased MII drive strength) of PHY
  647. * register 26 (Digital Config register) on this phy. */
  648. control = phy_read(phydev, 26);
  649. phy_write(phydev, 26, (control | 0x800));
  650. return 0;
  651. }
  652. #define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
  653. #define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
  654. #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
  655. static __init void davinci_evm_init(void)
  656. {
  657. int ret;
  658. struct clk *aemif_clk;
  659. struct davinci_soc_info *soc_info = &davinci_soc_info;
  660. ret = dm644x_gpio_register();
  661. if (ret)
  662. pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
  663. aemif_clk = clk_get(NULL, "aemif");
  664. clk_prepare_enable(aemif_clk);
  665. if (HAS_ATA) {
  666. if (HAS_NAND || HAS_NOR)
  667. pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
  668. "\tDisable IDE for NAND/NOR support\n");
  669. davinci_init_ide();
  670. } else if (HAS_NAND || HAS_NOR) {
  671. davinci_cfg_reg(DM644X_HPIEN_DISABLE);
  672. davinci_cfg_reg(DM644X_ATAEN_DISABLE);
  673. /* only one device will be jumpered and detected */
  674. if (HAS_NAND) {
  675. platform_device_register(&davinci_evm_nandflash_device);
  676. if (davinci_aemif_setup(&davinci_evm_nandflash_device))
  677. pr_warn("%s: Cannot configure AEMIF\n",
  678. __func__);
  679. #ifdef CONFIG_I2C
  680. evm_leds[7].default_trigger = "nand-disk";
  681. #endif
  682. if (HAS_NOR)
  683. pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
  684. } else if (HAS_NOR)
  685. platform_device_register(&davinci_evm_norflash_device);
  686. }
  687. platform_add_devices(davinci_evm_devices,
  688. ARRAY_SIZE(davinci_evm_devices));
  689. #ifdef CONFIG_I2C
  690. evm_init_i2c();
  691. davinci_setup_mmc(0, &dm6446evm_mmc_config);
  692. #endif
  693. dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
  694. davinci_serial_init(dm644x_serial_device);
  695. dm644x_init_asp();
  696. /* irlml6401 switches over 1A, in under 8 msec */
  697. davinci_setup_usb(1000, 8);
  698. if (IS_BUILTIN(CONFIG_PHYLIB)) {
  699. soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
  700. /* Register the fixup for PHY on DaVinci */
  701. phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
  702. davinci_phy_fixup);
  703. }
  704. }
  705. MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
  706. /* Maintainer: MontaVista Software <source@mvista.com> */
  707. .atag_offset = 0x100,
  708. .map_io = davinci_evm_map_io,
  709. .init_irq = davinci_irq_init,
  710. .init_time = davinci_timer_init,
  711. .init_machine = davinci_evm_init,
  712. .init_late = davinci_init_late,
  713. .dma_zone_size = SZ_128M,
  714. .restart = davinci_restart,
  715. MACHINE_END