bios32.c 16 KB

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  1. /*
  2. * linux/arch/arm/kernel/bios32.c
  3. *
  4. * PCI bios-type initialisation for PCI machines
  5. *
  6. * Bits taken from various places.
  7. */
  8. #include <linux/export.h>
  9. #include <linux/kernel.h>
  10. #include <linux/pci.h>
  11. #include <linux/slab.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <asm/mach-types.h>
  15. #include <asm/mach/map.h>
  16. #include <asm/mach/pci.h>
  17. static int debug_pci;
  18. /*
  19. * We can't use pci_get_device() here since we are
  20. * called from interrupt context.
  21. */
  22. static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
  23. {
  24. struct pci_dev *dev;
  25. list_for_each_entry(dev, &bus->devices, bus_list) {
  26. u16 status;
  27. /*
  28. * ignore host bridge - we handle
  29. * that separately
  30. */
  31. if (dev->bus->number == 0 && dev->devfn == 0)
  32. continue;
  33. pci_read_config_word(dev, PCI_STATUS, &status);
  34. if (status == 0xffff)
  35. continue;
  36. if ((status & status_mask) == 0)
  37. continue;
  38. /* clear the status errors */
  39. pci_write_config_word(dev, PCI_STATUS, status & status_mask);
  40. if (warn)
  41. printk("(%s: %04X) ", pci_name(dev), status);
  42. }
  43. list_for_each_entry(dev, &bus->devices, bus_list)
  44. if (dev->subordinate)
  45. pcibios_bus_report_status(dev->subordinate, status_mask, warn);
  46. }
  47. void pcibios_report_status(u_int status_mask, int warn)
  48. {
  49. struct pci_bus *bus;
  50. list_for_each_entry(bus, &pci_root_buses, node)
  51. pcibios_bus_report_status(bus, status_mask, warn);
  52. }
  53. /*
  54. * We don't use this to fix the device, but initialisation of it.
  55. * It's not the correct use for this, but it works.
  56. * Note that the arbiter/ISA bridge appears to be buggy, specifically in
  57. * the following area:
  58. * 1. park on CPU
  59. * 2. ISA bridge ping-pong
  60. * 3. ISA bridge master handling of target RETRY
  61. *
  62. * Bug 3 is responsible for the sound DMA grinding to a halt. We now
  63. * live with bug 2.
  64. */
  65. static void pci_fixup_83c553(struct pci_dev *dev)
  66. {
  67. /*
  68. * Set memory region to start at address 0, and enable IO
  69. */
  70. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
  71. pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
  72. dev->resource[0].end -= dev->resource[0].start;
  73. dev->resource[0].start = 0;
  74. /*
  75. * All memory requests from ISA to be channelled to PCI
  76. */
  77. pci_write_config_byte(dev, 0x48, 0xff);
  78. /*
  79. * Enable ping-pong on bus master to ISA bridge transactions.
  80. * This improves the sound DMA substantially. The fixed
  81. * priority arbiter also helps (see below).
  82. */
  83. pci_write_config_byte(dev, 0x42, 0x01);
  84. /*
  85. * Enable PCI retry
  86. */
  87. pci_write_config_byte(dev, 0x40, 0x22);
  88. /*
  89. * We used to set the arbiter to "park on last master" (bit
  90. * 1 set), but unfortunately the CyberPro does not park the
  91. * bus. We must therefore park on CPU. Unfortunately, this
  92. * may trigger yet another bug in the 553.
  93. */
  94. pci_write_config_byte(dev, 0x83, 0x02);
  95. /*
  96. * Make the ISA DMA request lowest priority, and disable
  97. * rotating priorities completely.
  98. */
  99. pci_write_config_byte(dev, 0x80, 0x11);
  100. pci_write_config_byte(dev, 0x81, 0x00);
  101. /*
  102. * Route INTA input to IRQ 11, and set IRQ11 to be level
  103. * sensitive.
  104. */
  105. pci_write_config_word(dev, 0x44, 0xb000);
  106. outb(0x08, 0x4d1);
  107. }
  108. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
  109. static void pci_fixup_unassign(struct pci_dev *dev)
  110. {
  111. dev->resource[0].end -= dev->resource[0].start;
  112. dev->resource[0].start = 0;
  113. }
  114. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
  115. /*
  116. * Prevent the PCI layer from seeing the resources allocated to this device
  117. * if it is the host bridge by marking it as such. These resources are of
  118. * no consequence to the PCI layer (they are handled elsewhere).
  119. */
  120. static void pci_fixup_dec21285(struct pci_dev *dev)
  121. {
  122. int i;
  123. if (dev->devfn == 0) {
  124. dev->class &= 0xff;
  125. dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
  126. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  127. dev->resource[i].start = 0;
  128. dev->resource[i].end = 0;
  129. dev->resource[i].flags = 0;
  130. }
  131. }
  132. }
  133. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
  134. /*
  135. * PCI IDE controllers use non-standard I/O port decoding, respect it.
  136. */
  137. static void pci_fixup_ide_bases(struct pci_dev *dev)
  138. {
  139. struct resource *r;
  140. int i;
  141. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
  142. return;
  143. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  144. r = dev->resource + i;
  145. if ((r->start & ~0x80) == 0x374) {
  146. r->start |= 2;
  147. r->end = r->start;
  148. }
  149. }
  150. }
  151. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
  152. /*
  153. * Put the DEC21142 to sleep
  154. */
  155. static void pci_fixup_dec21142(struct pci_dev *dev)
  156. {
  157. pci_write_config_dword(dev, 0x40, 0x80000000);
  158. }
  159. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
  160. /*
  161. * The CY82C693 needs some rather major fixups to ensure that it does
  162. * the right thing. Idea from the Alpha people, with a few additions.
  163. *
  164. * We ensure that the IDE base registers are set to 1f0/3f4 for the
  165. * primary bus, and 170/374 for the secondary bus. Also, hide them
  166. * from the PCI subsystem view as well so we won't try to perform
  167. * our own auto-configuration on them.
  168. *
  169. * In addition, we ensure that the PCI IDE interrupts are routed to
  170. * IRQ 14 and IRQ 15 respectively.
  171. *
  172. * The above gets us to a point where the IDE on this device is
  173. * functional. However, The CY82C693U _does not work_ in bus
  174. * master mode without locking the PCI bus solid.
  175. */
  176. static void pci_fixup_cy82c693(struct pci_dev *dev)
  177. {
  178. if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
  179. u32 base0, base1;
  180. if (dev->class & 0x80) { /* primary */
  181. base0 = 0x1f0;
  182. base1 = 0x3f4;
  183. } else { /* secondary */
  184. base0 = 0x170;
  185. base1 = 0x374;
  186. }
  187. pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
  188. base0 | PCI_BASE_ADDRESS_SPACE_IO);
  189. pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
  190. base1 | PCI_BASE_ADDRESS_SPACE_IO);
  191. dev->resource[0].start = 0;
  192. dev->resource[0].end = 0;
  193. dev->resource[0].flags = 0;
  194. dev->resource[1].start = 0;
  195. dev->resource[1].end = 0;
  196. dev->resource[1].flags = 0;
  197. } else if (PCI_FUNC(dev->devfn) == 0) {
  198. /*
  199. * Setup IDE IRQ routing.
  200. */
  201. pci_write_config_byte(dev, 0x4b, 14);
  202. pci_write_config_byte(dev, 0x4c, 15);
  203. /*
  204. * Disable FREQACK handshake, enable USB.
  205. */
  206. pci_write_config_byte(dev, 0x4d, 0x41);
  207. /*
  208. * Enable PCI retry, and PCI post-write buffer.
  209. */
  210. pci_write_config_byte(dev, 0x44, 0x17);
  211. /*
  212. * Enable ISA master and DMA post write buffering.
  213. */
  214. pci_write_config_byte(dev, 0x45, 0x03);
  215. }
  216. }
  217. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
  218. static void pci_fixup_it8152(struct pci_dev *dev)
  219. {
  220. int i;
  221. /* fixup for ITE 8152 devices */
  222. /* FIXME: add defines for class 0x68000 and 0x80103 */
  223. if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
  224. dev->class == 0x68000 ||
  225. dev->class == 0x80103) {
  226. for (i = 0; i < PCI_NUM_RESOURCES; i++) {
  227. dev->resource[i].start = 0;
  228. dev->resource[i].end = 0;
  229. dev->resource[i].flags = 0;
  230. }
  231. }
  232. }
  233. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
  234. /*
  235. * If the bus contains any of these devices, then we must not turn on
  236. * parity checking of any kind. Currently this is CyberPro 20x0 only.
  237. */
  238. static inline int pdev_bad_for_parity(struct pci_dev *dev)
  239. {
  240. return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
  241. (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
  242. dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
  243. (dev->vendor == PCI_VENDOR_ID_ITE &&
  244. dev->device == PCI_DEVICE_ID_ITE_8152));
  245. }
  246. /*
  247. * pcibios_fixup_bus - Called after each bus is probed,
  248. * but before its children are examined.
  249. */
  250. void pcibios_fixup_bus(struct pci_bus *bus)
  251. {
  252. struct pci_dev *dev;
  253. u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
  254. /*
  255. * Walk the devices on this bus, working out what we can
  256. * and can't support.
  257. */
  258. list_for_each_entry(dev, &bus->devices, bus_list) {
  259. u16 status;
  260. pci_read_config_word(dev, PCI_STATUS, &status);
  261. /*
  262. * If any device on this bus does not support fast back
  263. * to back transfers, then the bus as a whole is not able
  264. * to support them. Having fast back to back transfers
  265. * on saves us one PCI cycle per transaction.
  266. */
  267. if (!(status & PCI_STATUS_FAST_BACK))
  268. features &= ~PCI_COMMAND_FAST_BACK;
  269. if (pdev_bad_for_parity(dev))
  270. features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  271. switch (dev->class >> 8) {
  272. case PCI_CLASS_BRIDGE_PCI:
  273. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
  274. status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
  275. status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
  276. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
  277. break;
  278. case PCI_CLASS_BRIDGE_CARDBUS:
  279. pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
  280. status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
  281. pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
  282. break;
  283. }
  284. }
  285. /*
  286. * Now walk the devices again, this time setting them up.
  287. */
  288. list_for_each_entry(dev, &bus->devices, bus_list) {
  289. u16 cmd;
  290. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  291. cmd |= features;
  292. pci_write_config_word(dev, PCI_COMMAND, cmd);
  293. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
  294. L1_CACHE_BYTES >> 2);
  295. }
  296. /*
  297. * Propagate the flags to the PCI bridge.
  298. */
  299. if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  300. if (features & PCI_COMMAND_FAST_BACK)
  301. bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
  302. if (features & PCI_COMMAND_PARITY)
  303. bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
  304. }
  305. /*
  306. * Report what we did for this bus
  307. */
  308. pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
  309. bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
  310. }
  311. EXPORT_SYMBOL(pcibios_fixup_bus);
  312. /*
  313. * Swizzle the device pin each time we cross a bridge. If a platform does
  314. * not provide a swizzle function, we perform the standard PCI swizzling.
  315. *
  316. * The default swizzling walks up the bus tree one level at a time, applying
  317. * the standard swizzle function at each step, stopping when it finds the PCI
  318. * root bus. This will return the slot number of the bridge device on the
  319. * root bus and the interrupt pin on that device which should correspond
  320. * with the downstream device interrupt.
  321. *
  322. * Platforms may override this, in which case the slot and pin returned
  323. * depend entirely on the platform code. However, please note that the
  324. * PCI standard swizzle is implemented on plug-in cards and Cardbus based
  325. * PCI extenders, so it can not be ignored.
  326. */
  327. static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
  328. {
  329. struct pci_sys_data *sys = dev->sysdata;
  330. int slot, oldpin = *pin;
  331. if (sys->swizzle)
  332. slot = sys->swizzle(dev, pin);
  333. else
  334. slot = pci_common_swizzle(dev, pin);
  335. if (debug_pci)
  336. printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
  337. pci_name(dev), oldpin, *pin, slot);
  338. return slot;
  339. }
  340. /*
  341. * Map a slot/pin to an IRQ.
  342. */
  343. static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  344. {
  345. struct pci_sys_data *sys = dev->sysdata;
  346. int irq = -1;
  347. if (sys->map_irq)
  348. irq = sys->map_irq(dev, slot, pin);
  349. if (debug_pci)
  350. printk("PCI: %s mapping slot %d pin %d => irq %d\n",
  351. pci_name(dev), slot, pin, irq);
  352. return irq;
  353. }
  354. static int pcibios_init_resource(int busnr, struct pci_sys_data *sys,
  355. int io_optional)
  356. {
  357. int ret;
  358. struct resource_entry *window;
  359. if (list_empty(&sys->resources)) {
  360. pci_add_resource_offset(&sys->resources,
  361. &iomem_resource, sys->mem_offset);
  362. }
  363. /*
  364. * If a platform says I/O port support is optional, we don't add
  365. * the default I/O space. The platform is responsible for adding
  366. * any I/O space it needs.
  367. */
  368. if (io_optional)
  369. return 0;
  370. resource_list_for_each_entry(window, &sys->resources)
  371. if (resource_type(window->res) == IORESOURCE_IO)
  372. return 0;
  373. sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
  374. sys->io_res.end = (busnr + 1) * SZ_64K - 1;
  375. sys->io_res.flags = IORESOURCE_IO;
  376. sys->io_res.name = sys->io_res_name;
  377. sprintf(sys->io_res_name, "PCI%d I/O", busnr);
  378. ret = request_resource(&ioport_resource, &sys->io_res);
  379. if (ret) {
  380. pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
  381. return ret;
  382. }
  383. pci_add_resource_offset(&sys->resources, &sys->io_res,
  384. sys->io_offset);
  385. return 0;
  386. }
  387. static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
  388. struct list_head *head)
  389. {
  390. struct pci_sys_data *sys = NULL;
  391. int ret;
  392. int nr, busnr;
  393. for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
  394. sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
  395. if (WARN(!sys, "PCI: unable to allocate sys data!"))
  396. break;
  397. sys->busnr = busnr;
  398. sys->swizzle = hw->swizzle;
  399. sys->map_irq = hw->map_irq;
  400. INIT_LIST_HEAD(&sys->resources);
  401. if (hw->private_data)
  402. sys->private_data = hw->private_data[nr];
  403. ret = hw->setup(nr, sys);
  404. if (ret > 0) {
  405. struct pci_host_bridge *host_bridge;
  406. ret = pcibios_init_resource(nr, sys, hw->io_optional);
  407. if (ret) {
  408. kfree(sys);
  409. break;
  410. }
  411. if (hw->scan)
  412. sys->bus = hw->scan(nr, sys);
  413. else
  414. sys->bus = pci_scan_root_bus_msi(parent,
  415. sys->busnr, hw->ops, sys,
  416. &sys->resources, hw->msi_ctrl);
  417. if (WARN(!sys->bus, "PCI: unable to scan bus!")) {
  418. kfree(sys);
  419. break;
  420. }
  421. busnr = sys->bus->busn_res.end + 1;
  422. list_add(&sys->node, head);
  423. host_bridge = pci_find_host_bridge(sys->bus);
  424. host_bridge->align_resource = hw->align_resource;
  425. } else {
  426. kfree(sys);
  427. if (ret < 0)
  428. break;
  429. }
  430. }
  431. }
  432. void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
  433. {
  434. struct pci_sys_data *sys;
  435. LIST_HEAD(head);
  436. pci_add_flags(PCI_REASSIGN_ALL_RSRC);
  437. if (hw->preinit)
  438. hw->preinit();
  439. pcibios_init_hw(parent, hw, &head);
  440. if (hw->postinit)
  441. hw->postinit();
  442. pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
  443. list_for_each_entry(sys, &head, node) {
  444. struct pci_bus *bus = sys->bus;
  445. /*
  446. * We insert PCI resources into the iomem_resource and
  447. * ioport_resource trees in either pci_bus_claim_resources()
  448. * or pci_bus_assign_resources().
  449. */
  450. if (pci_has_flag(PCI_PROBE_ONLY)) {
  451. pci_bus_claim_resources(bus);
  452. } else {
  453. struct pci_bus *child;
  454. pci_bus_size_bridges(bus);
  455. pci_bus_assign_resources(bus);
  456. list_for_each_entry(child, &bus->children, node)
  457. pcie_bus_configure_settings(child);
  458. }
  459. pci_bus_add_devices(bus);
  460. }
  461. }
  462. #ifndef CONFIG_PCI_HOST_ITE8152
  463. void pcibios_set_master(struct pci_dev *dev)
  464. {
  465. /* No special bus mastering setup handling */
  466. }
  467. #endif
  468. char * __init pcibios_setup(char *str)
  469. {
  470. if (!strcmp(str, "debug")) {
  471. debug_pci = 1;
  472. return NULL;
  473. }
  474. return str;
  475. }
  476. /*
  477. * From arch/i386/kernel/pci-i386.c:
  478. *
  479. * We need to avoid collisions with `mirrored' VGA ports
  480. * and other strange ISA hardware, so we always want the
  481. * addresses to be allocated in the 0x000-0x0ff region
  482. * modulo 0x400.
  483. *
  484. * Why? Because some silly external IO cards only decode
  485. * the low 10 bits of the IO address. The 0x00-0xff region
  486. * is reserved for motherboard devices that decode all 16
  487. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  488. * but we want to try to avoid allocating at 0x2900-0x2bff
  489. * which might be mirrored at 0x0100-0x03ff..
  490. */
  491. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  492. resource_size_t size, resource_size_t align)
  493. {
  494. struct pci_dev *dev = data;
  495. resource_size_t start = res->start;
  496. struct pci_host_bridge *host_bridge;
  497. if (res->flags & IORESOURCE_IO && start & 0x300)
  498. start = (start + 0x3ff) & ~0x3ff;
  499. start = (start + align - 1) & ~(align - 1);
  500. host_bridge = pci_find_host_bridge(dev->bus);
  501. if (host_bridge->align_resource)
  502. return host_bridge->align_resource(dev, res,
  503. start, size, align);
  504. return start;
  505. }
  506. int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  507. enum pci_mmap_state mmap_state, int write_combine)
  508. {
  509. if (mmap_state == pci_mmap_io)
  510. return -EINVAL;
  511. /*
  512. * Mark this as IO
  513. */
  514. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  515. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  516. vma->vm_end - vma->vm_start,
  517. vma->vm_page_prot))
  518. return -EAGAIN;
  519. return 0;
  520. }
  521. void __init pci_map_io_early(unsigned long pfn)
  522. {
  523. struct map_desc pci_io_desc = {
  524. .virtual = PCI_IO_VIRT_BASE,
  525. .type = MT_DEVICE,
  526. .length = SZ_64K,
  527. };
  528. pci_io_desc.pfn = pfn;
  529. iotable_init(&pci_io_desc, 1);
  530. }