ufshcd-pltfrm.txt 3.0 KB

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  1. * Universal Flash Storage (UFS) Host Controller
  2. UFSHC nodes are defined to describe on-chip UFS host controllers.
  3. Each UFS controller instance should have its own node.
  4. Required properties:
  5. - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may
  6. also list one or more of the following:
  7. "qcom,msm8994-ufshc"
  8. "qcom,msm8996-ufshc"
  9. "qcom,ufshc"
  10. - interrupts : <interrupt mapping for UFS host controller IRQ>
  11. - reg : <registers mapping>
  12. Optional properties:
  13. - phys : phandle to UFS PHY node
  14. - phy-names : the string "ufsphy" when is found in a node, along
  15. with "phys" attribute, provides phandle to UFS PHY node
  16. - vdd-hba-supply : phandle to UFS host controller supply regulator node
  17. - vcc-supply : phandle to VCC supply regulator node
  18. - vccq-supply : phandle to VCCQ supply regulator node
  19. - vccq2-supply : phandle to VCCQ2 supply regulator node
  20. - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
  21. or 2.7-3.6V. This boolean property when set, specifies
  22. to use low voltage range of 1.7-1.95V. Note for external
  23. UFS cards this property is invalid and valid VCC range is
  24. always 2.7-3.6V.
  25. - vcc-max-microamp : specifies max. load that can be drawn from vcc supply
  26. - vccq-max-microamp : specifies max. load that can be drawn from vccq supply
  27. - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
  28. - <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
  29. - clocks : List of phandle and clock specifier pairs
  30. - clock-names : List of clock input name strings sorted in the same
  31. order as the clocks property.
  32. - freq-table-hz : Array of <min max> operating frequencies stored in the same
  33. order as the clocks property. If this property is not
  34. defined or a value in the array is "0" then it is assumed
  35. that the frequency is set by the parent clock or a
  36. fixed rate clock source.
  37. -lanes-per-direction : number of lanes available per direction - either 1 or 2.
  38. Note that it is assume same number of lanes is used both
  39. directions at once. If not specified, default is 2 lanes per direction.
  40. Note: If above properties are not defined it can be assumed that the supply
  41. regulators or clocks are always on.
  42. Example:
  43. ufshc@0xfc598000 {
  44. compatible = "jedec,ufs-1.1";
  45. reg = <0xfc598000 0x800>;
  46. interrupts = <0 28 0>;
  47. vdd-hba-supply = <&xxx_reg0>;
  48. vdd-hba-fixed-regulator;
  49. vcc-supply = <&xxx_reg1>;
  50. vcc-supply-1p8;
  51. vccq-supply = <&xxx_reg2>;
  52. vccq2-supply = <&xxx_reg3>;
  53. vcc-max-microamp = 500000;
  54. vccq-max-microamp = 200000;
  55. vccq2-max-microamp = 200000;
  56. clocks = <&core 0>, <&ref 0>, <&iface 0>;
  57. clock-names = "core_clk", "ref_clk", "iface_clk";
  58. freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
  59. phys = <&ufsphy1>;
  60. phy-names = "ufsphy";
  61. };