pmu.txt 1.7 KB

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  1. Device Tree bindings for Marvell PMU
  2. Required properties:
  3. - compatible: value should be "marvell,dove-pmu".
  4. May also include "simple-bus" if there are child devices, in which
  5. case the ranges node is required.
  6. - reg: two base addresses and sizes of the PM controller and PMU.
  7. - interrupts: single interrupt number for the PMU interrupt
  8. - interrupt-controller: must be specified as the PMU itself is an
  9. interrupt controller.
  10. - #interrupt-cells: must be 1.
  11. - #reset-cells: must be 1.
  12. - domains: sub-node containing domain descriptions
  13. Optional properties:
  14. - ranges: defines the address mapping for child devices, as per the
  15. standard property of this name. Required when compatible includes
  16. "simple-bus".
  17. Power domain descriptions are listed as child nodes of the "domains"
  18. sub-node. Each domain has the following properties:
  19. Required properties:
  20. - #power-domain-cells: must be 0.
  21. Optional properties:
  22. - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
  23. - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
  24. - resets: points to the reset manager (PMU node) and reset index.
  25. Example:
  26. pmu: power-management@d0000 {
  27. compatible = "marvell,dove-pmu";
  28. reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
  29. interrupts = <33>;
  30. interrupt-controller;
  31. #interrupt-cells = <1>;
  32. #reset-cells = <1>;
  33. domains {
  34. vpu_domain: vpu-domain {
  35. #power-domain-cells = <0>;
  36. marvell,pmu_pwr_mask = <0x00000008>;
  37. marvell,pmu_iso_mask = <0x00000001>;
  38. resets = <&pmu 16>;
  39. };
  40. gpu_domain: gpu-domain {
  41. #power-domain-cells = <0>;
  42. marvell,pmu_pwr_mask = <0x00000004>;
  43. marvell,pmu_iso_mask = <0x00000002>;
  44. resets = <&pmu 18>;
  45. };
  46. };
  47. };