ralink,rt3883-pci.txt 4.7 KB

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  1. * Mediatek/Ralink RT3883 PCI controller
  2. 1) Main node
  3. Required properties:
  4. - compatible: must be "ralink,rt3883-pci"
  5. - reg: specifies the physical base address of the controller and
  6. the length of the memory mapped region.
  7. - #address-cells: specifies the number of cells needed to encode an
  8. address. The value must be 1.
  9. - #size-cells: specifies the number of cells used to represent the size
  10. of an address. The value must be 1.
  11. - ranges: specifies the translation between child address space and parent
  12. address space
  13. Optional properties:
  14. - status: indicates the operational status of the device.
  15. Value must be either "disabled" or "okay".
  16. 2) Child nodes
  17. The main node must have two child nodes which describes the built-in
  18. interrupt controller and the PCI host bridge.
  19. a) Interrupt controller:
  20. Required properties:
  21. - interrupt-controller: identifies the node as an interrupt controller
  22. - #address-cells: specifies the number of cells needed to encode an
  23. address. The value must be 0. As such, 'interrupt-map' nodes do not
  24. have to specify a parent unit address.
  25. - #interrupt-cells: specifies the number of cells needed to encode an
  26. interrupt source. The value must be 1.
  27. - interrupt-parent: the phandle for the interrupt controller that
  28. services interrupts for this device.
  29. - interrupts: specifies the interrupt source of the parent interrupt
  30. controller. The format of the interrupt specifier depends on the
  31. parent interrupt controller.
  32. b) PCI host bridge:
  33. Required properties:
  34. - #address-cells: specifies the number of cells needed to encode an
  35. address. The value must be 0.
  36. - #size-cells: specifies the number of cells used to represent the size
  37. of an address. The value must be 2.
  38. - #interrupt-cells: specifies the number of cells needed to encode an
  39. interrupt source. The value must be 1.
  40. - device_type: must be "pci"
  41. - bus-range: PCI bus numbers covered
  42. - ranges: specifies the ranges for the PCI memory and I/O regions
  43. - interrupt-map-mask,
  44. - interrupt-map: standard PCI properties to define the mapping of the
  45. PCI interface to interrupt numbers.
  46. The PCI host bridge node migh have additional sub-nodes representing
  47. the onboard PCI devices/PCI slots. Each such sub-node must have the
  48. following mandatory properties:
  49. - reg: used only for interrupt mapping, so only the first four bytes
  50. are used to refer to the correct bus number and device number.
  51. - device_type: must be "pci"
  52. If a given sub-node represents a PCI bridge it must have following
  53. mandatory properties as well:
  54. - #address-cells: must be set to <3>
  55. - #size-cells: must set to <2>
  56. - #interrupt-cells: must be set to <1>
  57. - interrupt-map-mask,
  58. - interrupt-map: standard PCI properties to define the mapping of the
  59. PCI interface to interrupt numbers.
  60. Besides the required properties the sub-nodes may have these optional
  61. properties:
  62. - status: indicates the operational status of the sub-node.
  63. Value must be either "disabled" or "okay".
  64. 3) Example:
  65. a) SoC specific dtsi file:
  66. pci@10140000 {
  67. compatible = "ralink,rt3883-pci";
  68. reg = <0x10140000 0x20000>;
  69. #address-cells = <1>;
  70. #size-cells = <1>;
  71. ranges; /* direct mapping */
  72. status = "disabled";
  73. pciintc: interrupt-controller {
  74. interrupt-controller;
  75. #address-cells = <0>;
  76. #interrupt-cells = <1>;
  77. interrupt-parent = <&cpuintc>;
  78. interrupts = <4>;
  79. };
  80. host-bridge {
  81. #address-cells = <3>;
  82. #size-cells = <2>;
  83. #interrupt-cells = <1>;
  84. device_type = "pci";
  85. bus-range = <0 255>;
  86. ranges = <
  87. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  88. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  89. >;
  90. interrupt-map-mask = <0xf800 0 0 7>;
  91. interrupt-map = <
  92. /* IDSEL 17 */
  93. 0x8800 0 0 1 &pciintc 18
  94. 0x8800 0 0 2 &pciintc 18
  95. 0x8800 0 0 3 &pciintc 18
  96. 0x8800 0 0 4 &pciintc 18
  97. /* IDSEL 18 */
  98. 0x9000 0 0 1 &pciintc 19
  99. 0x9000 0 0 2 &pciintc 19
  100. 0x9000 0 0 3 &pciintc 19
  101. 0x9000 0 0 4 &pciintc 19
  102. >;
  103. pci-bridge@1 {
  104. reg = <0x0800 0 0 0 0>;
  105. device_type = "pci";
  106. #interrupt-cells = <1>;
  107. #address-cells = <3>;
  108. #size-cells = <2>;
  109. interrupt-map-mask = <0x0 0 0 0>;
  110. interrupt-map = <0x0 0 0 0 &pciintc 20>;
  111. status = "disabled";
  112. };
  113. pci-slot@17 {
  114. reg = <0x8800 0 0 0 0>;
  115. device_type = "pci";
  116. status = "disabled";
  117. };
  118. pci-slot@18 {
  119. reg = <0x9000 0 0 0 0>;
  120. device_type = "pci";
  121. status = "disabled";
  122. };
  123. };
  124. };
  125. b) Board specific dts file:
  126. pci@10140000 {
  127. status = "okay";
  128. host-bridge {
  129. pci-bridge@1 {
  130. status = "okay";
  131. };
  132. };
  133. };