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- NVIDIA Tegra ACONNECT Bus
- The Tegra ACONNECT bus is an AXI switch which is used to connnect various
- components inside the Audio Processing Engine (APE). All CPU accesses to
- the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
- Required properties:
- - compatible: Must be "nvidia,tegra210-aconnect".
- - clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
- and APE interface clock (TEGRA210_CLK_APB2APE).
- - clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
- 'clocks' entries.
- - power-domains: Must contain a phandle that points to the audio powergate
- (namely 'aud') for Tegra210.
- - #address-cells: The number of cells used to represent physical base addresses
- in the aconnect address space. Should be 1.
- - #size-cells: The number of cells used to represent the size of an address
- range in the aconnect address space. Should be 1.
- - ranges: Mapping of the aconnect address space to the CPU address space.
- All devices accessed via the ACONNNECT are described by child-nodes.
- Example:
- aconnect@702c0000 {
- compatible = "nvidia,tegra210-aconnect";
- clocks = <&tegra_car TEGRA210_CLK_APE>,
- <&tegra_car TEGRA210_CLK_APB2APE>;
- clock-names = "ape", "apb2ape";
- power-domains = <&pd_audio>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
- status = "disabled";
- child1 {
- ...
- };
- child2 {
- ...
- };
- };
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