ti-gpmc.txt 4.2 KB

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  1. GPMC (General Purpose Memory Controller):
  2. =========================================
  3. GPMC is an unified memory controller dedicated to interfacing external
  4. memory devices like
  5. * Asynchronous SRAM like memories and application specific integrated
  6. circuit devices.
  7. * Asynchronous, synchronous, and page mode burst NOR flash devices
  8. NAND flash
  9. * Pseudo-SRAM devices
  10. GPMC is found on Texas Instruments SoC's (OMAP based)
  11. IP details: http://www.ti.com/lit/pdf/spruh73 section 7.1
  12. GPMC generic timing calculation:
  13. ================================
  14. GPMC has certain timings that has to be programmed for proper
  15. functioning of the peripheral, while peripheral has another set of
  16. timings. To have peripheral work with gpmc, peripheral timings has to
  17. be translated to the form gpmc can understand. The way it has to be
  18. translated depends on the connected peripheral. Also there is a
  19. dependency for certain gpmc timings on gpmc clock frequency. Hence a
  20. generic timing routine was developed to achieve above requirements.
  21. Generic routine provides a generic method to calculate gpmc timings
  22. from gpmc peripheral timings. struct gpmc_device_timings fields has to
  23. be updated with timings from the datasheet of the peripheral that is
  24. connected to gpmc. A few of the peripheral timings can be fed either
  25. in time or in cycles, provision to handle this scenario has been
  26. provided (refer struct gpmc_device_timings definition). It may so
  27. happen that timing as specified by peripheral datasheet is not present
  28. in timing structure, in this scenario, try to correlate peripheral
  29. timing to the one available. If that doesn't work, try to add a new
  30. field as required by peripheral, educate generic timing routine to
  31. handle it, make sure that it does not break any of the existing.
  32. Then there may be cases where peripheral datasheet doesn't mention
  33. certain fields of struct gpmc_device_timings, zero those entries.
  34. Generic timing routine has been verified to work properly on
  35. multiple onenand's and tusb6010 peripherals.
  36. A word of caution: generic timing routine has been developed based
  37. on understanding of gpmc timings, peripheral timings, available
  38. custom timing routines, a kind of reverse engineering without
  39. most of the datasheets & hardware (to be exact none of those supported
  40. in mainline having custom timing routine) and by simulation.
  41. gpmc timing dependency on peripheral timings:
  42. [<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]
  43. 1. common
  44. cs_on: t_ceasu
  45. adv_on: t_avdasu, t_ceavd
  46. 2. sync common
  47. sync_clk: clk
  48. page_burst_access: t_bacc
  49. clk_activation: t_ces, t_avds
  50. 3. read async muxed
  51. adv_rd_off: t_avdp_r
  52. oe_on: t_oeasu, t_aavdh
  53. access: t_iaa, t_oe, t_ce, t_aa
  54. rd_cycle: t_rd_cycle, t_cez_r, t_oez
  55. 4. read async non-muxed
  56. adv_rd_off: t_avdp_r
  57. oe_on: t_oeasu
  58. access: t_iaa, t_oe, t_ce, t_aa
  59. rd_cycle: t_rd_cycle, t_cez_r, t_oez
  60. 5. read sync muxed
  61. adv_rd_off: t_avdp_r, t_avdh
  62. oe_on: t_oeasu, t_ach, cyc_aavdh_oe
  63. access: t_iaa, cyc_iaa, cyc_oe
  64. rd_cycle: t_cez_r, t_oez, t_ce_rdyz
  65. 6. read sync non-muxed
  66. adv_rd_off: t_avdp_r
  67. oe_on: t_oeasu
  68. access: t_iaa, cyc_iaa, cyc_oe
  69. rd_cycle: t_cez_r, t_oez, t_ce_rdyz
  70. 7. write async muxed
  71. adv_wr_off: t_avdp_w
  72. we_on, wr_data_mux_bus: t_weasu, t_aavdh, cyc_aavhd_we
  73. we_off: t_wpl
  74. cs_wr_off: t_wph
  75. wr_cycle: t_cez_w, t_wr_cycle
  76. 8. write async non-muxed
  77. adv_wr_off: t_avdp_w
  78. we_on, wr_data_mux_bus: t_weasu
  79. we_off: t_wpl
  80. cs_wr_off: t_wph
  81. wr_cycle: t_cez_w, t_wr_cycle
  82. 9. write sync muxed
  83. adv_wr_off: t_avdp_w, t_avdh
  84. we_on, wr_data_mux_bus: t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we
  85. we_off: t_wpl, cyc_wpl
  86. cs_wr_off: t_wph
  87. wr_cycle: t_cez_w, t_ce_rdyz
  88. 10. write sync non-muxed
  89. adv_wr_off: t_avdp_w
  90. we_on, wr_data_mux_bus: t_weasu, t_rdyo
  91. we_off: t_wpl, cyc_wpl
  92. cs_wr_off: t_wph
  93. wr_cycle: t_cez_w, t_ce_rdyz
  94. Note: Many of gpmc timings are dependent on other gpmc timings (a few
  95. gpmc timings purely dependent on other gpmc timings, a reason that
  96. some of the gpmc timings are missing above), and it will result in
  97. indirect dependency of peripheral timings to gpmc timings other than
  98. mentioned above, refer timing routine for more details. To know what
  99. these peripheral timings correspond to, please see explanations in
  100. struct gpmc_device_timings definition. And for gpmc timings refer
  101. IP details (link above).