fw.c 38 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. * Copyright(c) 2016 Intel Deutschland GmbH
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of version 2 of the GNU General Public License as
  14. * published by the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  24. * USA
  25. *
  26. * The full GNU General Public License is included in this distribution
  27. * in the file called COPYING.
  28. *
  29. * Contact Information:
  30. * Intel Linux Wireless <linuxwifi@intel.com>
  31. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32. *
  33. * BSD LICENSE
  34. *
  35. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  36. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37. * All rights reserved.
  38. *
  39. * Redistribution and use in source and binary forms, with or without
  40. * modification, are permitted provided that the following conditions
  41. * are met:
  42. *
  43. * * Redistributions of source code must retain the above copyright
  44. * notice, this list of conditions and the following disclaimer.
  45. * * Redistributions in binary form must reproduce the above copyright
  46. * notice, this list of conditions and the following disclaimer in
  47. * the documentation and/or other materials provided with the
  48. * distribution.
  49. * * Neither the name Intel Corporation nor the names of its
  50. * contributors may be used to endorse or promote products derived
  51. * from this software without specific prior written permission.
  52. *
  53. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  54. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  55. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  56. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  57. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  58. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  59. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  60. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  61. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  62. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  63. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  64. *
  65. *****************************************************************************/
  66. #include <net/mac80211.h>
  67. #include <linux/netdevice.h>
  68. #include <linux/acpi.h>
  69. #include "iwl-trans.h"
  70. #include "iwl-op-mode.h"
  71. #include "iwl-fw.h"
  72. #include "iwl-debug.h"
  73. #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
  74. #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
  75. #include "iwl-prph.h"
  76. #include "iwl-eeprom-parse.h"
  77. #include "mvm.h"
  78. #include "fw-dbg.h"
  79. #include "iwl-phy-db.h"
  80. #define MVM_UCODE_ALIVE_TIMEOUT HZ
  81. #define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
  82. #define UCODE_VALID_OK cpu_to_le32(0x1)
  83. struct iwl_mvm_alive_data {
  84. bool valid;
  85. u32 scd_base_addr;
  86. };
  87. static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
  88. {
  89. struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
  90. .valid = cpu_to_le32(valid_tx_ant),
  91. };
  92. IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
  93. return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
  94. sizeof(tx_ant_cmd), &tx_ant_cmd);
  95. }
  96. static int iwl_send_rss_cfg_cmd(struct iwl_mvm *mvm)
  97. {
  98. int i;
  99. struct iwl_rss_config_cmd cmd = {
  100. .flags = cpu_to_le32(IWL_RSS_ENABLE),
  101. .hash_mask = IWL_RSS_HASH_TYPE_IPV4_TCP |
  102. IWL_RSS_HASH_TYPE_IPV4_UDP |
  103. IWL_RSS_HASH_TYPE_IPV4_PAYLOAD |
  104. IWL_RSS_HASH_TYPE_IPV6_TCP |
  105. IWL_RSS_HASH_TYPE_IPV6_UDP |
  106. IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
  107. };
  108. if (mvm->trans->num_rx_queues == 1)
  109. return 0;
  110. /* Do not direct RSS traffic to Q 0 which is our fallback queue */
  111. for (i = 0; i < ARRAY_SIZE(cmd.indirection_table); i++)
  112. cmd.indirection_table[i] =
  113. 1 + (i % (mvm->trans->num_rx_queues - 1));
  114. netdev_rss_key_fill(cmd.secret_key, sizeof(cmd.secret_key));
  115. return iwl_mvm_send_cmd_pdu(mvm, RSS_CONFIG_CMD, 0, sizeof(cmd), &cmd);
  116. }
  117. static int iwl_mvm_send_dqa_cmd(struct iwl_mvm *mvm)
  118. {
  119. struct iwl_dqa_enable_cmd dqa_cmd = {
  120. .cmd_queue = cpu_to_le32(IWL_MVM_DQA_CMD_QUEUE),
  121. };
  122. u32 cmd_id = iwl_cmd_id(DQA_ENABLE_CMD, DATA_PATH_GROUP, 0);
  123. int ret;
  124. ret = iwl_mvm_send_cmd_pdu(mvm, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd);
  125. if (ret)
  126. IWL_ERR(mvm, "Failed to send DQA enabling command: %d\n", ret);
  127. else
  128. IWL_DEBUG_FW(mvm, "Working in DQA mode\n");
  129. return ret;
  130. }
  131. void iwl_free_fw_paging(struct iwl_mvm *mvm)
  132. {
  133. int i;
  134. if (!mvm->fw_paging_db[0].fw_paging_block)
  135. return;
  136. for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
  137. struct iwl_fw_paging *paging = &mvm->fw_paging_db[i];
  138. if (!paging->fw_paging_block) {
  139. IWL_DEBUG_FW(mvm,
  140. "Paging: block %d already freed, continue to next page\n",
  141. i);
  142. continue;
  143. }
  144. dma_unmap_page(mvm->trans->dev, paging->fw_paging_phys,
  145. paging->fw_paging_size, DMA_BIDIRECTIONAL);
  146. __free_pages(paging->fw_paging_block,
  147. get_order(paging->fw_paging_size));
  148. paging->fw_paging_block = NULL;
  149. }
  150. kfree(mvm->trans->paging_download_buf);
  151. mvm->trans->paging_download_buf = NULL;
  152. mvm->trans->paging_db = NULL;
  153. memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
  154. }
  155. static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
  156. {
  157. int sec_idx, idx;
  158. u32 offset = 0;
  159. /*
  160. * find where is the paging image start point:
  161. * if CPU2 exist and it's in paging format, then the image looks like:
  162. * CPU1 sections (2 or more)
  163. * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
  164. * CPU2 sections (not paged)
  165. * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
  166. * non paged to CPU2 paging sec
  167. * CPU2 paging CSS
  168. * CPU2 paging image (including instruction and data)
  169. */
  170. for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
  171. if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
  172. sec_idx++;
  173. break;
  174. }
  175. }
  176. /*
  177. * If paging is enabled there should be at least 2 more sections left
  178. * (one for CSS and one for Paging data)
  179. */
  180. if (sec_idx >= ARRAY_SIZE(image->sec) - 1) {
  181. IWL_ERR(mvm, "Paging: Missing CSS and/or paging sections\n");
  182. iwl_free_fw_paging(mvm);
  183. return -EINVAL;
  184. }
  185. /* copy the CSS block to the dram */
  186. IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
  187. sec_idx);
  188. memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
  189. image->sec[sec_idx].data,
  190. mvm->fw_paging_db[0].fw_paging_size);
  191. dma_sync_single_for_device(mvm->trans->dev,
  192. mvm->fw_paging_db[0].fw_paging_phys,
  193. mvm->fw_paging_db[0].fw_paging_size,
  194. DMA_BIDIRECTIONAL);
  195. IWL_DEBUG_FW(mvm,
  196. "Paging: copied %d CSS bytes to first block\n",
  197. mvm->fw_paging_db[0].fw_paging_size);
  198. sec_idx++;
  199. /*
  200. * copy the paging blocks to the dram
  201. * loop index start from 1 since that CSS block already copied to dram
  202. * and CSS index is 0.
  203. * loop stop at num_of_paging_blk since that last block is not full.
  204. */
  205. for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
  206. struct iwl_fw_paging *block = &mvm->fw_paging_db[idx];
  207. memcpy(page_address(block->fw_paging_block),
  208. image->sec[sec_idx].data + offset,
  209. block->fw_paging_size);
  210. dma_sync_single_for_device(mvm->trans->dev,
  211. block->fw_paging_phys,
  212. block->fw_paging_size,
  213. DMA_BIDIRECTIONAL);
  214. IWL_DEBUG_FW(mvm,
  215. "Paging: copied %d paging bytes to block %d\n",
  216. mvm->fw_paging_db[idx].fw_paging_size,
  217. idx);
  218. offset += mvm->fw_paging_db[idx].fw_paging_size;
  219. }
  220. /* copy the last paging block */
  221. if (mvm->num_of_pages_in_last_blk > 0) {
  222. struct iwl_fw_paging *block = &mvm->fw_paging_db[idx];
  223. memcpy(page_address(block->fw_paging_block),
  224. image->sec[sec_idx].data + offset,
  225. FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
  226. dma_sync_single_for_device(mvm->trans->dev,
  227. block->fw_paging_phys,
  228. block->fw_paging_size,
  229. DMA_BIDIRECTIONAL);
  230. IWL_DEBUG_FW(mvm,
  231. "Paging: copied %d pages in the last block %d\n",
  232. mvm->num_of_pages_in_last_blk, idx);
  233. }
  234. return 0;
  235. }
  236. static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
  237. const struct fw_img *image)
  238. {
  239. struct page *block;
  240. dma_addr_t phys = 0;
  241. int blk_idx = 0;
  242. int order, num_of_pages;
  243. int dma_enabled;
  244. if (mvm->fw_paging_db[0].fw_paging_block)
  245. return 0;
  246. dma_enabled = is_device_dma_capable(mvm->trans->dev);
  247. /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
  248. BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
  249. num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
  250. mvm->num_of_paging_blk = ((num_of_pages - 1) /
  251. NUM_OF_PAGE_PER_GROUP) + 1;
  252. mvm->num_of_pages_in_last_blk =
  253. num_of_pages -
  254. NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
  255. IWL_DEBUG_FW(mvm,
  256. "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
  257. mvm->num_of_paging_blk,
  258. mvm->num_of_pages_in_last_blk);
  259. /* allocate block of 4Kbytes for paging CSS */
  260. order = get_order(FW_PAGING_SIZE);
  261. block = alloc_pages(GFP_KERNEL, order);
  262. if (!block) {
  263. /* free all the previous pages since we failed */
  264. iwl_free_fw_paging(mvm);
  265. return -ENOMEM;
  266. }
  267. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  268. mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
  269. if (dma_enabled) {
  270. phys = dma_map_page(mvm->trans->dev, block, 0,
  271. PAGE_SIZE << order, DMA_BIDIRECTIONAL);
  272. if (dma_mapping_error(mvm->trans->dev, phys)) {
  273. /*
  274. * free the previous pages and the current one since
  275. * we failed to map_page.
  276. */
  277. iwl_free_fw_paging(mvm);
  278. return -ENOMEM;
  279. }
  280. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  281. } else {
  282. mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG |
  283. blk_idx << BLOCK_2_EXP_SIZE;
  284. }
  285. IWL_DEBUG_FW(mvm,
  286. "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
  287. order);
  288. /*
  289. * allocate blocks in dram.
  290. * since that CSS allocated in fw_paging_db[0] loop start from index 1
  291. */
  292. for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  293. /* allocate block of PAGING_BLOCK_SIZE (32K) */
  294. order = get_order(PAGING_BLOCK_SIZE);
  295. block = alloc_pages(GFP_KERNEL, order);
  296. if (!block) {
  297. /* free all the previous pages since we failed */
  298. iwl_free_fw_paging(mvm);
  299. return -ENOMEM;
  300. }
  301. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  302. mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
  303. if (dma_enabled) {
  304. phys = dma_map_page(mvm->trans->dev, block, 0,
  305. PAGE_SIZE << order,
  306. DMA_BIDIRECTIONAL);
  307. if (dma_mapping_error(mvm->trans->dev, phys)) {
  308. /*
  309. * free the previous pages and the current one
  310. * since we failed to map_page.
  311. */
  312. iwl_free_fw_paging(mvm);
  313. return -ENOMEM;
  314. }
  315. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  316. } else {
  317. mvm->fw_paging_db[blk_idx].fw_paging_phys =
  318. PAGING_ADDR_SIG |
  319. blk_idx << BLOCK_2_EXP_SIZE;
  320. }
  321. IWL_DEBUG_FW(mvm,
  322. "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
  323. order);
  324. }
  325. return 0;
  326. }
  327. static int iwl_save_fw_paging(struct iwl_mvm *mvm,
  328. const struct fw_img *fw)
  329. {
  330. int ret;
  331. ret = iwl_alloc_fw_paging_mem(mvm, fw);
  332. if (ret)
  333. return ret;
  334. return iwl_fill_paging_mem(mvm, fw);
  335. }
  336. /* send paging cmd to FW in case CPU2 has paging image */
  337. static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
  338. {
  339. struct iwl_fw_paging_cmd paging_cmd = {
  340. .flags =
  341. cpu_to_le32(PAGING_CMD_IS_SECURED |
  342. PAGING_CMD_IS_ENABLED |
  343. (mvm->num_of_pages_in_last_blk <<
  344. PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
  345. .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
  346. .block_num = cpu_to_le32(mvm->num_of_paging_blk),
  347. };
  348. int blk_idx, size = sizeof(paging_cmd);
  349. /* A bit hard coded - but this is the old API and will be deprecated */
  350. if (!iwl_mvm_has_new_tx_api(mvm))
  351. size -= NUM_OF_FW_PAGING_BLOCKS * 4;
  352. /* loop for for all paging blocks + CSS block */
  353. for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  354. dma_addr_t addr = mvm->fw_paging_db[blk_idx].fw_paging_phys;
  355. addr = addr >> PAGE_2_EXP_SIZE;
  356. if (iwl_mvm_has_new_tx_api(mvm)) {
  357. __le64 phy_addr = cpu_to_le64(addr);
  358. paging_cmd.device_phy_addr.addr64[blk_idx] = phy_addr;
  359. } else {
  360. __le32 phy_addr = cpu_to_le32(addr);
  361. paging_cmd.device_phy_addr.addr32[blk_idx] = phy_addr;
  362. }
  363. }
  364. return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
  365. IWL_ALWAYS_LONG_GROUP, 0),
  366. 0, size, &paging_cmd);
  367. }
  368. /*
  369. * Send paging item cmd to FW in case CPU2 has paging image
  370. */
  371. static int iwl_trans_get_paging_item(struct iwl_mvm *mvm)
  372. {
  373. int ret;
  374. struct iwl_fw_get_item_cmd fw_get_item_cmd = {
  375. .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING),
  376. };
  377. struct iwl_fw_get_item_resp *item_resp;
  378. struct iwl_host_cmd cmd = {
  379. .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0),
  380. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  381. .data = { &fw_get_item_cmd, },
  382. };
  383. cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd);
  384. ret = iwl_mvm_send_cmd(mvm, &cmd);
  385. if (ret) {
  386. IWL_ERR(mvm,
  387. "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n",
  388. ret);
  389. return ret;
  390. }
  391. item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data;
  392. if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) {
  393. IWL_ERR(mvm,
  394. "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n",
  395. le32_to_cpu(item_resp->item_id));
  396. ret = -EIO;
  397. goto exit;
  398. }
  399. /* Add an extra page for headers */
  400. mvm->trans->paging_download_buf = kzalloc(PAGING_BLOCK_SIZE +
  401. FW_PAGING_SIZE,
  402. GFP_KERNEL);
  403. if (!mvm->trans->paging_download_buf) {
  404. ret = -ENOMEM;
  405. goto exit;
  406. }
  407. mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val);
  408. mvm->trans->paging_db = mvm->fw_paging_db;
  409. IWL_DEBUG_FW(mvm,
  410. "Paging: got paging request address (paging_req_addr 0x%08x)\n",
  411. mvm->trans->paging_req_addr);
  412. exit:
  413. iwl_free_resp(&cmd);
  414. return ret;
  415. }
  416. static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
  417. struct iwl_rx_packet *pkt, void *data)
  418. {
  419. struct iwl_mvm *mvm =
  420. container_of(notif_wait, struct iwl_mvm, notif_wait);
  421. struct iwl_mvm_alive_data *alive_data = data;
  422. struct mvm_alive_resp_ver1 *palive1;
  423. struct mvm_alive_resp_ver2 *palive2;
  424. struct mvm_alive_resp *palive;
  425. if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
  426. palive1 = (void *)pkt->data;
  427. mvm->support_umac_log = false;
  428. mvm->error_event_table =
  429. le32_to_cpu(palive1->error_event_table_ptr);
  430. mvm->log_event_table =
  431. le32_to_cpu(palive1->log_event_table_ptr);
  432. alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
  433. alive_data->valid = le16_to_cpu(palive1->status) ==
  434. IWL_ALIVE_STATUS_OK;
  435. IWL_DEBUG_FW(mvm,
  436. "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  437. le16_to_cpu(palive1->status), palive1->ver_type,
  438. palive1->ver_subtype, palive1->flags);
  439. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
  440. palive2 = (void *)pkt->data;
  441. mvm->error_event_table =
  442. le32_to_cpu(palive2->error_event_table_ptr);
  443. mvm->log_event_table =
  444. le32_to_cpu(palive2->log_event_table_ptr);
  445. alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
  446. mvm->umac_error_event_table =
  447. le32_to_cpu(palive2->error_info_addr);
  448. mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
  449. mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
  450. alive_data->valid = le16_to_cpu(palive2->status) ==
  451. IWL_ALIVE_STATUS_OK;
  452. if (mvm->umac_error_event_table)
  453. mvm->support_umac_log = true;
  454. IWL_DEBUG_FW(mvm,
  455. "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  456. le16_to_cpu(palive2->status), palive2->ver_type,
  457. palive2->ver_subtype, palive2->flags);
  458. IWL_DEBUG_FW(mvm,
  459. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  460. palive2->umac_major, palive2->umac_minor);
  461. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
  462. palive = (void *)pkt->data;
  463. mvm->error_event_table =
  464. le32_to_cpu(palive->error_event_table_ptr);
  465. mvm->log_event_table =
  466. le32_to_cpu(palive->log_event_table_ptr);
  467. alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
  468. mvm->umac_error_event_table =
  469. le32_to_cpu(palive->error_info_addr);
  470. mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
  471. mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
  472. alive_data->valid = le16_to_cpu(palive->status) ==
  473. IWL_ALIVE_STATUS_OK;
  474. if (mvm->umac_error_event_table)
  475. mvm->support_umac_log = true;
  476. IWL_DEBUG_FW(mvm,
  477. "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  478. le16_to_cpu(palive->status), palive->ver_type,
  479. palive->ver_subtype, palive->flags);
  480. IWL_DEBUG_FW(mvm,
  481. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  482. le32_to_cpu(palive->umac_major),
  483. le32_to_cpu(palive->umac_minor));
  484. }
  485. return true;
  486. }
  487. static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
  488. struct iwl_rx_packet *pkt, void *data)
  489. {
  490. struct iwl_phy_db *phy_db = data;
  491. if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
  492. WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
  493. return true;
  494. }
  495. WARN_ON(iwl_phy_db_set_section(phy_db, pkt));
  496. return false;
  497. }
  498. static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
  499. enum iwl_ucode_type ucode_type)
  500. {
  501. struct iwl_notification_wait alive_wait;
  502. struct iwl_mvm_alive_data alive_data;
  503. const struct fw_img *fw;
  504. int ret, i;
  505. enum iwl_ucode_type old_type = mvm->cur_ucode;
  506. static const u16 alive_cmd[] = { MVM_ALIVE };
  507. struct iwl_sf_region st_fwrd_space;
  508. if (ucode_type == IWL_UCODE_REGULAR &&
  509. iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE) &&
  510. !(fw_has_capa(&mvm->fw->ucode_capa,
  511. IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED)))
  512. fw = iwl_get_ucode_image(mvm->fw, IWL_UCODE_REGULAR_USNIFFER);
  513. else
  514. fw = iwl_get_ucode_image(mvm->fw, ucode_type);
  515. if (WARN_ON(!fw))
  516. return -EINVAL;
  517. mvm->cur_ucode = ucode_type;
  518. mvm->ucode_loaded = false;
  519. iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
  520. alive_cmd, ARRAY_SIZE(alive_cmd),
  521. iwl_alive_fn, &alive_data);
  522. ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
  523. if (ret) {
  524. mvm->cur_ucode = old_type;
  525. iwl_remove_notification(&mvm->notif_wait, &alive_wait);
  526. return ret;
  527. }
  528. /*
  529. * Some things may run in the background now, but we
  530. * just wait for the ALIVE notification here.
  531. */
  532. ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
  533. MVM_UCODE_ALIVE_TIMEOUT);
  534. if (ret) {
  535. if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
  536. IWL_ERR(mvm,
  537. "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
  538. iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
  539. iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
  540. mvm->cur_ucode = old_type;
  541. return ret;
  542. }
  543. if (!alive_data.valid) {
  544. IWL_ERR(mvm, "Loaded ucode is not valid!\n");
  545. mvm->cur_ucode = old_type;
  546. return -EIO;
  547. }
  548. /*
  549. * update the sdio allocation according to the pointer we get in the
  550. * alive notification.
  551. */
  552. st_fwrd_space.addr = mvm->sf_space.addr;
  553. st_fwrd_space.size = mvm->sf_space.size;
  554. ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
  555. if (ret) {
  556. IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
  557. return ret;
  558. }
  559. iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
  560. /*
  561. * configure and operate fw paging mechanism.
  562. * driver configures the paging flow only once, CPU2 paging image
  563. * included in the IWL_UCODE_INIT image.
  564. */
  565. if (fw->paging_mem_size) {
  566. /*
  567. * When dma is not enabled, the driver needs to copy / write
  568. * the downloaded / uploaded page to / from the smem.
  569. * This gets the location of the place were the pages are
  570. * stored.
  571. */
  572. if (!is_device_dma_capable(mvm->trans->dev)) {
  573. ret = iwl_trans_get_paging_item(mvm);
  574. if (ret) {
  575. IWL_ERR(mvm, "failed to get FW paging item\n");
  576. return ret;
  577. }
  578. }
  579. ret = iwl_save_fw_paging(mvm, fw);
  580. if (ret) {
  581. IWL_ERR(mvm, "failed to save the FW paging image\n");
  582. return ret;
  583. }
  584. ret = iwl_send_paging_cmd(mvm, fw);
  585. if (ret) {
  586. IWL_ERR(mvm, "failed to send the paging cmd\n");
  587. iwl_free_fw_paging(mvm);
  588. return ret;
  589. }
  590. }
  591. /*
  592. * Note: all the queues are enabled as part of the interface
  593. * initialization, but in firmware restart scenarios they
  594. * could be stopped, so wake them up. In firmware restart,
  595. * mac80211 will have the queues stopped as well until the
  596. * reconfiguration completes. During normal startup, they
  597. * will be empty.
  598. */
  599. memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
  600. if (iwl_mvm_is_dqa_supported(mvm))
  601. mvm->queue_info[IWL_MVM_DQA_CMD_QUEUE].hw_queue_refcount = 1;
  602. else
  603. mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1;
  604. for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
  605. atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
  606. mvm->ucode_loaded = true;
  607. return 0;
  608. }
  609. static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
  610. {
  611. struct iwl_phy_cfg_cmd phy_cfg_cmd;
  612. enum iwl_ucode_type ucode_type = mvm->cur_ucode;
  613. /* Set parameters */
  614. phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
  615. phy_cfg_cmd.calib_control.event_trigger =
  616. mvm->fw->default_calib[ucode_type].event_trigger;
  617. phy_cfg_cmd.calib_control.flow_trigger =
  618. mvm->fw->default_calib[ucode_type].flow_trigger;
  619. IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
  620. phy_cfg_cmd.phy_cfg);
  621. return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
  622. sizeof(phy_cfg_cmd), &phy_cfg_cmd);
  623. }
  624. int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
  625. {
  626. struct iwl_notification_wait calib_wait;
  627. static const u16 init_complete[] = {
  628. INIT_COMPLETE_NOTIF,
  629. CALIB_RES_NOTIF_PHY_DB
  630. };
  631. int ret;
  632. lockdep_assert_held(&mvm->mutex);
  633. if (WARN_ON_ONCE(mvm->calibrating))
  634. return 0;
  635. iwl_init_notification_wait(&mvm->notif_wait,
  636. &calib_wait,
  637. init_complete,
  638. ARRAY_SIZE(init_complete),
  639. iwl_wait_phy_db_entry,
  640. mvm->phy_db);
  641. /* Will also start the device */
  642. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
  643. if (ret) {
  644. IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
  645. goto error;
  646. }
  647. ret = iwl_send_bt_init_conf(mvm);
  648. if (ret)
  649. goto error;
  650. /* Read the NVM only at driver load time, no need to do this twice */
  651. if (read_nvm) {
  652. /* Read nvm */
  653. ret = iwl_nvm_init(mvm, true);
  654. if (ret) {
  655. IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
  656. goto error;
  657. }
  658. }
  659. /* In case we read the NVM from external file, load it to the NIC */
  660. if (mvm->nvm_file_name)
  661. iwl_mvm_load_nvm_to_nic(mvm);
  662. ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
  663. WARN_ON(ret);
  664. /*
  665. * abort after reading the nvm in case RF Kill is on, we will complete
  666. * the init seq later when RF kill will switch to off
  667. */
  668. if (iwl_mvm_is_radio_hw_killed(mvm)) {
  669. IWL_DEBUG_RF_KILL(mvm,
  670. "jump over all phy activities due to RF kill\n");
  671. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  672. ret = 1;
  673. goto out;
  674. }
  675. mvm->calibrating = true;
  676. /* Send TX valid antennas before triggering calibrations */
  677. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  678. if (ret)
  679. goto error;
  680. /*
  681. * Send phy configurations command to init uCode
  682. * to start the 16.0 uCode init image internal calibrations.
  683. */
  684. ret = iwl_send_phy_cfg_cmd(mvm);
  685. if (ret) {
  686. IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
  687. ret);
  688. goto error;
  689. }
  690. /*
  691. * Some things may run in the background now, but we
  692. * just wait for the calibration complete notification.
  693. */
  694. ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
  695. MVM_UCODE_CALIB_TIMEOUT);
  696. if (ret && iwl_mvm_is_radio_hw_killed(mvm)) {
  697. IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
  698. ret = 1;
  699. }
  700. goto out;
  701. error:
  702. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  703. out:
  704. mvm->calibrating = false;
  705. if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
  706. /* we want to debug INIT and we have no NVM - fake */
  707. mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
  708. sizeof(struct ieee80211_channel) +
  709. sizeof(struct ieee80211_rate),
  710. GFP_KERNEL);
  711. if (!mvm->nvm_data)
  712. return -ENOMEM;
  713. mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
  714. mvm->nvm_data->bands[0].n_channels = 1;
  715. mvm->nvm_data->bands[0].n_bitrates = 1;
  716. mvm->nvm_data->bands[0].bitrates =
  717. (void *)mvm->nvm_data->channels + 1;
  718. mvm->nvm_data->bands[0].bitrates->hw_value = 10;
  719. }
  720. return ret;
  721. }
  722. static void iwl_mvm_parse_shared_mem_a000(struct iwl_mvm *mvm,
  723. struct iwl_rx_packet *pkt)
  724. {
  725. struct iwl_shared_mem_cfg *mem_cfg = (void *)pkt->data;
  726. int i;
  727. mvm->shared_mem_cfg.num_txfifo_entries =
  728. ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size);
  729. for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++)
  730. mvm->shared_mem_cfg.txfifo_size[i] =
  731. le32_to_cpu(mem_cfg->txfifo_size[i]);
  732. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
  733. mvm->shared_mem_cfg.rxfifo_size[i] =
  734. le32_to_cpu(mem_cfg->rxfifo_size[i]);
  735. BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) !=
  736. sizeof(mem_cfg->internal_txfifo_size));
  737. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
  738. i++)
  739. mvm->shared_mem_cfg.internal_txfifo_size[i] =
  740. le32_to_cpu(mem_cfg->internal_txfifo_size[i]);
  741. }
  742. static void iwl_mvm_parse_shared_mem(struct iwl_mvm *mvm,
  743. struct iwl_rx_packet *pkt)
  744. {
  745. struct iwl_shared_mem_cfg_v1 *mem_cfg = (void *)pkt->data;
  746. int i;
  747. mvm->shared_mem_cfg.num_txfifo_entries =
  748. ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size);
  749. for (i = 0; i < ARRAY_SIZE(mem_cfg->txfifo_size); i++)
  750. mvm->shared_mem_cfg.txfifo_size[i] =
  751. le32_to_cpu(mem_cfg->txfifo_size[i]);
  752. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
  753. mvm->shared_mem_cfg.rxfifo_size[i] =
  754. le32_to_cpu(mem_cfg->rxfifo_size[i]);
  755. /* new API has more data, from rxfifo_addr field and on */
  756. if (fw_has_capa(&mvm->fw->ucode_capa,
  757. IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
  758. BUILD_BUG_ON(sizeof(mvm->shared_mem_cfg.internal_txfifo_size) !=
  759. sizeof(mem_cfg->internal_txfifo_size));
  760. for (i = 0;
  761. i < ARRAY_SIZE(mvm->shared_mem_cfg.internal_txfifo_size);
  762. i++)
  763. mvm->shared_mem_cfg.internal_txfifo_size[i] =
  764. le32_to_cpu(mem_cfg->internal_txfifo_size[i]);
  765. }
  766. }
  767. static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
  768. {
  769. struct iwl_host_cmd cmd = {
  770. .flags = CMD_WANT_SKB,
  771. .data = { NULL, },
  772. .len = { 0, },
  773. };
  774. struct iwl_rx_packet *pkt;
  775. lockdep_assert_held(&mvm->mutex);
  776. if (fw_has_capa(&mvm->fw->ucode_capa,
  777. IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))
  778. cmd.id = iwl_cmd_id(SHARED_MEM_CFG_CMD, SYSTEM_GROUP, 0);
  779. else
  780. cmd.id = SHARED_MEM_CFG;
  781. if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
  782. return;
  783. pkt = cmd.resp_pkt;
  784. if (iwl_mvm_has_new_tx_api(mvm))
  785. iwl_mvm_parse_shared_mem_a000(mvm, pkt);
  786. else
  787. iwl_mvm_parse_shared_mem(mvm, pkt);
  788. IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
  789. iwl_free_resp(&cmd);
  790. }
  791. static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
  792. {
  793. struct iwl_ltr_config_cmd cmd = {
  794. .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
  795. };
  796. if (!mvm->trans->ltr_enabled)
  797. return 0;
  798. return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
  799. sizeof(cmd), &cmd);
  800. }
  801. #define ACPI_WRDS_METHOD "WRDS"
  802. #define ACPI_WRDS_WIFI (0x07)
  803. #define ACPI_WRDS_TABLE_SIZE 10
  804. struct iwl_mvm_sar_table {
  805. bool enabled;
  806. u8 values[ACPI_WRDS_TABLE_SIZE];
  807. };
  808. #ifdef CONFIG_ACPI
  809. static int iwl_mvm_sar_get_wrds(struct iwl_mvm *mvm, union acpi_object *wrds,
  810. struct iwl_mvm_sar_table *sar_table)
  811. {
  812. union acpi_object *data_pkg;
  813. u32 i;
  814. /* We need at least two packages, one for the revision and one
  815. * for the data itself. Also check that the revision is valid
  816. * (i.e. it is an integer set to 0).
  817. */
  818. if (wrds->type != ACPI_TYPE_PACKAGE ||
  819. wrds->package.count < 2 ||
  820. wrds->package.elements[0].type != ACPI_TYPE_INTEGER ||
  821. wrds->package.elements[0].integer.value != 0) {
  822. IWL_DEBUG_RADIO(mvm, "Unsupported wrds structure\n");
  823. return -EINVAL;
  824. }
  825. /* loop through all the packages to find the one for WiFi */
  826. for (i = 1; i < wrds->package.count; i++) {
  827. union acpi_object *domain;
  828. data_pkg = &wrds->package.elements[i];
  829. /* Skip anything that is not a package with the right
  830. * amount of elements (i.e. domain_type,
  831. * enabled/disabled plus the sar table size.
  832. */
  833. if (data_pkg->type != ACPI_TYPE_PACKAGE ||
  834. data_pkg->package.count != ACPI_WRDS_TABLE_SIZE + 2)
  835. continue;
  836. domain = &data_pkg->package.elements[0];
  837. if (domain->type == ACPI_TYPE_INTEGER &&
  838. domain->integer.value == ACPI_WRDS_WIFI)
  839. break;
  840. data_pkg = NULL;
  841. }
  842. if (!data_pkg)
  843. return -ENOENT;
  844. if (data_pkg->package.elements[1].type != ACPI_TYPE_INTEGER)
  845. return -EINVAL;
  846. sar_table->enabled = !!(data_pkg->package.elements[1].integer.value);
  847. for (i = 0; i < ACPI_WRDS_TABLE_SIZE; i++) {
  848. union acpi_object *entry;
  849. entry = &data_pkg->package.elements[i + 2];
  850. if ((entry->type != ACPI_TYPE_INTEGER) ||
  851. (entry->integer.value > U8_MAX))
  852. return -EINVAL;
  853. sar_table->values[i] = entry->integer.value;
  854. }
  855. return 0;
  856. }
  857. static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm,
  858. struct iwl_mvm_sar_table *sar_table)
  859. {
  860. acpi_handle root_handle;
  861. acpi_handle handle;
  862. struct acpi_buffer wrds = {ACPI_ALLOCATE_BUFFER, NULL};
  863. acpi_status status;
  864. int ret;
  865. root_handle = ACPI_HANDLE(mvm->dev);
  866. if (!root_handle) {
  867. IWL_DEBUG_RADIO(mvm,
  868. "Could not retrieve root port ACPI handle\n");
  869. return -ENOENT;
  870. }
  871. /* Get the method's handle */
  872. status = acpi_get_handle(root_handle, (acpi_string)ACPI_WRDS_METHOD,
  873. &handle);
  874. if (ACPI_FAILURE(status)) {
  875. IWL_DEBUG_RADIO(mvm, "WRDS method not found\n");
  876. return -ENOENT;
  877. }
  878. /* Call WRDS with no arguments */
  879. status = acpi_evaluate_object(handle, NULL, NULL, &wrds);
  880. if (ACPI_FAILURE(status)) {
  881. IWL_DEBUG_RADIO(mvm, "WRDS invocation failed (0x%x)\n", status);
  882. return -ENOENT;
  883. }
  884. ret = iwl_mvm_sar_get_wrds(mvm, wrds.pointer, sar_table);
  885. kfree(wrds.pointer);
  886. return ret;
  887. }
  888. #else /* CONFIG_ACPI */
  889. static int iwl_mvm_sar_get_table(struct iwl_mvm *mvm,
  890. struct iwl_mvm_sar_table *sar_table)
  891. {
  892. return -ENOENT;
  893. }
  894. #endif /* CONFIG_ACPI */
  895. static int iwl_mvm_sar_init(struct iwl_mvm *mvm)
  896. {
  897. struct iwl_mvm_sar_table sar_table;
  898. struct iwl_dev_tx_power_cmd cmd = {
  899. .v3.set_mode = cpu_to_le32(IWL_TX_POWER_MODE_SET_CHAINS),
  900. };
  901. int ret, i, j, idx;
  902. int len = sizeof(cmd);
  903. if (!fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_TX_POWER_ACK))
  904. len = sizeof(cmd.v3);
  905. ret = iwl_mvm_sar_get_table(mvm, &sar_table);
  906. if (ret < 0) {
  907. IWL_DEBUG_RADIO(mvm,
  908. "SAR BIOS table invalid or unavailable. (%d)\n",
  909. ret);
  910. /* we don't fail if the table is not available */
  911. return 0;
  912. }
  913. if (!sar_table.enabled)
  914. return 0;
  915. IWL_DEBUG_RADIO(mvm, "Sending REDUCE_TX_POWER_CMD per chain\n");
  916. BUILD_BUG_ON(IWL_NUM_CHAIN_LIMITS * IWL_NUM_SUB_BANDS !=
  917. ACPI_WRDS_TABLE_SIZE);
  918. for (i = 0; i < IWL_NUM_CHAIN_LIMITS; i++) {
  919. IWL_DEBUG_RADIO(mvm, " Chain[%d]:\n", i);
  920. for (j = 0; j < IWL_NUM_SUB_BANDS; j++) {
  921. idx = (i * IWL_NUM_SUB_BANDS) + j;
  922. cmd.v3.per_chain_restriction[i][j] =
  923. cpu_to_le16(sar_table.values[idx]);
  924. IWL_DEBUG_RADIO(mvm, " Band[%d] = %d * .125dBm\n",
  925. j, sar_table.values[idx]);
  926. }
  927. }
  928. ret = iwl_mvm_send_cmd_pdu(mvm, REDUCE_TX_POWER_CMD, 0, len, &cmd);
  929. if (ret)
  930. IWL_ERR(mvm, "failed to set per-chain TX power: %d\n", ret);
  931. return ret;
  932. }
  933. int iwl_mvm_up(struct iwl_mvm *mvm)
  934. {
  935. int ret, i;
  936. struct ieee80211_channel *chan;
  937. struct cfg80211_chan_def chandef;
  938. lockdep_assert_held(&mvm->mutex);
  939. ret = iwl_trans_start_hw(mvm->trans);
  940. if (ret)
  941. return ret;
  942. /*
  943. * If we haven't completed the run of the init ucode during
  944. * module loading, load init ucode now
  945. * (for example, if we were in RFKILL)
  946. */
  947. ret = iwl_run_init_mvm_ucode(mvm, false);
  948. if (iwlmvm_mod_params.init_dbg)
  949. return 0;
  950. if (ret) {
  951. IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
  952. /* this can't happen */
  953. if (WARN_ON(ret > 0))
  954. ret = -ERFKILL;
  955. goto error;
  956. }
  957. /*
  958. * Stop and start the transport without entering low power
  959. * mode. This will save the state of other components on the
  960. * device that are triggered by the INIT firwmare (MFUART).
  961. */
  962. _iwl_trans_stop_device(mvm->trans, false);
  963. ret = _iwl_trans_start_hw(mvm->trans, false);
  964. if (ret)
  965. goto error;
  966. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
  967. if (ret) {
  968. IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
  969. goto error;
  970. }
  971. iwl_mvm_get_shared_mem_conf(mvm);
  972. ret = iwl_mvm_sf_update(mvm, NULL, false);
  973. if (ret)
  974. IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
  975. mvm->fw_dbg_conf = FW_DBG_INVALID;
  976. /* if we have a destination, assume EARLY START */
  977. if (mvm->fw->dbg_dest_tlv)
  978. mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
  979. iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
  980. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  981. if (ret)
  982. goto error;
  983. ret = iwl_send_bt_init_conf(mvm);
  984. if (ret)
  985. goto error;
  986. /* Send phy db control command and then phy db calibration*/
  987. ret = iwl_send_phy_db_data(mvm->phy_db);
  988. if (ret)
  989. goto error;
  990. ret = iwl_send_phy_cfg_cmd(mvm);
  991. if (ret)
  992. goto error;
  993. /* Init RSS configuration */
  994. if (iwl_mvm_has_new_rx_api(mvm)) {
  995. ret = iwl_send_rss_cfg_cmd(mvm);
  996. if (ret) {
  997. IWL_ERR(mvm, "Failed to configure RSS queues: %d\n",
  998. ret);
  999. goto error;
  1000. }
  1001. }
  1002. /* init the fw <-> mac80211 STA mapping */
  1003. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  1004. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  1005. mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
  1006. /* reset quota debouncing buffer - 0xff will yield invalid data */
  1007. memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
  1008. /* Enable DQA-mode if required */
  1009. if (iwl_mvm_is_dqa_supported(mvm)) {
  1010. ret = iwl_mvm_send_dqa_cmd(mvm);
  1011. if (ret)
  1012. goto error;
  1013. } else {
  1014. IWL_DEBUG_FW(mvm, "Working in non-DQA mode\n");
  1015. }
  1016. /* Add auxiliary station for scanning */
  1017. ret = iwl_mvm_add_aux_sta(mvm);
  1018. if (ret)
  1019. goto error;
  1020. /* Add all the PHY contexts */
  1021. chan = &mvm->hw->wiphy->bands[NL80211_BAND_2GHZ]->channels[0];
  1022. cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
  1023. for (i = 0; i < NUM_PHY_CTX; i++) {
  1024. /*
  1025. * The channel used here isn't relevant as it's
  1026. * going to be overwritten in the other flows.
  1027. * For now use the first channel we have.
  1028. */
  1029. ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
  1030. &chandef, 1, 1);
  1031. if (ret)
  1032. goto error;
  1033. }
  1034. #ifdef CONFIG_THERMAL
  1035. if (iwl_mvm_is_tt_in_fw(mvm)) {
  1036. /* in order to give the responsibility of ct-kill and
  1037. * TX backoff to FW we need to send empty temperature reporting
  1038. * cmd during init time
  1039. */
  1040. iwl_mvm_send_temp_report_ths_cmd(mvm);
  1041. } else {
  1042. /* Initialize tx backoffs to the minimal possible */
  1043. iwl_mvm_tt_tx_backoff(mvm, 0);
  1044. }
  1045. /* TODO: read the budget from BIOS / Platform NVM */
  1046. if (iwl_mvm_is_ctdp_supported(mvm) && mvm->cooling_dev.cur_state > 0) {
  1047. ret = iwl_mvm_ctdp_command(mvm, CTDP_CMD_OPERATION_START,
  1048. mvm->cooling_dev.cur_state);
  1049. if (ret)
  1050. goto error;
  1051. }
  1052. #else
  1053. /* Initialize tx backoffs to the minimal possible */
  1054. iwl_mvm_tt_tx_backoff(mvm, 0);
  1055. #endif
  1056. WARN_ON(iwl_mvm_config_ltr(mvm));
  1057. ret = iwl_mvm_power_update_device(mvm);
  1058. if (ret)
  1059. goto error;
  1060. /*
  1061. * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
  1062. * anyway, so don't init MCC.
  1063. */
  1064. if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
  1065. ret = iwl_mvm_init_mcc(mvm);
  1066. if (ret)
  1067. goto error;
  1068. }
  1069. if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
  1070. mvm->scan_type = IWL_SCAN_TYPE_NOT_SET;
  1071. ret = iwl_mvm_config_scan(mvm);
  1072. if (ret)
  1073. goto error;
  1074. }
  1075. if (iwl_mvm_is_csum_supported(mvm) &&
  1076. mvm->cfg->features & NETIF_F_RXCSUM)
  1077. iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
  1078. /* allow FW/transport low power modes if not during restart */
  1079. if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
  1080. iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
  1081. ret = iwl_mvm_sar_init(mvm);
  1082. if (ret)
  1083. goto error;
  1084. IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
  1085. return 0;
  1086. error:
  1087. iwl_mvm_stop_device(mvm);
  1088. return ret;
  1089. }
  1090. int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
  1091. {
  1092. int ret, i;
  1093. lockdep_assert_held(&mvm->mutex);
  1094. ret = iwl_trans_start_hw(mvm->trans);
  1095. if (ret)
  1096. return ret;
  1097. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
  1098. if (ret) {
  1099. IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
  1100. goto error;
  1101. }
  1102. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  1103. if (ret)
  1104. goto error;
  1105. /* Send phy db control command and then phy db calibration*/
  1106. ret = iwl_send_phy_db_data(mvm->phy_db);
  1107. if (ret)
  1108. goto error;
  1109. ret = iwl_send_phy_cfg_cmd(mvm);
  1110. if (ret)
  1111. goto error;
  1112. /* init the fw <-> mac80211 STA mapping */
  1113. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  1114. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  1115. /* Add auxiliary station for scanning */
  1116. ret = iwl_mvm_add_aux_sta(mvm);
  1117. if (ret)
  1118. goto error;
  1119. return 0;
  1120. error:
  1121. iwl_mvm_stop_device(mvm);
  1122. return ret;
  1123. }
  1124. void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
  1125. struct iwl_rx_cmd_buffer *rxb)
  1126. {
  1127. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1128. struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
  1129. u32 flags = le32_to_cpu(card_state_notif->flags);
  1130. IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
  1131. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  1132. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  1133. (flags & CT_KILL_CARD_DISABLED) ?
  1134. "Reached" : "Not reached");
  1135. }
  1136. void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
  1137. struct iwl_rx_cmd_buffer *rxb)
  1138. {
  1139. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1140. struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
  1141. IWL_DEBUG_INFO(mvm,
  1142. "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
  1143. le32_to_cpu(mfuart_notif->installed_ver),
  1144. le32_to_cpu(mfuart_notif->external_ver),
  1145. le32_to_cpu(mfuart_notif->status),
  1146. le32_to_cpu(mfuart_notif->duration));
  1147. }